JPS6126227B2 - - Google Patents

Description

Detailed Description of the Invention The present invention provides a plurality of capacitive elements having a fixed capacitance value in parallel, a switching element corresponding to each of the capacitive elements, and a control signal for controlling the switching element. This invention relates to a digital capacitor that is selectively activated to switch the capacitive elements and digitally change the overall capacitance value.

Such digital capacitors can be used not only in broadcast receiver tuning devices, but also in LC oscillators and CR oscillators to digitally change their frequencies or finely adjust the frequency of crystal oscillators. Furthermore, it can also be used in a digital-to-analog converter that converts a digital capacitance value into a voltage value.

Figure ₁ shows a specific _circuit when a digital capacitor is used in the tuning circuit _of a tuning device. A digital capacitor 1 consisting of switching transistors T ₁ , T ₂ , ..., T _o is connected to the switching transistors T ₁ , T ₂ , ..., T _o and resistors R ₁ , R ₂ , T o .
. . . A digital control signal from the channel selection storage/switching signal supply circuit 2 is applied through R _o .

By the way, in order to be able to select many channels using such a digital capacitor, the number of capacitive elements will inevitably increase.
This is something I would like to change.

In view of these points, the present invention proposes a digital capacitor that can be integrated into an IC and has a high resolution.

Figure 2B shows an example of a digital capacitor integrated into an IC, with only one capacitive element and transistors T ₁₁ and T' ₁₁ serving as switching elements. Figure 2B shows a simplified planar pattern. There is. 9 in the figure is a semiconductor substrate of one conductivity type (for example, P
P-type silicon semiconductor substrate (hereinafter referred to as "P-type semiconductor substrate"), and its specific resistance is 20 to 50 Ωcm. The capacitive element C ₁ includes an opposite conductivity type region 10 (for example, an n region, hereinafter referred to as "n region") provided on one surface of the P-type semiconductor substrate 9 and an insulating layer 11 formed on the n region 10. An insulated gate transistor T is formed by using the P-type semiconductor substrate 9 on both sides of the capacitive element _C1 configured as described above. ₁₁ , forming T ₁₁ ′. Reference numerals 13 and 14 denote gate electrodes of the transistors T ₁₁ and T ₁₁ ', which are made of polysilicon or a refractory metal (heat-resistant metal) such as molybdenum, chromium, tantalum, or titanium. Reference numerals 15 and 17 indicate the sources of the transistors T ₁₁ and T ₁₁ ', and 16 and 18 indicate the drains of the transistors T _{11 and} T 11 '. It consists of an n region of impurities. Reference numeral 19 is a conductor for applying a constant DC voltage to the other electrode 12 of the capacitive element C ₁ and is formed by vapor-depositing aluminum. Conductors _20, 21 for guiding the sources 15, 17 of the transistors T 11 , T ₁₁ ′ to ground
are also made from a similar aluminum material.
A gold alloy material layer 22 is provided on the other surface of the P-type semiconductor substrate 9, and is connected to ground.

In addition, when converting into an IC, it is also possible to use the IC structure shown in FIGS. 3 and 4 in addition to the IC structure shown in FIG.

In FIG. 3, oxide film layers 41, 42, 43 for preventing parasitic transistors are formed on a P-type semiconductor substrate 9, and polycrystalline silicon layers 44, 45, 46 doped with phosphorus as an impurity are formed. Phosphorus is diffused from the polysilicon layer into the P-type semiconductor substrate 9 to form n ⁺ regions 65, 66, 67, 68.
form. Subsequently, the exposed surface of the P-type semiconductor substrate 9 and the polysilicon layers 44, 45, 46 are
An insulating film 47 with a thickness of 0.1 μm is formed on the surface, and electrodes 48 and 49 are formed by aluminum vapor deposition to form insulated gate transistors T ₁₁ and T ₁₁ ′.At the same time, an electrode 50 is formed and a capacitor C ₁ is formed. make. Electrodes 51 and 52 are insulated gate transistors
These are source extraction electrodes for T ₁₁ and T ₁₁ ′.

Next, in FIG. 4, P-type silicon is epitaxially grown to a thickness of 0.4μ on a single-crystal sapphire substrate 53 to form P-type silicon layers 54 to 58, and phosphorus is diffused thereon to form a high concentration n layer. ⁺ area 54,5
6, 58 and 0.1μ on the silicon layer.
A thick insulating film 59 is formed, and then aluminum is deposited to form gate electrodes 60 and 61 of insulated gate transistors T ₁₁ and T ₁₁ ', and similarly an electrode 62 is formed.
The capacitor _C1 is formed by making . Note that the electrodes 63 and 64 are source extraction electrodes of the insulated gate transistors T ₁₁ and T ₁₁ '.

The digital capacitor 1 can be integrated into an IC with various IC structures as described above.

By the way, in a tuned circuit, a minute frequency change Δf occurs in response to a minute capacitance change ΔC of a capacitive element.

In a tuning circuit using a digital capacitor, the frequency can only be adjusted stepwise, so a deviation of △fo from the normal frequency fo that should be tuned remains, such as fo + △fo.

Therefore, the minimum required capacitance change ΔComin is determined for the maximum allowable deviation Δfomax determined by circuit operation. Therefore, the minimum unit of a group of n capacitive elements is at least △comin
Must be a smaller value.

In _the present invention, _this value is set to △Co _, and ⁿ number _of One feature is that the value of the capacitive element is selected. In this way, the capacitance of the capacitive element group is △Co in increments of △Co~(1+2+4+...
2n ^-1 ) All capacitance values up to △Co can be achieved.
For example, if this is shown halfway, it will become clear that all capacitance values can be realized sequentially in steps of ΔCo as shown below. Note that here, the numbers in parentheses indicate the combination of capacitive elements that should be operated to obtain the capacitance value on the left.

△Co [C ₁ ] 2△Co [C ₂ ] 3△Co [C ₁ +C ₂ ] 4△Co [C ₃ ] 5△Co [C ₁ +C ₃ ] 6△Co [C ₂ +C ₃ ] 7△Co [C ₁ +C ₂ +C ₃ ] 8△Co [C ₄ ] 9△Co [C ₁ +C ₄ ] 10△Co [C ₂ +C ₄ ] 11△Co [C ₁ +C ₂ +C ₄ ] : : : Like this If the capacitance values are selected to have a certain ratio for C ₁ , C _{2 .} . . , Cn, a large number of capacitance values can be obtained. This means that it is difficult to provide a capacitive element with such a relationship with high precision.

For example, for the capacitance C, the distance between the electrodes is d, the dielectric constant of the insulating layer interposed between the electrodes is ε, and the dielectric constant in vacuum is ε.
ο, if the width of the electrode is W and the length is l, the capacitance C is generally expressed as C=εεοlW/d, so if you want to double the value of C, theoretically ε, l,
It is possible to change W and d appropriately, but changing ε is inconvenient because it means using a different IC material, and it is also difficult to change d. Therefore, when changing C, W is generally changed, but it is not appropriate to apply this method to the present device.

To explain this point in more detail, the causes of dimensional errors in the electrodes that form the capacitance are as follows:
First, a frame mask is attached to the photoresist in advance in a light baking process prior to etching.
This frame mask deforms depending on the amount of light that hits it, the light goes around to parts of the photoresist that are hidden by the frame mask, and even during etching, there are effects due to the length of the etching time, etc. be. Therefore, an error of about 1 micron is unavoidable, but in this case, the error △l in the length l direction is small and can be ignored with respect to the overall capacity, but the error △W in the width W direction is It can be easily understood from Figure 2A that this has a large effect on capacity. And this error △W
occurs in the same amount for C ₁ , C ₂ , ..., Cn, so C ₁ = εεοl (W+△W)/d C ₂ = εεοl (2W + △W)/d, and C ₂ /C ₁ = 2W+ ΔW/W+ΔW Similarly, C ₃ /C ₂ =4W+ΔW/2W+ΔW, and the ratio of Cn and Co _-1 is no longer constant, making it impossible to satisfy the above-mentioned requirements.

However, it has been found that this problem can be solved by keeping W constant and varying l.

In this way, C ₁ =εεο(W+ΔW)l/d, C ₂ =εεο(W+ΔW)×2 l/d, and C ₂ /C ₁ =2 Similarly, C ₃ /C ₂ =2 , Cn/C _o-1 =2, and the above requirements can be satisfied.

In addition, changing the length l of the capacitive element at a constant ratio in this way reduces the undesired junction capacitance C _S1 , which occurs between the n region 10 and the P-type semiconductor substrate 9, for example.
Another effect is that the influence of C _S2 , . . . , C _So (see Figure 1) can be removed. For example, in Figure 1, if there is a parasitic capacitance C _S1 when T ₁ is off, the combined capacitance with C ₁ is C ₁ · C _S1 /C ₁ + C ₂ , so T ₁ changes from off to on. The capacitance change ΔC ₁ at this time is ΔC ₁ =C ₁ −C ₁ · _CS1 /C ₁ + _CS1 =C ₁₂ /C ₁ + _CS1 =ΔCo/ΔCo+ _CS1 ·ΔCo. Similarly, the capacitance change △C ₂ when T ₂ turns from OFF to ON is △C ₂ = C ₂ /C ₂ +C _S2・2△Co Similarly, in the case of △Cn, △Cn = Cn/Cn + C _So・2 ^n-1 △Co, and the capacitance value cannot be changed in steps of the minimum unit △Co. However, each capacitive element C ₁ , C ₂ , ...,
If the parasitic capacitance has a certain ratio to the capacitance of Cn (C _So = αCn (for example, On/Cn- ₁ = 2 as in the present invention), C ₂ = 2C ₁ and the structure Since C _S2 also becomes C _S2 = 2 _S1 , C _S1 /C ₁ = α
If so, C _S2 /C ₂ =2C _S1 /2C ₁ =C _S1 /C
₁ = α and C _So = αCn is satisfied), then △C ₁ = 1/1 + α・△Co △C ₂ = 2・1/1+α・△Co : : : △Cn=2 ^n-1・1/1+α・△Co, and the minimum unit changes from △Co to 1/1+α・△Co, and the capacitance of this capacitive element group increases by 1 from the minimum capacitance value in steps of 1/1+α・△Co. All capacitance values from /1+α·ΔCo to (1+2+2 ² + . . . +2 ^n-1 ) 1/1+α·ΔCo can be realized, and the undesirable influence of parasitic capacitance can be eliminated.

Regarding such parasitic capacitance, not only the junction capacitance generated between the n-region 10 and the P-type semiconductor substrate 9 but also the capacitance between the gates 13 and 14 and the drains 16 and 18 of the transistors cannot be ignored. gate 13,
This is because the capacitance between the capacitance 14 and the substrate 9 is large and does not affect the overall capacitance, but the capacitance between the gate and drain is relatively small and has a large effect on the overall capacitance. However, as with the capacitive element, this parasitic capacitance between the gate and drain is T ₁ ,
If the lengths of T ₂ , . . . , T _o are changed at a constant ratio, this undesirable effect can be easily eliminated. Specifically, when the length of the drain electrode and the length of the gate electrode of the transistor is the minimum length l, 2 l, 4 l, ...,
2 ^n-1 l.

Thus, the digital windshield of the present invention
The IC pattern is as shown in the plan view of FIG. Although only three capacitive elements C ₁ , C ₂ , and C ₃ are shown here, it is possible that a predetermined number of capacitive elements whose lengths change at the same rate are sequentially formed on the right side of the drawing. should be understood.

In this FIG. 5, the shaded areas 13, 14, 1
3', 14', 13'', and 14'' indicate gate electrodes of a pair of switching transistors formed on both sides of the first, second, and third capacitive elements _C1 , _C2 , and _C3, respectively. These are passages 27, 28,
27', 28', 27'', 28'' to the switching control signal input terminals A ₁ , A ₂ , A ₃ .
Next, 1 of the hatched areas
9, 19', 19'' represent current-carrying aluminum conductors of the capacitive elements C ₁ , C ₂ , C ₃ , and these conductors are coupled to each other through respective passages 29, 29', 29'' and are supplied with a constant DC current. It is combined into a voltage V _c supply path 30 . Other mesh hatched parts 20, 21, 2
1', 21'' are aluminum conductors leading to the source electrodes of each _of the transistors and are commonly coupled to the ground voltage supply path ₃₁ . transistor on the left,
The sources of the right-hand transistor for C ₂ and the left-hand transistor for C ₃ are shared for simplicity, so that the aluminum conductor 21,
21' is also shared by these adjacent transistors. Next, as can be seen from FIG. 2, the drains of the transistors T ₁₁ and T ₁₁ ' and one electrode of the capacitive element C ₁ are formed of mutually continuous n regions 16, 18, and 10, so that the current flow in them is It is served by one passage 32. This passage 32 is, for example, an extension of the n-type drain region of the transistor T ₁₁ provided on the P-type semiconductor substrate 9, and in the middle thereof, another transistor r ₁ ' constituting a resistor is formed by a well-known method. ing. 34 is connected to the drain of the resistor transistor r ₁ ' and a relatively high DC voltage E.
shows an aluminum conductor connecting with the supply path 33 of
Similarly, reference numeral 35 designates an aluminum conductor which connects the gate of resistive transistor r ₁ ' to the supply path 33 via a passage 36. As shown in the figure, a similar configuration is also adopted for capacitive elements C ₃ and C ₂ .

The present invention includes a capacitive element formed on one surface of a semiconductor substrate of one conductivity type, an opposite conductivity type region, an insulator layer provided on the transmission conductivity type region, and a capacitive element separated from the conductivity type region by sandwiching the insulator layer. consisting of an electrode layer formed
When integrated into an IC and the minimum capacitance value of multiple capacitive elements is △Co, respectively △Co, 2△Co, 4△Co, ..., 2 ^n-1 △Co (n
is an integer greater than or equal to 1), a large number of capacitance values can be realized in ΔCo increments, and the resolution is high. Moreover, since the width direction dimension, which cannot be ignored due to the error caused in the production of the capacitor element, is fixed, and the length direction dimension, which can have an negligible error, is changed at a fixed ratio, one electrode forming the capacitor element can be used. The adverse effects caused by parasitic capacitance generated between the semiconductor region and the semiconductor substrate can be removed.

In addition, since the lengths of the gate and drain of the switching transistor are varied at a constant ratio, the adverse effects of parasitic capacitance occurring between the gate and drain of the switching transistor can be ignored, making the present invention extremely useful. It is.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an example in which a digital capacitor is used in a tuning circuit. FIG. 2 is a schematic diagram showing the IC structure of the digital capacitor of the present invention, and FIGS.
FIG. 2 is a schematic diagram showing an IC structure. FIG. 5 is an IC pattern diagram of a digital capacitor embodying the present invention. C ₁ , C ₂ , C _o ... Capacitive element, T ₁ , T ₂ , T _o ...
Switching transistor, T ₁₁ , T ₁₁ '... Switching transistor of C ₁ , 1... Digital capacitor, 9... P-type semiconductor substrate (single substrate), 53
... Single crystal sapphire substrate (single substrate), 10,
45, 56... n region (conductivity type region), 11, 4
7, 49... Insulator layer, 12, 50, 62... One electrode constituting a capacitive element, 13, 48, 60
...Gate electrode.

Claims (1)

[Claims] 1 A plurality of capacitive elements having a fixed capacitance value are connected in parallel, and a switching element is arranged corresponding to each of the capacitive elements, and the switching element is selectively activated by a digital control signal to increase the capacitance. In a digital capacitor in which the overall capacitance value is changed by switching elements, a region of an opposite conductivity type in which the capacitor element is formed on one surface of a semiconductor substrate of one conductivity type, and an insulator provided on the region of the opposite conductivity type. comprising a material layer and an electrode formed apart from the opposite conductivity type region with the insulating material layer sandwiched therebetween,
For each capacitive element, the area of the overlapping portion of the opposite conductivity type region and the electrode is changed in the length direction, and the capacitance value of the capacitive element is set to the minimum capacitance value among them.
When Co, △Co, 2△Co, 4△ respectively
^Co , . A digital capacitor characterized in that the lengths of the drain and the gate are set to 1, 2 1, 4 1, . . . , 2 ^n-1 1, where the minimum length is 1.