JPS6127770B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data shift method used, for example, in small electronic calculators.

In recent years, for example, it has been used as a storage device for small electronic calculators.
There are several types of RAM that use RMM (random access memory), but in conventional RAM, in order to shift the data stored in this RAM, the data to be shifted is called into an accumulator register, and the data stored in the RAM is loaded into an accumulator register. A plurality of microinstructions were used to move the address designation by +1 or -1 and then write the data in the accumulator register to the RAM. However, such a shift method has disadvantages such as an increase in the number of microinstructions, a slow shift processing time, and a complicated circuit configuration for addressing.

The present invention has been made to eliminate the above-mentioned drawbacks, and provides a data shift method that can be performed with fewer microinstructions, reduce shift processing time, and simplify circuit configuration.

Hereinafter, one implementation of the present invention will be described in detail with reference to the drawings.

In FIG. 1, the RAM 11 is made of, for example, a semiconductor integrated circuit, and an address is specified by the intersection of a specified address in the row direction and a specified address in the column direction, and so-called matrix type addressing is performed. The RAM 11 is provided with various registers such as operation registers such as an X register, a Y register, and a Z register in the row direction. The RAM 11 has a row address input terminal RAU, a column address input terminal RAL, and a read/write terminal.
Write command input terminal R/W, data input terminal IN,
A data output terminal OUT is provided.

On the other hand, 12 is a ROM in which various microinstructions are stored, and from this ROM 12, the above-mentioned RAM 11
A signal that specifies the address of a predetermined row of [F _U ], a signal that specifies the processing start column address [S _L ], a signal that specifies the processing end column address [F _L ], instructions for carry, carry, etc. A signal [INS] and a signal [NA] specifying its own next address are output in parallel via bus lines a to e, respectively. The signal [NA] output via the bus line e is temporarily stored in the address register 13, and the output of the address register 13 is input to the address decoder 14. This address decoder 14 decodes the input signal into each address and supplies it to the ROM 12, thereby specifying the address of the ROM 12. Also, the signal [INS] is the bus line d
The signal is applied to the instruction decoder 15 via the instruction decoder 15. This instruction decoder 15
together with the above signal [INS], the clocks φ ₁ , φ
The output of the timing counter 16, which generates a timing signal of _{the second} class, is inputted via the timing decoder 17, which decodes and outputs the three-phase timing signal [ _t1 , _t2 , _t3 ] that synchronizes various circuits. , outputs various control signals to be described later.

Further, a signal [F _U ] specifying the row address of the register of the RAM 11 is applied to the gate circuit G ₁ via the bus line a, and the gate circuit G ₁
The output is input to the row address input terminal [RAU] of the RAM 11 via the bus line. In addition,
The above gate circuit G ₁ includes a timing decoder 1
A timing signal [t ₁ ] output from 7 is supplied via an inverter 18 to control opening and closing.

In addition, a signal [S
_L ] is output to the input/output common bus line g via the gate circuit G ₂ whose opening/closing is controlled by the signal [O ₁ ] output from the instruction decoder 15, and is sent to the column address input terminal [RAL] of the RAM 11. Address counter 1
9 as a preset signal. This address counter 19 performs a reading operation using the clock _φ1 , and the instruction decoder 15
The operation is controlled by the up-down control signal [A] output from the up-down control signal [A]. This up-down control signal [A] is applied at timing _t2 when a right shift is specified by the instruction signal [INS], and at timings _t1 and _t3 when a left shift is specified.
The instruction decoder 15 is configured to output "1" at each of the instruction decoders 15 and 15. The output of the address counter 19 is outputted to the input/output common bus line g via the gate circuit _G3 whose opening/closing is controlled by the output _O2 of the instruction decoder 15, and inputted again to itself to perform the counting operation. Let's do it. The signals O ₁ and O ₂ that control the opening and closing of the gate circuits G ₂ and G ₃ are based on the logic condition of O ₁ = S ₀・t ₁ O ₂ = ₀・₁ using the head cycle timing S ₀ described later. The instruction decoder 15 is configured to output the instruction.

Thus, the output of the RAM 11 whose row and column addresses are designated by the terminals [RAU] and [RAL] is output as parallel 4-bit data from the terminal [OUT], and the timing signals _t1 and t are sent via the bus line h. ₂ is input to buffer registers 20 and 21 whose reading is controlled by 2. In this embodiment, which performs a shift operation, the signal [F _U ] specifying the row address of the register storing the data to be processed is set to be output by the gate circuit G ₁ at timings t ₂ and t ₃ . Therefore, the data output to the bus line h is read into the buffer register 21 which is read and controlled at timing _t2 . The respective outputs of these buffer registers 20 and 21 are input to the addition/subtraction circuit 22 via adder input gate circuits G ₄ and G ₅ whose opening and closing are controlled by the output signals SB and FA of the instruction decoder 15. The output is input to the data input terminal [IN] of the RAM 11 at timing _t3 . Furthermore, for data input/output of the RAM 11, that is, data writing and reading, the output AF of the instruction decoder 15 and the timing signal _t3 are sent to the RAM ₁₁ via the R/R/
It is controlled by being applied to the W terminal.

In addition, a signal [F
_L ] is input to one input terminal of the matching circuit 23 via the bus line c, and the output of the address counter 19 is input to the other input terminal of the matching circuit 23 via the input/output common bus line g. It has been entered. Therefore, the coincidence output of this coincidence circuit 23 is
It is applied to one input terminal of the AND circuit 24. A timing signal t ₃ output from the timing decoder 17 is applied to the other input terminal of the AND circuit 24, and the output of the AND circuit 24 is input to one input terminal of the AND circuit 25. ₃ , and is input to a flip-flop 26 which performs a read operation at the timing of _φ1 .
On the other hand, the clock _φ1 output from the timing counter 16 is input to the other input terminal of the AND circuit 25, and the output of the AND circuit 25 is as follows.
It is applied to the address register 13 as a read clock for the address register 13. On the other hand,
The output of the flip-flop 26 is applied to the instruction decoder 15 as head cycle timing _S0 .

By the way, the address counter 19 and the gate circuit _G3 are constituted by a parallel 4-bit up-down counter, for example, as shown in FIG.
That is, in FIG. 2, the outputs of each stage ( ²⁰ to ²³ ) of the 4-bit binary counter 30 are inputted to one input terminal of the NAND circuits 31 to 34, respectively. A control signal _O2 is introduced from an instruction decoder (FIG. 115) to the other input terminals of the NAND circuits 31-34. This control signal _O2 becomes "0" when a preset command is given to the address counter 19, and becomes "1" when a count operation command is given. The respective outputs of the NAND circuits 31-33 are respectively led as one input of mismatch circuits 35-37. Further, input/output lines 38-41 are connected to each output of the NAND circuits 31-34. These input/output lines 38 to 41 are given a preset code input at the time of presetting, and the output of the binary counter 30 is sent to the NAND circuit 3 at the time of counting operation.
1 to 34. An up-down control signal A is applied from an instruction decoder (FIG. 15) as the other input of each of the mismatch circuits 35-37. This signal is "0" when an up operation command is issued, and "1" when a down operation command is issued. Further, the output of the mismatch circuit 35 is led as one input of the match circuit 42 and as one input of the NAND circuit 43. The output of the mismatch circuit 36 is introduced as the other input of the NAND circuit 43, and the output of the NAND circuit 43 is introduced as one input of the mismatch circuit 44.
Further, each output of the mismatch circuits 35, 36, and 37 is led to a NAND circuit 45, and the output of this NAND circuit 45 is led as one input of the mismatch circuit 46. The other input of this mismatch circuit 46 is the output of the NAND circuit 34, and the other input of the mismatch circuit 44 is the NAND circuit 3.
3, and the output of the NAND circuit 32 is introduced as the other input of the matching circuit 42. And a NAND circuit 31, a coincidence circuit 42, a mismatch circuit 44,
Each output of 46 corresponds to the counter 3.
This counter 30 is supplied with a clock _φ1 as a read clock at each timing from _t1 to _t3 .

Next, in the data shift method described above, the third
As shown in the figure, the right shift operation when S _L =0 and F _L =3 will be explained by taking as an example the case where data is stored as shown in FIG. 4a. First, at clock _t1 of the head cycle _S0 (cycle time 1), the gate circuit _G2 is opened by the control output _O1 of the decoder 15, and this gate circuit _G2 is connected to the signal [ _SL ] (0, 0, 0) of the ROM 12. , 0) is passed and the address counter 19 is preset to (0, 0, 0, 0). At this time, the signal A output from the instruction decoder is "O" and gives a count up command, so the count is increased by +1 and the contents of the binary counter 30 are (0, 1 , 1, 1). Then, when the timing changes from t ₁ to t ₂ , the gate circuit is activated by the control outputs O ₁ and O ₂ of the instruction decoder 15.
G ₂ closes and gate circuit G ₃ opens. Therefore, the count output of address counter 19 is
The column address of RAM11 will be specified.
Also, at this time, gate circuit _G1 also opens.
A signal [F _U ] of the ROM 12 specifies a row address of the RAM 11. Also, at this time, the write commands AF and _t3 are not supplied to the gate circuit _G6 , and the RAM
A read command is given to the R/W terminal 11. Therefore, the specified address of RAM11 is “1”
In the data register of the row designated by the signal [F _U ], data 3 of the shift start digit designated by the output of the address counter 19 is read out and held in the buffer register 21 . Note that the output of the address counter 19 is input to the coincidence circuit 23 and a coincidence judgment is made between it and the signal [F _L ] 3, but there is still no coincidence and no coincidence output is generated. Therefore, the gate of the AND circuit 24 is closed,
Due to the AND output of the AND circuit 24, the gate of the AND circuit 25 is also closed. Then, at the above timing _t2 , the signal A is "1" and gives a countdown command, so the address counter 19 counts down by -1 and the binary counter 30 becomes (1, 1, 1, 1), and the NAND circuit The count output obtained through 31 to 34 becomes "0". Next, when the timing changes from _t2 to _t3 , a control output FA is generated from the instruction decoder 15, the gate circuit _G5 is opened, and the data 13 of the buffer register 21 is transferred to the gate circuit _G5 .
and is input to the RAM 11 through the addition/subtraction circuit 22. At this time, the AF signal is also output from the instruction decoder, and the timing is
Since t ₃ , gate circuit G ₆ sends the write command.
It is given to the R/W terminal of RAM11. Therefore, the above data 3 (timing
The data one digit higher than that read out and held at _t2 is written, resulting in a right shift as shown in FIG. 4b. and timing
At time _t3 , the signal A is "0", so the address counter 19 counts +1 and the pre-binary counter 30 becomes (0, 1, 1, 1).

Below, at cycle times 2 to 4, as in head cycle S ₀ , +1 at timing t ₁ .
Counts up, reads the data one digit above the address specified by the count output at timing _t2 and holds it, then counts down by -1, and at timing _t3 writes the held data to the address specified by the count output +1 Repeat the counting up action.

Therefore, in the data register of the RAM 11, as cycle times 1 to 4 progress, the data in the first to fourth digits are shifted one by one from the upper digit to the lower digit, as shown in c to e. However, the fourth digit is the blanking code α. Then, when the count output of the address counter 19 matches the signal [F _L ] of the ROM 12 at timing _t3 , a match output is generated from the match circuit 23. Therefore, an AND output "1" between the coincidence output and the timing _t3 is generated from the AND circuit 24, and this AND output "1" is read into the flip-flop 26 and applied to the AND circuit 25, which is in turn connected to the clock. When _φ1 is output, "1" is output and applied to the address register 13, causing the address register 13 to read its own next address. Then, the data in the address register 13 is decoded by the address decoder 14, and the address designation of the ROM 12 is changed based on the decoded output to move to the next microstep. Further, the output of the flip-flop 26 is applied to the instruction decoder 15 as a signal specifying a head cycle.

Next, as shown in FIG. 5, a left shift operation with S _L =3 and F _L =0 will be described using as an example the case where data is stored as shown in FIG. 6a. As shown in Fig. 5, the left shift operation is performed by counting down by -1 at timing _t1 at each cycle time, and at timing _t2 reading and holding the data one digit lower than the address specified by the count output. It counts up by +1, writes the held data to the address specified by the count output at timing _t3 , and then counts down by -1, and the operation of each circuit is the same as in the right shift described above.

Therefore, in the data register of RAM11,
For example, if 123 is initially stored as shown in a in FIG.
It is shifted to the left one digit at a time as shown in . Then, the output of address counter 19 is timing
When "0" is output at time _t3 , the coincidence output of the coincidence circuit 23 is applied to the AND circuit 25 and flip-flop 26 via the AND circuit 24, and causes the address register 13 to read its own next address in the same way as the right shift described above. In addition, the head cycle designation signal
S ₀ is applied to the instruction decoder 15.

Note that the data α and β are planking codes like zero suppression codes;
In order to prohibit the shift of β and write data “0” instead, for example, a gate circuit (not shown) is provided on the output line of the addition/subtraction circuit 22.
Normally, this gate may be opened and the gate circuit may be closed when AND output "1" is obtained from the AND circuit 24.

Next, the operations of the address counter 19 and gate circuit _G3 will be explained. In FIG. 2, it is assumed that the _O2 input is "0" at the time of preset, the preset input is (0,0,0,0), and the A input is "0" at this time. Therefore, Nando circuit 3
1 to 34 are "0" because their outputs are directly connected to the preset inputs, and the mismatch circuits 35,
36 and 37 have their respective inputs “0”, “0”,
Since it is "0" and they match, the output is "0". Since the inputs of the matching circuit 42 are "0" and "0", the output is "1". In addition, each input of the NAND circuit 43 is “0”,
Since it is "0", the output is "1", and each input of the mismatch circuit 44 is "0" and "1", so there is no mismatch, and the output is "1". In addition, since each input of the NAND circuit 45 is "0" and "0", the output is "1", and each input of the mismatch circuit 46 is "0" and "1", and the output is "1" due to mismatch. It is. Therefore, the reading pulse φ ₁ causes the caranta 30 to read the input (0, 1, 1, 1), and then O ₂
When the input becomes "1", the outputs of the NAND circuits 31 to 34 become 1, 0, 0, 0, respectively, and are taken out as count output 1. If the A input is "1" at this time, the mismatch circuits 36, 3
7, the two inputs are "0" and "1", which are inconsistent, so the respective outputs are "1". However, since the two inputs of the mismatch circuit 35 match as 1, 1, the output remains "0". Therefore, the outputs of the NAND circuits 43 and 45 remain at "1", and the outputs of the match circuit 42 and mismatch circuits 44 and 46 remain at "1".

Therefore, with the next read pulse φ ₁ , the counter 30 reads (1, 1, 1, 1), and the outputs of the NAND circuits 31 to 34 correspond to (0, 0, 0, 0) and count. It is taken out as output 0.

That is, according to the circuit shown in FIG. 2 described above, the output of the counter 30 is taken out via the NAND circuits 31 to 34, and when A is "0", +1 is added to the output of the NAND circuits 31 to 34. A is “1”
In this case, -1 is subtracted and the counter 30 is read by a read pulse _φ1 . Furthermore, when presetting, if the NAND circuits 31 to 34 are closed and the preset inputs are directly connected to the outputs of the NAND circuits 31 to 34, in other words, if the preset input is applied instead of taking out the count output, the "0" signal will have priority. As a result, the preset code is given priority and can be read by the binary counter 30 through appropriate processing.

Although the above embodiment uses a three-phase clock per microcycle, the key point is that the address is shifted by 2 after writing in one microcycle, and the address is shifted back by 1 after reading in the next microcycle. Needless to say, such control can also be performed using a two-phase clock.

Further, in the above embodiment, the data held in the buffer register 21 is led to the data input terminal [IN] of the RAM 11 through the addition/subtraction circuit 22, but it may be directly led without passing through the addition/subtraction circuit 22.

As explained in detail above, according to the data shift method of the present invention, a shift processing start address and a shift processing end address are specified with one microinstruction, and the address of data to be shifted and written every cycle. The shift process is performed from the shift process start address to the end address by specifying the address to read and hold the data, and then specifying the address to write the data to write the data. There is. Therefore, compared to the conventional method of calling the data to be shifted to the accumulator using multiple microinstructions, shifting the RAM address specification, and then writing the data, the shift processing time can be shortened and the number of microinstructions can be reduced. It also has various advantages such as a simplified circuit configuration for addressing.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the data shift method according to the present invention, and FIG.
A configuration explanatory diagram showing the address counter and gate _G3 shown in FIG. 3, FIGS. 3 and 4 are diagrams shown to explain the right shift operation of FIG. FIG. 3 is a diagram shown to explain a left shift operation of the controller. 11...RAM, 12...ROM, 19...address counter, 20, 21...buffer register, 23...
matching circuit.

Claims (1)

[Claims] 1. Storage means in which various data necessary for calculations are stored and addressed by row and column, and microinstruction generation means that outputs the row address of the storage means, data processing start column, and end column address in one microinstruction. , an initial value is set for the storage means every microcycle by a timing control means for controlling reading and writing of data at different timings, and the data processing start column address outputted from the microinstruction generation means. Further, it has an up/down count means controlled by an up/down control signal outputted from the microinstruction generation means, and changes the contents of the up/down count means in synchronization with the read and write timings. Addressing means for specifying data read and write addresses of the storage means every microcycle, and means for reintroducing the data addressed and read by the addressing means into the storage means at the write timing. and detection means for detecting that the output of the address designation means matches the data processing end column address output from the microinstruction generation means;
and means for changing the address of the micro-instruction generating means based on the output of the detecting means, and the data shifting method is characterized in that data is shifted by one micro-instruction.