JPS6127785B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data transfer method that includes a plurality of microprocessors (CPUs) and mutually transfers data using a shared memory in order to improve the processing capacity of a computer control device. The purpose is to provide a data transfer method that simplifies the circuit by sampling memory control using a clock signal, improves circuit reliability, and reduces the number of parts. .

Generally, in a device using two CPUs, shared memory occupancy is controlled by access signals output from each CPU, but as shown in Figure 1, the access signals are in the non-access state 1, the access state 1, and the access signal output from each CPU. There are four states: start state 2, access state 3, and access completion state 4. Since there are four access states for one CPU, if there are two CPUs, the number of states becomes 16 depending on the combination, which complicates the control method and control circuit, leading to various problems in terms of reliability and assembly work.

In order to solve the above-mentioned drawbacks, the present invention fixes each state by sampling using a clock signal and simplifies its control. The fixed state includes three states described below, and embodiments of the present invention will be described below with reference to the drawings.

Figure 2 is a circuit diagram showing the data transfer circuit of a device with two CPUs, 5 and 6 are CPUs, and 7 is a circuit diagram showing the data transfer circuit of a device with two CPUs.
Memory control for writing and reading data to and from memory 8 shared by CPUs 5 and 6; 9;
10, 11, 12 are gate circuits for the data bus and address bus of CPUs 5 and 6, 13 is the CPU
5, 6 and the memory control 7. The memory control 7 outputs a signal (OPENA) to open the gate circuits 9, 11 and a signal (OPENB) to open the gate circuits 10, 12 based on the access signals (MREQA, MREQB) of the CPUs 5, 6. . When OPENA is output, memory 8 is the CPU
5 is occupied, and when OPENB is output, memory 8
will be occupied by CPU6. In addition, the signals (WAITA, WAITB) output from memory control 7 will
This is a signal for making 6 standby. Its operation is
When MREQA is output from CPU5 to memory control 7, OPENA is output from memory control 7.
is output, gate circuits 9 and 11 are opened, and CPU5
Write data to the memory 8 or transfer the read address by the write signal (WRA) or read signal (RDA) from the CPU.
5 occupies memory 8. Also, from CPU6
When MREQB is output, memory control 7
OPENB is output from , and the CPU 6 occupies the memory 8 in the same way as above. Furthermore, when the access signals (MREQA, MREQB) are output from the CPUs 5 and 6 at the same time, the memory control 7
Set and prioritize one of 6.
Make the CPU occupy memory 8. For example, if CPU 5 is given priority, OPENB and WAITA are output from memory control 7,
Make CPU 6 occupy memory 8.

FIG. 3 is a circuit diagram showing the details of the memory control 7 shown in FIG.
9, 20 are not gates, and gates 2
A clock signal Φ is input from the clock generator 13 to one input terminal of the flip-flop 14.
And from CPU5 to AND gates 15 and 16
MREQB is input from the CPU 6 to one input terminal of MREQA and AND gates 17 and 18, and OPENA and MREQB are input from the outputs of AND gates 15 to 18, respectively.
WAITA, OPENB, WAITB are output. CPU
Access signals from 5 and 6 (MREQA,
MREQB) is not output (MREQA=
0, MREQB=0), the output of the flip-flop 14 is "0". Therefore, the outputs of the AND gates 15 to 18 become "0", and the gate circuit 9
~12 are closed and the memory 8 is separated from the CPUs 5 and 6. This state is state A in FIG. Next, when MREQA is output from CPU5 (MREQA=1), flip-flop 14
The output signal Q of the AND gate 21 becomes "1" from the rising edge of the output (signal Φ), the output of the AND gate 15 becomes "1", and the memory 8 is connected to the CPU.
5 (state B in FIG. 4).
At this time, when MREQB is output from the CPU 6 (MREQB=1), the output signal (WAITB) of the AND gate 18 becomes "1", causing the CPU 6 to enter a standby state. Flip-flop 14 samples MREQA by signal Φ and sets MREQA to “0”.
Outputs the sampled signal until .
When MREQA becomes "0", the state returns to state A in FIG. Next, when MREQB becomes "1", the output signal (OPENB) of the AND gate 17 becomes "1", and the memory 8 is occupied by the CPU 6. This state is state C in FIG. Also, at this time, MREQA
Even if becomes "1", since OPENB is "1", the output of the not gate 20 is "0", and the output signal Φ of the AND gate 21 is not output, and sampling by the signal of MREQA is stopped. Also,
When MREQA becomes "1", the output signal (WAITA) of the AND gate 16 becomes "1" because the output of the NOT gate 19 is "1", causing the CPU 5 to enter the standby state until MREQB becomes "0". Continue to wait. When MREQB becomes "0", the input of the AND gate 21 through the NOT gate 20 becomes "1" and starts outputting the signal Φ, resulting in state B in FIG. 4, where the memory 8 is occupied by the CPU 5. Ru. When MREQA and MREQB become "1" at the same time, the output of the flip-flop 14 is "0", so the operation to stop the signal Φ is quick and the state C described above is reached.

As described above, the present invention configures the memory control with one flip-flop, five AND gates, and two NOT gates, one of which is
The memory access signal from the CPU is transferred to the other side.
By sampling with a flip-flop in synchronization with the rise or fall of an AND signal between a signal based on an access signal from the CPU and a clock signal, and stopping the sampling with a signal based on an access signal from the other CPU. Therefore, one memory is controlled so that it can be shared by two CPUs, and the control circuit is simplified by changing from the conventional 16-state control to 3-state control, A, B, and C. In addition, the number of parts can be reduced, the management of circuit parts becomes easier, and the reliability of the circuit is improved.
Furthermore, even when a thin pulse is input from the outside to a signal line such as an access signal, malfunction does not occur, and a circuit that is resistant to external noise can be realized.

[Brief explanation of the drawing]

Figure 1 is a time chart of CPU access signals, Figure 2 is a circuit diagram showing the data transfer method according to the present invention, Figure 3 is a circuit diagram showing details of the memory control in Figure 1, and Figure 4 is a memory control diagram. This is a time chart showing the signal status. 5, 6...CPU, 7...Memory control, 8
...memory, 9,10,11,12...gate circuit,
13... Clock generator, 14... Flip-flop, 15, 16, 17, 18, 21... AND gate, 19, 20... NOT gate.

Claims (1)

[Claims] 1 When a memory is provided that is shared by multiple microprocessors and data is transferred to and from the memory, the access signal from one microprocessor to the memory is based on the access signal from the other microprocessor. The shared memory is controlled by sampling by a flip-flop in synchronization with the rise or fall of an AND signal between the signal and the clock signal, and stopping the sampling with a signal based on the access signal from the other microprocessor. Characteristic data transfer method.