JPS6128276B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a jitter amount display method for quantitatively displaying jitter detected by a jitter detection section.

As is already known, jitter is the wavering, bending, or disturbance of the playback screen in the time axis direction, which is caused by uneven running of the tape or uneven rotation of the rotating unit during image playback on a VTR.

This is nothing but a variation in the time interval of the horizontal synchronizing signal, which should originally be at equal intervals (1H is 63.5 μs).

Therefore, to measure this jitter, the horizontal synchronizing pulse is extracted from the video signal and its time interval fluctuation is detected and measured. It is only displayed, but there is almost no quantitative display such as how many microseconds the jitter is.

Therefore, even if jitter is detected, it is not possible to quantitatively determine the extent of the detected jitter.

In view of the current situation, the present invention is designed to quantitatively display detected jitter using analog or digital means.

Note that television images are scanned using interlaced scanning, and one field is repeated at 60 HZ/sec in the NTSC system.

Furthermore, in order to detect jitter, the horizontal synchronizing pulse is extracted from the television composite signal and fluctuations in the pulse interval are detected as jitter, so vertical synchronizing pulses and equivalent pulses are not subject to jitter detection.

Therefore, the number of repetitions of the vertical synchronizing pulse and the equivalent pulse within a certain jitter measurement time (χsec) is χsec×1/1/60=60× times. (Here, 1/60 is the time required to scan one field, and 1/1/60 is the number of times it is scanned per second.) Therefore, the detection signal within a certain jitter measurement time (χsec) is As shown in FIG. 1, the jitter detection section A and the non-detection section (vertical synchronization pulse and equivalent pulse time) B are alternately repeated and discontinuous.

Furthermore, a portion C of the jitter detector A that is close to the vertical synchronization pulse is susceptible to skew distortion.

Therefore, the present invention extracts only the pure jitter (portion D in Figure 1) that is not affected by skew and distortion from the jitter detected by the jitter detector and displays it quantitatively. be.

The present invention detects a vertical synchronization pulse from a television composite signal, uses this pulse to create a selection signal,
This selection signal is applied to the output of the jitter detector for the time set by the measurement time setting circuit, only the jitter component that is not affected by skew distortion is extracted, this jitter component is rectified, and the selection signal is applied. It is designed to hold any one of the peak value, average value, effective value, sigma value, etc. within the measurement time, and quantitatively display the held jitter amount on an indicator in analog or digital form.

The area within the dashed line 1 in FIGS. 2 to 5 is a jitter amount display section illustrating the method of the present invention, and the other portion is a jitter detection section for detecting jitter as shown in FIG. 1 from a television composite signal.

Of Figures 2 to 4, Figure 2 shows the peak value of jitter, Figure 3 shows the sigma value of jitter, and Figure 4 shows the average value of jitter. , FIG. 5 shows a digital display of the peak value. 2 to 5, 2 is a vertical synchronization pulse detection circuit, which is composed of an integrating circuit 3 and a monostable multivibrator 4 as shown in FIG. The synchronizing pulse is integrated as shown in the figure (b), and the monostable multivibrator 4 is turned on at the trigger point E in the figure (b), as shown in the figure (c).

Reference numeral 5 denotes a gate circuit, which consists of two stages of monostable multivibrators 6 and 7 connected as shown in Fig. 8. A pulse that turns on at the rising edge of the pulse is generated, and the subsequent monostable multivibrator 7 generates a pulse that turns on at the rising edge of the pulse as shown in FIG.

8 is a time setting circuit for setting the time at which the jitter component shown in FIG. 1D is to be measured, and 9 is a gate circuit.
The former turns on and off as shown in Figure 10 A,
The latter is a monostable multivibrator that generates pulses that turn on and off as shown in the figure (b). 10
1 is a gate circuit using an AND circuit, 11 is a full-wave rectifier circuit, 12 is a hold circuit, and 13 is an indicator such as a voltmeter.

In addition, in Figures 2, 3, and 5, 14
1 is a comparison circuit, and 15 is a buffer circuit.

16 in FIG. 3 is a sigma value detection section inserted between the full-wave rectifier circuit 11 and the buffer circuit 15, which includes transistors TR, IC, IC ₂ , resistors R ₁ , R ₂ , and capacitor C ₁
Consisting of

17 in FIG. 4 is an average value detection section inserted between the buffer circuit 15 and the hold circuit 12, and the resistance R ₃ ,
It consists of R ₄ and capacitor C ₂ .

The jitter amount display section 1 shown in FIG. 2 operates as follows to quantitatively display the peak value on the indicator 13. (In the following explanation, circled numbers refer to Figure 2~
A waveform diagram at the circled number points in FIG. 5 is shown. ) First, the video signal is removed from the television composite signal input to the input terminal 18 by the synchronization separation circuit 19, resulting in the signal shown in FIG.

This enters the vertical synchronizing pulse detection path 2, where the vertical synchronizing pulse (signal shown in FIG. 11) is detected.

This signal enters the gate circuit 5, and the output of the gate circuit 5 becomes the pulse signal shown in FIG. This pulse is used as a selection signal for extracting only the pure jitter component (portion D in Figure 1) that is not affected by skew distortion out of the jitter as shown in Figure 1 detected by the jitter detection section. Enter circuit 10.

A signal from the time setting circuit 8 (the pulse shown in FIG. 11) is also applied to this gate circuit 10, and this signal selection signal is ANDed to produce the pulse shown in FIG.

Switch _S1 is turned on only when this selection signal is on, and only the pure jitter component (Fig. 11'), which is not affected by skew distortion, is extracted from the jitter in Fig. 11 detected by the jitter detection section. , this pure jitter component is used in the next stage full-wave rectifier circuit 1.
Enter 1.

The pure jitter component that has entered the full-wave rectifier circuit 11 is rectified as shown in FIG. 11 (an enlarged view of which is shown in FIG. It is compared with the input voltage at input end b (voltage at capacitor _C3 ).

In this case, if the voltage at input terminal a is higher than the voltage at input terminal b, switch _S2 is turned on and both input terminals a and b
The capacitor _C3 is charged until the voltages are the same. Note that, prior to turning on the switch _S1 , it is turned on by the signal from the gate circuit 9 (Fig. 11), and a jitter voltage is applied to the input terminal a in order to clear the charge that had been accumulated in the capacitor _C3 . Initially, the voltage is always higher than the voltage at input terminal b.

When the amount of jitter decreases and the rectified voltage decreases, and the voltage at input terminal a becomes lower than the voltage at input terminal b, switch _S2 is turned off and charging to capacitor _C3 is _stopped . The electric charge charged in the cell is held as shown in FIG.

Next, when the jitter increases and the voltage at input terminal a becomes higher than the voltage at input terminal b, switch _S2 is turned on again and charging of capacitor _C3 is resumed. By repeating this process, the peak voltage during the measurement time when the switch _S1 is on is accumulated in the capacitor _C3 , and the peak value is held in the hold circuit 12. This enters the indicator 13 and is displayed in analog form.

Next, the sigma value detecting section 16 shown in FIG. 3, which indicates the sigma value to the indicator 13, operates as follows.

First, IC ₁ compares input voltage c and output voltage d, and when c>d, transistor TR turns on, and I ₂
A current of +I ₃ =I ₄ flows. Furthermore, when c<d, the transistor TR is turned off, and the resistor R ₁ is connected from the power supply.
A current I ₁ flows through C ₁ and IC ₂ through the current I 1 .

At this time, if the resistors R ₁ and R ₂ are selected such that R ₁ > R ₂ ,
The time relationship between the current entering and exiting the capacitor C ₁ is C ₁ R ₁ > C ₁ R ₂ , and the charging time constant C ₁ · R ₂ seen from d is smaller than the discharging time constant C ₁ · R _1. ,
The output F of IC ₂ with respect to the input voltage c approximately indicates the standard deviation value of the probability statistical theory as shown by the dotted line in FIG.

In FIG. 3, switch _S4 is used to eliminate jitter measurement errors. That is, if this switch _S4 is removed, even when no jitter is being transmitted, the voltage at the input terminal c in the figure becomes lower than the voltage at the input terminal d, and current _I1 flows to capacitor _C1 , resulting in the same state as the measurement state. However, if switch S ₄ is installed, and switch S ₁ is installed, it will cause a measurement error.
Measurement errors are eliminated by turning on and off in synchronization with the

The signal sigma-processed as described above (dotted line in Figure 13) enters the comparator circuit 14, is processed in the same manner as in Figure 2, is held in the hold circuit 12 as shown in Figure 11, and is displayed as an indicator. 13, and the sigma value is displayed in analog on the indicator 13.

Note that the switches S ₃ and S ₅ in FIG. 3 are turned on and off by the signal from the gate circuit 9 (FIG. 11) prior to the measurement, and the capacitors C ₃ and
This discharges the charge accumulated in _C1 .

Next, the average value detection section 17 in FIG. 4 operates as follows.

First, the average value Ia for the sine wave is the maximum value Im
Since Ia=2Im/π, R ₃・
The relationship between the charging time constant of C ₂ and the discharging time constant of R ₄ ·C ₂ must be selected to indicate 63.7% for a sinusoidal rectified input. Therefore, in order to measure an intermittent signal over a certain period of time and obtain its average value, the capacitor _C2 must be charged and discharged while the switch _S6 is turned on and off to add jitter.

Therefore, in the average value detection section 17 of FIG. 4, the switches S ₆ , S ₇ , and S ₈ are turned on and off by the signal from the gate circuit 9 (FIG. 11), and the capacitor
The charges accumulated in C ₂ and C ₃ are discharged, and then the switch S ₁ is turned on by the signal from the gate circuit 10 (Fig. 11), and at the same time the switch is turned on.
Turn on S ₆ and S ₈ to enter the measurement state.

At this time, capacitor _C3 is also charged with the same amount of charge as that stored in capacitor _C2 .

When the measurement time elapses and switches S ₁ , S ₆ , and S ₈ turn off, the charges in capacitors C ₂ and C ₃ are held at the charge immediately before they were turned off, as shown by the dotted lines in Figure 14, and then This continues until the measurement starts when the switches S ₁ , S ₆ , and S ₈ are turned on, and the measurement is restarted when these switches are turned on again. By this repetition, the holding of the average value by the hold circuit 12 is also repeated.

In addition, the charge of capacitor C ₃ is the same as that of switch S ₁ ,
Even when S ₆ and S ₈ are turned off and no signal is received from the jitter detection section, the hold circuit 12 holds the average value, so the average value continues as shown in Figure 11 and is displayed in analog on the indicator 13. .

The ones in Figures 2 to 4 explained above are for analog display of the jitter peak value, sigma value, average value, etc., respectively, but in order to digitally display these values, one point in Figure 5 is used. As shown within the chain line,
A voltage-code conversion circuit 20, a code hold circuit 21, a read pulse generation circuit 22, and a code transfer pulse generation circuit 23 may be provided.

The voltage-code conversion circuit 20 converts the input voltage from the peak hold circuit 12 into a predetermined bit code.

The read pulse generation circuit 22 generates timing pulses that code the voltage entering the voltage-code conversion circuit 20 from the peak hold circuit 12.

The code hold circuit 21 holds and stores the code when the voltage input to the voltage-code conversion circuit 20 is converted into a code proportional to the voltage. That is, when a read pulse is input from the voltage-code conversion circuit 22, encoding starts, but in this case, it starts from 0 and becomes a code proportional to the voltage input from the peak hold circuit 12 to the voltage-code conversion circuit 20. If the output of the voltage-code conversion circuit 20 is input to the linear indicator 13', the numbers in the display window of the indicator 13' will change accordingly, making the numbers difficult to read. Become. Therefore, the hold circuit 21 does not store the coding process, but stores only the code proportional to the input voltage, and inputs it to the indicator 13'.

Note that, when the code of the voltage-code conversion circuit 20 changes, the code hold circuit 21 holds only the change from the previously stored code (for example, if only the last digit of the 4-bit code changes). (by the same amount) and memorize the new code.

The code transfer pulse generation circuit 23 generates a timing pulse (FIG. 15) for transferring the voltage coded by the voltage-code conversion circuit 20 to the code hold circuit 21.

Now, the analog signal from the hold circuit 12 (FIG. 11) enters the voltage-code conversion circuit 20, and the pulse from the measurement time setting circuit 8 (FIG. 15) causes the read pulse generation circuit 22 to output When a read pulse is generated and enters the voltage-code conversion circuit 20, the voltage input from the hold circuit 12 is changed in the same circuit 20.
It is converted to an appropriate code such as BCD code.

When the transfer pulse (FIG. 15) from the code transfer pulse generation circuit 23 enters the code hold circuit 21, the converted code signal is transferred to the same circuit 21 and held.
The signal enters an indicator 13' including a decoder and is digitally displayed on a 7-segment LED or the like.

The above digital display shows sigma value, average value,
Even when displaying effective values, etc., the configuration and operation are exactly the same.

Next, the jitter detector may be any type as long as it detects jitter from the TV composite signal and detects jitter as shown in Figure 1, but as an example, it is shown in Figures 2 to 4. The structure and operation of the device are as follows. First, the configuration consists of a sync separation circuit 19 that removes the video signal from the composite signal, a vertical/equivalent pulse removal circuit 24 that removes the vertical sync pulse and the equivalent pulse, and a first removal circuit that removes the first pulse of the horizontal pulses. a circuit 25, a second removal circuit 26 for removing the second pulse of the horizontal pulses, an integrating circuit 30 consisting of gate circuits 27, 28, 29, resistors R _A capacitor C _A , and an amplifier 31 for amplifying the integrated voltage. , a capacitor C _B that charges the amplified voltage, a peak hold circuit 32 that holds the peak, and a visual correction filter 3
3. It also consists of switches S _A , S _B , and S _C .

Next, its operation is as follows.

The TV composite signal (FIG. 16) that enters the input terminal 18 from the output terminal of the VTR is sent to the sync separation circuit 19,
By passing through the vertical/equivalent pulse removal circuit 24, the video signal, vertical synchronizing pulse, and equivalent pulse are sequentially removed, and the horizontal synchronizing pulse is extracted as shown in FIG.

This pulse passes through the first removal circuit 25 and becomes the first horizontal synchronizing pulse as shown in FIG.
H ₁ is removed and enters gate circuits 28 and 29.

This gate circuit 28 turns the discharge switch S _A on and off as shown in Fig. 16, so when the second and subsequent horizontal synchronizing pulses are input to the gate circuit 28, the switch _S It is turned off and stored in capacitor C _A. Charge is discharged.

At this time, the second and subsequent horizontal synchronizing pulses enter the gate circuit 29 that turns on and off the charging switch S _B , and the switch S _B turns on and off as shown in Figure 16 and is discharged first. Capacitor C _A is charged as shown in Figure 16.

In this case, the time during which the charging switch S _B remains on (charging time) is equal to the pulse width shown in Figure 16. Therefore, when the horizontal synchronization pulse width is large, the charging time becomes long and the peak value of the integral waveform becomes large, and when the pulse width is small, the charging time becomes short and the peak value of the integrated waveform becomes small.

Moreover, if the pulse interval of the horizontal synchronizing pulse is larger or smaller than 63.5 μs, which should be an equal interval, the magnitude will cause jitter, so the magnitude of the peak of the integral waveform will be proportional to the magnitude of jitter, and therefore jitter is detected as an integral waveform voltage.

Moreover, when the integral waveform reaches its peak, the third and subsequent horizontal synchronizing pulses that enter the gate circuit 27 cause the circuit 27 to switch the hold switch _SC to the first position.
In order to turn on and off as shown in FIG. 6, the peak value (jitter) of the integral waveform is held by the peak hold circuit 32 as shown in FIG.

In this case, the hold switch S _C is turned off before the discharge switch S _A is turned on, so when the discharge switch S _A is turned on, the peak hold circuit 3
2, the hold should stop, but when the hold switch S _C is turned on, the peak voltage also charges the capacitor C _B , so even if the hold switch S _C is turned off and the discharge switch S _A is turned on, The held peak voltage continues as shown in FIG.

If this is put into the visual sensation correction filter 33, the first
This results in jitters as shown in the figure. Also, this filter 33
By connecting a waveform observation device such as an oscilloscope to the oscilloscope, the detected jitter can be observed as a voltage value.

Since the present invention is constructed as described above, it has the following effects.

Since the jitter component is rectified and its peak value, sigma value, average value, effective value, etc. are held, discontinuous jitter as shown in Fig. 1 is displayed continuously, making it easier to measure. Also, since it is displayed quantitatively, jitter can be confirmed concretely.

(b) Since the selection signal is applied to the output of the jitter detector for the time set by the measurement time setting circuit, it is possible to adjust the setting time of the measurement time setting circuit to severely affect only the portion affected by skew distortion. Can be removed. Therefore, more jitter than necessary is not removed, allowing accurate jitter measurement.

(c) Since the selection signal is generated using a vertical synchronizing pulse, it is possible to accurately remove only the jitter in the vicinity of the vertical synchronizing pulse, which is susceptible to skew distortion. Therefore, the jitter that is held is limited to the portion that is not affected by skew distortion, and highly accurate quantitative display can be performed.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of jitter detected by a jitter detection section, FIGS. 2 to 5 are block explanatory diagrams showing different examples of the present invention, FIG. 6 is an explanatory diagram of the configuration of a vertical synchronization pulse detection circuit, and FIG. 7 is an explanatory diagram of the operation of FIG. 6, and FIG. 8 is an explanatory diagram of the configuration of the gate circuit that generates the selection signal.
9 is an explanatory diagram of the operation of FIG. 8, FIG. 10 is an explanatory diagram of the operation of the measurement time setting circuit, B is an explanatory diagram of the operation of the gate circuit, and FIG. 12A and 12B are waveform diagrams for explaining the operation of the rectifier circuit, FIG. 13 is a waveform diagram for explaining the operation of FIG. 3, and FIG. 14 is a waveform diagram for explaining the operation of FIG. 15 is a waveform diagram for explaining the operation of FIG. 5, and FIG. 16 is a waveform diagram for explaining the operation of the jitter detection section in FIGS. 2 to 4. 2 is a vertical synchronization pulse detection circuit, 5, 9, and 10 are gate circuits, 8 is a measurement time setting circuit, 11 is a full-wave rectifier circuit, 12 is a hold circuit, 13 and 13' are indicators, 14 is a comparison circuit, 15 is the buffer circuit, A is the jitter, and D is the part of the jitter that is not affected by skew distortion.

Claims (1)

[Claims] 1 Detect the vertical synchronization pulse from the TV composite signal, use this pulse to create a selection signal, apply this selection signal to the output of the jitter detection section for the time set by the measurement time setting circuit, and measure the effects of skew distortion. Only the jitter that is not affected is extracted, this jitter is rectified, the peak value, average value, effective value, sigma value, etc. is held during the measurement time when the selection signal is applied, and the held jitter amount is displayed on the indicator. A jitter amount display method characterized by quantitatively displaying the amount of jitter in analog or digital form.