JPS6129011B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a system for processing information using a reference clock pulse and controlling the operation of the entire device, particularly in a computer system, by using arbitrary frequency divisions or delays for circuit tests, etc. This invention relates to a method for outputting pulses to a circuit under test.

With the recent development of information processing technology and electronic equipment, various types of automation equipment, including computer systems, generate a reference clock pulse and control the entire equipment based on that clock pulse (hereinafter simply referred to as clock). A method of synchronizing operations is generally used.

As the complexity and reliability of equipment increases, the need to test the operation of each part of the equipment corresponding to this clock also increases, and various test circuits have been proposed for this purpose.

FIG. 1 is a block diagram of an embodiment of a conventional circuit, in which a transfer circuit 10 outputs the output clock a of a clock oscillator 11 to a transmission gate 14, and also outputs it to a clock control circuit 12. 12 transmits a transmission gate signal b as a selection signal to the transmission gate 14 in accordance with instructions from the single-shot continuous command circuit 13 (manual changeover switch or program signal, etc.) during the test.

In the figure, the sending gate 14 which receives the clock a and the sending gate signal b outputs a single or continuous sending clock C depending on the signals, and the sending clock C is sent to the receiving circuit 30 via the transmission line 20. The signal is then input to the receiving gate 31.

In the figure, both the sending gate 14 and the receiving gate 31 are one piece, and the subsequent elements of the receiving circuit 30 are
Supply phase clock X. In this figure, the receiving circuit is a flip-flop (hereinafter abbreviated as FF) 35
A typical circuit terminated in Of course, the circuit configuration does not impose any restrictions on the features of the present invention.

If the signal waveform of the circuit in Figure 1 is continuous, the signal waveform in Figure 2 is
(1) and the case of a single shot are also shown in (2).

In FIG. 2(1), the clock a output from the clock oscillator 11 is "1" for the higher voltage (hereinafter referred to as high level) and "1" for the lower voltage (hereinafter referred to as low level) in this example. Binary information is expressed as "0".

In the figure, since a continuous clock a is to be transmitted, when a continuous command is transmitted from the single continuous command circuit, the sending gate signal b which is the output of the clock control circuit 12 has a value of "1" as shown in the figure. Therefore, when the clock a is "1", the sending gate 14, which is an AND gate, always receives the sending gate signal b "1" at one input, so the sending clock c immediately changes. "1" is transmitted, and therefore clock a and sending clock c become the same continuous pulse.

On the other hand, in the case of a single clock as shown in Figure 2 (2), the first
In the figure, since the single-shot continuous command circuit 13 is set to single-shot, only when a transmission command is input to the clock control circuit 12 by a transmission mechanism (not shown), the transmission gate signal b becomes "1" as shown in FIG. Transmit the value of

Since the sending clock c in FIG. 2(2) becomes "1" only when the clock a and the sending gate signal b become "1", a single pulse is transmitted as a clock as shown in the figure.

Receiving gate 31 provided in receiving circuit 30 in FIG.
receives the continuous or single transmission clock c shown in Fig. 2 (1) and (2) and outputs it as is to the connected circuit.

FIG. 3 shows another embodiment of the conventional circuit. In this figure, the transmission gates of the transfer circuit 10 are 14-1, 1
The transmitting clock a always reaches the receiving gate 31 of the receiving circuit 30 via the transmitting gate 14-1 and the transmission line 20-1. In the case of a test, as in the circuit shown in FIG. 1, the feed gate 14 is
-2, the sending gate signal b reaches the receiving gate 31 via the transmission line 20-2.

Since the circuit shown in Fig. 3 constantly receives clock a, even if the clock cycle becomes high and the pulse waveform becomes distorted due to attenuation due to the transmission line and transient characteristics of the circuit, the receiving gate 31 has a rectifying function. This makes it possible to reliably receive stable clock signals.

However, both circuits require higher-speed clocks, and the functions of the receiving circuit 30 also become more sophisticated.
Due to the increased complexity required, clocks are inadequate for testing, and a wide variety of clocks are needed.

The present invention aims to provide a test pulse transmission control system that satisfies the above-mentioned requirements, and its purpose is to provide a test pulse transmission control system that satisfies the above-mentioned requirements. Testing of a command circuit that outputs a command signal to select an arbitrary clock from a continuous reference clock output from a clock generation circuit, and a test that inputs the command signal and outputs a selection signal to select an arbitrary clock. A synchronous pulse transmission control system comprising a clock circuit, a plurality of transmission circuits for transmitting a continuous reference clock and the selection signal, and a receiving circuit connected to the transmission circuit to form a desired test clock. This can be achieved by

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 4 is a block diagram of an embodiment of the present invention, in which the transfer circuit 10 has n+1 transfer gates 14-0 to 14-0 controlled by a single-shot continuous command circuit 13 operated manually or by program operation (not shown). 14-
The circuit of the conventional device is the same as that of the conventional device explained using FIG. 3 except that it has n.

In the figure, the transmission clock c, which is a continuous reference clock, and the transmission gate signals b-1 to b-n, which are selection signals, are sent from the n+1 transmission gates 14-0 to 14-n to the transmission lines 20-0 to 14-n. 20-n
The clock c corresponds to all of the receiving gates 31-1 to 31-n of the receiving circuit 30 via the terminals _T0 to _T0 , and the sending gate signals b-1 to b-n respectively correspond to the receiving gates 31-1 to 31-n of the receiving circuit 30. Receiving gates 31-1 to 31-n
input for.

In the same figure, receiving gates 31-2 to 31-n
, n-1 delay circuits DL-2 to DL
-n are connected correspondingly, and if the phase of the clock output from the receiving gate 31-1 is X, the phases of the output clocks of the delay circuits DL2 to DLn are X+DL2 to X+DLn, respectively.

5 and 6 show signal waveforms of the circuit of FIG. 4.

FIG. 5 shows the signal waveforms of the X phase to xDLn phase when a continuous clock command is issued from the single continuous command circuit 13 of FIG.

FIG. 5 Wa shows the waveform of clock a in FIG. 4, and the "0" of "1" and "0" having the same period is drawn eight times as large for convenience of explanation Wb ₁ to b _o is the fourth
In the signal waveforms of the transmission gate signals b-1 to b-n shown in the figure, in this example, all “1” signals are output when they are continuous, but other combination methods may be used. The method of the present invention is not limited to the method length of this example.

Wx to Wx+DLn in Fig. 5 are transmission gate signals Wb ₁
Receiving gates 31-1 to 31-3 controlled by ~b _o
1-n, receiving gates 31-2 to 31-
This is a clock waveform obtained by connecting delay circuits DL-2 to DL-n to clock a, where Wx is continuous in the same phase as clock a, and hereinafter W _x+DL-2 to W _x+DL-o A clock waveform delayed by the delay time set based on the circuit requirements appears in the delay circuits DL-2 to DL-n.

Figure 6 shows the waveforms Wb 1 to W _bo of each transmission gate signal b- ₁ to b-n and the clock waveform when a single clock command is issued from a single continuous command circuit.
Indicates Wx to Wx _+DL-o .

Compared to the continuous case in FIG. 5, in FIG. 6, the sending gate signals b-2 to b-n are transmitted sequentially with a delay at a desired interval, so that the waveforms W _b-2 to W _bo are also It can be seen from the figure that the gate signal is transmitted with a delay with respect to the waveform of W _b-1 which is not delayed.

In this figure, the time axis is not uniform for convenience of drawing, but simply shows the chronological order.

In the figure, the clock waveform Wx has no delay, but the clocks of Wx _+DL-2 to Wx _+DL-o appear after the respective desired delay times have elapsed.

As described above, the present invention can reliably apply a variety of test clocks when testing the element circuits of a synchronization system such as an ultra-high performance electronic computer which is highly sophisticated and complicated with a high clock cycle. That is, using the clock that the element circuit is receiving, a gate pulse, which has a greater latitude than the clock pulse and can be reliably transmitted, is transmitted from the transfer circuit manually or by program operation according to the desired test conditions. Since the test clock is formed on the receiving circuit side, various test clocks with good and stable waveforms and accurate phases can be obtained. Therefore, the desired test can be carried out reliably, and highly reliable data can be obtained for use in design materials and maintenance guidelines, which is highly effective.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of a conventional circuit, FIG. 2 is a signal waveform diagram, FIG. 3 is a block diagram of another embodiment, and FIG. 4 is a block diagram of an embodiment of the present invention. , FIG. 5, and FIG. 6 are also signal waveform diagrams. In the figure, 10 is a transfer circuit, 11 is a clock oscillator, 12 is a clock control circuit, 13 and 13' are single/continuous command circuits, 14 to 14-n are transmission gates, and 20 to 20-n are transmission lines. , 30 is a receiving circuit,
31 to 31-n are receiving gates, 35 is a flip-flop circuit (FF), a is a clock, b is a sending gate signal, c is a sending clock, DL-2 to DL-n
is a delay circuit, T ₀ to Tn are terminals, Wa to W _x+DL-o
is the waveform, and X to _XDL-o are the clock phases.

Claims (1)

[Claims] 1. In a device configured with circuits that perform synchronous operations using synchronization pulses as a reference clock, a command circuit outputs a command signal for selecting an arbitrary clock with respect to the continuous reference clock output from a clock generation circuit; a clock control circuit that inputs a command signal and outputs a selection signal for selecting an arbitrary clock; a plurality of transmission circuits that transmit the continuous reference clock and the selection signal; A synchronous pulse transmission control system characterized by being configured with a receiving circuit that forms a test clock.