JPS6129015B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a display method that switches between a fixed three-digit display and a floating point display.

For example, in devices that process monetary data, such as electronic cash registers, floating point numbers have rarely been displayed since amounts are mainly entered. Therefore, the three-digit separator was fixedly set by each country. For example, in Japan, the 4th and 7th digits of an 8-digit display tube are displayed in 3-digit divisions, and in the United States, the 3rd and 6th digits are displayed in 3-digit divisions. However, in recent years, electronic cash registers with a large amount of processing power have been released.For example, the number of products can be expressed as a decimal point, such as 3.5 (items) x 125 (yen). In this case, the decimal point is displayed as a floating point.

The present invention has been made in view of the above circumstances, and detects whether or not decimal point data has been input, and if decimal point data has been input, displays a fixed three-digit separator, and after decimal point data has been input. The purpose of this invention is to provide a display method that performs floating point display.

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a system configuration when the present invention is implemented in an electronic cash register. In Figure 1, 11 is the CPU (processing unit).
The CPU 11 includes a memory circuit 12 that stores various sales data, and a data bus that transfers data D.
DB, row address bus to transfer row address RA
RB is connected through column address CB, which transfers column address CA. The memory circuit 12 is
A read/write signal R/W ₂ sent from the CPU 11 specifies reading or writing. Further, a mode switch 13 is connected to the CPU 11 via a data bus DB. This mode switch 13 is used to switch and specify various modes such as rounding, rounding down, rounding up, and specifying the position of 3-digit delimiters, the details of which will be described later.It selects the mode detection signal MS from the CPU 11 and uses the data bus DB Send to CPU11. Further, an I/O port 14 is connected to the CPU 11 via a data bus DB and a column address bus CB. An operation signal J is applied to this I/O port 14 from the CPU 11. A key input section 15, a display section 16, and a printing section 17 are connected to the I/O port 14. When the key input unit 15 performs a key operation, the I/O port 1
The key input signal KI is input to an input buffer (not shown) in the I/O port 14 in accordance with the timing signal KP from the I/O port 4. Further, the display section 16 performs a display operation in accordance with the digit signal DG from the I/O port 14 and the segment signal SG obtained by decoding the data in the display buffer of the I/O port 14. The printing unit 17 is, for example, a line printer, which sends a print position signal T from a print drum to the I/O port 14, and combines this print position signal T with data in a print buffer (not shown) of the I/O port 14. The hammer is driven by a hammer drive signal HD generated by the coincidence, and printing is performed on receipt paper and journal paper.

FIG. 2 shows details of the mode switch 13, in which there are a plurality of switches S ₁ to _{S o} for specifying modes.
are arranged in a matrix of 4 rows and 16 columns, and 0 sent from the CPU 11 to the input line of each column.
~15 mode detection signals MS are input, and the "1-2-4-8" weighted signal outputted by the 4 output lines is the mode designation signal.
It is now sent to the CPU 11.

Next, the main part of the I/O port 14, that is, the part related to data exchange with the display section 16 will be explained with reference to FIG. Data input via data input/output terminal D by data bus DB is supplied to decimal point buffer 21 and sent via gate circuit 22 to 16-digit display buffer 23 constituted by RAM. The contents of 0 to 14 digits of the A register (not shown) for input/output in the CPU 11 are written into this display buffer 23.
The held data is sent to the display unit 16 via the segment decoder 24. In addition, the above buffer 2
1 is where the decimal point data stored in the 15th digit of the A register is written, and the held data is sent to the AND circuit 26 via the decimal point decoder 25.
is input to. A gate control signal is input to this AND circuit 26 from the segment decoder 24 via an output line a. The segment decoder 24 outputs a "1" signal to the output line a when decoding numerical data from 0 to 9, and outputs a "1" signal to the output line a when decoding a code signal other than the numerical data from 0 to 9, that is, a blanking code signal. Outputs a “0” signal to a. The output of the AND circuit 26 is sent to the display section 16 as a segment signal for displaying decimal points or three-digit divisions.
Further, the output of the hexadecimal counter 27 is applied to the decimal point decoder 25 via a digital decoder 28 as a timing signal. Further, the output of the digital decoder 28 is a digital signal.
It is sent to the display section 16 as DG. On the other hand, CPU1
The operation signal J given from 1 and the column address CA given via the address bus CB are input to the control decoder 29. This control decoder 29 has an output line a that outputs a "1" signal when column address CA is "1" and an output line b that outputs a "1" signal when column address CA is "15". The signal output from line a is input to the set terminal S of flip-flop 30, and the signal output from output line b is input to reset terminal R of flip-flop 30 and is sent to buffer 21 as a data read signal. And flipflop 30
The Q side output of is an AND circuit 31 and a gate circuit 22.
It is added as a gate control signal to the display buffer 23 as a read/write signal R/W. Further, the side output of flip-flop 30 is applied to AND circuit 32 as a gate control signal. The column address CA is input to the AND circuit 31 via the address bus CB, and the value of the counter 27 is input to the AND circuit 32. The outputs of the AND circuits 31 and 32 are sent as address data to the display buffer 23 via an OR circuit 33.

Figure 4 shows the decimal point decoder 2 in Figure 3 above.
This shows the details of 5. 41 in Figure 4
is a decoder into which the 4-bit decimal point data from the decimal point buffer 21 is input;
Decode the decimal point data of “2”, “8” to “15” and output “1” from one predetermined output line.
Output a signal. The signals output from the output lines "15" to "9" of this decoder 41 are input to AND circuits 43a to 43g via OR circuits 42a to 42g, respectively. Further, the signal output from the output line "8" of the decoder 41 is directly input to the AND circuit 43h. Furthermore, the signal output from the output line "2" of the decoder 41 is OR circuit 42c and 42f.
The signals output from the "1" output lines are input to OR circuits 42a, 42d, and 42g, and the signals output from the "0" output lines are input to OR circuits 42b and 42e, respectively. The AND circuits 43a to 43h also receive digit signals D7 to _D7 .
D ₀ is input respectively. The outputs of the AND circuits 43a to 43h are output through an OR circuit 44, and sent to the display section 16 as a decimal point segment drive signal via the AND circuit 26. In this case, the first to eighth digits of the display section 16 are selected and designated by the digit signals D ₀ to D ₇ . As shown in FIG. 5, the decimal point decoder 25 configured as described above outputs a 3-digit display signal when decimal point data of "0" to "2" is given, and If decimal point data of "" is input, a signal for displaying a decimal point of a predetermined digit according to the content is output, and the operation mode for floating point is entered. When using the above 3-digit display, if the decimal point data is "0", a decimal point signal is output at the timing of the 4th and 7th digits, and the 3-digit display mode in Japan corresponding to the yen is set, and the decimal point data is "2". ”, a decimal point signal is output at the timing of the 3rd and 6th digits, resulting in a US digit separator display mode for the dollar. If the decimal point data is "1", a decimal point signal is output at the timing of 2nd, 5th, and 8th digits, and a digit separator display mode is established for cases other than yen and dollars.

Next, the overall operation of the present invention constructed as described above will be explained with reference to the flowchart of FIG. When a numeric key is operated on the key input unit 15, this input data is sent to the I/O port 14, where numeric value processing is performed as shown in step A of FIG. That is, data input from the key input unit 15 is temporarily held in an input buffer (not shown) in the I/O port 14, and then
The data is transferred to the A register (not shown) in the CPU 11. When the CPU 11 receives input data via the I/O port 14, the CPU 11 inputs the most significant digit of the A register, that is, the 15th digit, as shown in step B of FIG.
Determine whether the content of _A15 is less than "8" (binary number "1000") or greater than "8". Decimal point data is written to the 15th digit of this A register, and if the decimal point key is operated, it will be "8".
If the above value is written, and the decimal point key is not operated, a value smaller than "8", for example, in this embodiment, a value from "0" to "2" is written. However,
In step B, it is determined whether the 3-digit delimiter mode is floating point mode, and the 15th digit _A15 of the A register is
If the content is "8" or more, it is determined that the floating point mode is in effect, and the program proceeds to step C, where the 15 of register A is stored.
Add 1 to the contents of the digit. Through the processing of step C, the position of the decimal point is moved up by one digit. In other words, when the decimal point key is operated, "8" is placed in the 15th digit _A15 of the A register as shown in step D.
(1000) is written. And this step D
is carried out, or if the processing in step C is carried out, proceed to step E, read out the setting contents of the mode switch 13, and read out the setting contents of the mode switch 13.
Set the 15th digit of the register to _B15 . Next, proceed to step F, and check whether the content of the 15th digit _A15 of the A register is less than or greater than "8" (1000), that is,
Determine whether floating point mode or 3-digit delimited display data. As a result of this judgment, the 15th digit of the A register A ₁₅
If the content of is ``8'' (1000) or more, it is determined that the decimal point key has been operated, so it is determined that the floating point mode is in effect, and the process proceeds to step G, where the contents of the A register are shown in Figure 4. Send to I/O port 14. In this case, first, before reading the contents of the A register, a control signal is given to the control decoder 29 in the I/O port 14 via the address bus CB, and a timing control circuit (not shown) in the CPU 11 sends an operation signal. Signal J (“1”)
Output. The control signal is decoded by the control decoder 29, and the flip-flop 30
Set. When flip-flop 30 is set, its Q-side output opens AND circuit 31 and gate circuit 22, and a write signal (R/W="1") is applied to display buffer 23. In this state, when the contents of the A register in the CPU 11 are sequentially read from the 1st digit to the 14th digit, the contents are transferred from the CPU 11 to the display buffer via the data bus DB and the gate circuit 22 in the I/O port 14. 23. At this time, data CA of the CPU 11 is applied to the I/O port 14 via the data bus CB, and the column address of the display buffer 23 is applied to the display buffer 23 via the AND circuit 31 and the OR circuit 33. At this time, the operation signal J is "0". Then, when the content of the address data CA becomes "15", the flip-flop 30 is reset by the output of the control recorder 29. As a result, the gate circuit 22 is closed and input to the display buffer 23 is prohibited, and the decimal point buffer 21 is operated by the signal output from the output line b of the control decoder 29, and the contents of the 15th digit of the A register are changed to a decimal point. The data is read into the buffer 21. The decimal point data read into the decimal point buffer 21 is input to the decimal point decoder 25. At this time, if display data is stored in the display buffer 23, a "1" signal is output from the output line a of the segment decoder 24 and the gate of the AND circuit 26 is opened, so the decimal point decoder 25 The output is sent to the display unit 16 via the AND circuit 26, and a predetermined decimal point segment is displayed by lighting. For example, when the decimal point data is "8" as described above, the decimal point decoder 25 is transferred to the decoder 4 as shown in FIG.
The output line of "8" of 1 becomes "1" and is added to the AND circuit 43h. This AND circuit 43h
Since the digit signal D ₀ is input to
According to the output of the decoder 41, the AND circuit 43
A digit signal _D0 is output from h and sent to the display section 16 via the OR circuit 44, where a decimal point is displayed in the first digit as shown in FIG. In this case, data reading from the display buffer 23 is performed by the output of the counter 27. That is,
When the flip-flop 30 is reset by the output of the control decoder 29, the gate of the AND circuit 32 is opened by the output on that side, and the output of the counter 27 is sent to the display buffer 23 via the AND circuit 27 and the OR circuit 33. Address is specified. By this address designation, the contents of the display buffer 23 are read out and sent to the display unit 16 via the segment decoder 24 for display. When the next numerical data is input in this state,
Proceeding to step C via steps A and B, the contents of the 15th digit _A15 of the A register are incremented by 1. If you want to input the first numerical data after operating the decimal point key, enter "8" in the 15th digit of the A register, _A15 .
(1000) has been written, so in step C, addition of "8+1=9" is performed, and the A register is
A The content of the _15th digit is "9", and the decimal point displayed on the display section 16 is the second digit as shown in FIG.
Thereafter, each time a numeric operation is performed, the contents of the _15th digit A of the A register are sequentially incremented by 1, and the decimal point display position is sequentially carried forward as shown in FIG.

On the other hand, if the decimal point key is not operated, step D will not be executed and step F will be executed.
The content of the 15th digit _A15 of the A register is "8".
(1000), and the process proceeds to step H. Below this step H is the mode switch 13 set in the 15th digit of the E register at step E.
Transfer the setting contents to the 15th digit _A15 of the A register. Thereafter, the process proceeds to step G, where the contents of the A register are transferred to the display buffer 23 and decimal point buffer 21 in the I/O port 14. If the setting content of the mode switch 13 is domestic mode,
The setting value of the mode switch 13 is "0", and a "1" signal is output from the "0" output line of the decoder 41 in FIG. It will be done. Therefore, the digital signals D ₃ and D ₆ are outputted from the AND circuits 43e and 43b, and the fourth and seventh digits of the display section 16 are displayed separately as shown in FIG. Also, if the US mode is specified by the mode switch 13, the setting content is "2".
A "1" signal is output from the "2" output line of the decoder 41, and the OR circuits 42f, 42c
It is applied to AND circuits 43f and 43c via. Therefore, the digital signals D ₂ and D ₅ are outputted from the AND circuits 43f and 43c, and the third and sixth digits of the display section 16 are displayed separately as shown in FIG. In this manner, arbitrary three-digit division display is performed according to the designation of the mode switch 13. Furthermore, when the decimal point key is operated, the 3-digit display is switched to the floating point display as described above.

As described above, according to the present invention, it is detected whether or not decimal point data has been input, and if decimal point data has not been input, a fixed three-digit display is performed, and even after decimal point data has been input, It is designed to perform floating point arithmetic, and can be realized with a simple circuit configuration. It has various advantages such as automatic switching between floating point display and fixed 3-digit display.

[Brief explanation of the drawing]

Fig. 1 is an overall block diagram showing one embodiment of the present invention, Fig. 2 is a diagram showing details of the mode switch portion in the same embodiment, and Fig. 3 is a main part of the I/O port in the same embodiment. 4 is a configuration diagram showing details of the decimal point decoder portion in the same embodiment, and FIG. 5 is a diagram for explaining the decimal point and three-digit separator display operation of the display unit in the same embodiment. FIG. 6 is a flow chart showing the operation of the same embodiment. 11...CPU, 12...Memory circuit, 13...
...Mode switch, 14...I/O port, 23
... Display buffer, 25... Decimal point decoder.

Claims (1)

[Claims] 1. Storage means for storing floating point display data or fixed 3-digit display data, detection means for detecting whether decimal point data has been input, and decimal point data being input by the detection means. means for inputting predetermined floating point display data into the storage means when it is detected that decimal point data has not been input; A display system comprising means for inputting data for digit separator display into the storage means, and display means for displaying a decimal point or a fixed three-digit separator based on each decimal point or three-digit separator data in the storage means. .