JPS6129016B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data processing system suitable for, for example, a display device having a single-screen refresh memory.

2. Description of the Related Art Display devices are used as computer terminal equipment or for other purposes, and some display devices have a refresh memory. This type of display device is capable of displaying not only symbols such as numbers and letters, but also graphical displays, or a cursor for instructions as needed, and is equipped with memory for this purpose. However, in conventional devices of this type, the image display memory is a so-called random access memory in which writing and reading are performed in units of a fixed word length, and therefore the coordinates of data storage are limited.
That is, since writing and reading are performed in units of a fixed word length, it is not possible to rewrite or erase data from arbitrary coordinates, such as in the middle of this fixed word length. One way to avoid this restriction is to make memory randomly accessible in units of 1 dot, but in this case, it takes a long time to write and read data because it has to be processed in units of 1 dot, resulting in a slowdown. There are drawbacks.

The present invention improves these points and allows writing from any coordinate point, removing unnecessary data dot by dot, and combining already stored data with new data while using a storage memory that can be randomly accessed. The present invention provides a data processing method for writing data into an image display memory that enables overlapping storage.

An embodiment of the present invention will be described below with reference to the drawings. In the present invention, since the address of the random access memory described later is a binary number, it is convenient for processing certain data to have a length of 2 ⁿ (n = 1, 2, 3
. The data length for writing or deletion is also 8 bits. Of course, it does not have to be limited to 2 ⁿ , and can be set to any length. In Figure 1, 1 and 2 are 8-bit (equal to the data length) parallel in, parallel out, and shiftable first and second registers, 3 is an 8-bit register that stores memory data read from memory, and 4 is an 8-bit register that can be shifted. 5 is an 8-bit register with a number of bits equal to the data length and capable of parallel output; 5 is an 8-bit register with a number of bits equal to the data length and capable of parallel output. Further, 6, 7, and 8 are the first, second, and third complementers provided on the output side of the registers 3, 4, and 5, respectively, and 9, 10, and 11 are each of the complementer 7 and the registers 1 and 2. 12 is an AND circuit provided at the output side of the complementer 6 and the OR circuit 9;
3 is a data selector provided on the output side of the OR circuits 10 and 11 and selects and outputs one of the data from the two sides; 14 is a random access memory;
15 is a main timing generation circuit that generates timing pulses to each part; 16 is a flip-flop circuit; 17 is an adder; 18 is a clock generation circuit;
Address registers 9 and 20 respectively correspond to the X-axis and Y-axis of the display device. Further, 21 and 22 are X-axis coordinates and Y-axis coordinates on the screen in units of one dot, 23 is data for writing or deletion, 24 is data in the random access memory 14, an address line, and 25 is the random access memory. Read data, 26 is write data, 2
7 and 28 are address data of the random access memory 14.

The first, second and third complementers 6, 7 and 8 are exclusive OR circuits 301 and 30 as shown in FIG.
2,...,30n are connected in parallel, and the first
The OR circuit 9 is connected to the output terminal of the main timing generation circuit 15 as shown in FIG.
1,..., 40n are connected in parallel, and the second and third OR circuits 10, 11 are composed of a plurality of OR circuits 501, 502,..., 50 as shown in FIG.
n are connected in parallel to registers 1 and 2 and an AND circuit 12, respectively, and the AND circuit 12 has a first complementer 6 and a first OR circuit 9, as shown in FIG.
It is constructed by connecting AND circuits 601, 602, . . . , 60n in parallel.

Next, the operation will be explained separately for each case.

(a) For writing (data length is 8 bits ²³ ) Arbitrarily given X-axis and Y-axis coordinate values 21,
22 is input to the address registers 19 and 20, and at the same time, new input data 23 to be written to the first register 1 is input. By the way, in this device, input to the random access memory 14 is performed in units of 1 byte (8 bits), so in order to write 1 byte from an arbitrary coordinate in the middle of a fixed word length of the address of the random access memory 14, It is necessary to shift the input data. As mentioned above, since the data length is ²³ , the value of the lower 3 bits of the X-axis coordinate value 21 input to the address register 19 becomes a value indicating from which dot the data is input. Therefore, the data in register 1 may be shifted according to this value. That is, the data of the X-axis coordinate value 21 is inputted from the address register 19 to the clock generation circuit 18, and this clock generation circuit 18 is driven by the timing pulse from the main timing generation circuit 15. In other words, the clock generation circuit 18 is composed of a counter decoder, and generates a clock pulse corresponding to the number to be shifted based on the data obtained from the lower three bits of the coordinate value 21, and this clock pulse is sent to registers 1, 2, and 4. Can be added. In this way, the value to be shifted is determined.

Therefore, the data input to register 1 is shifted by a predetermined number, and the data output by this shift is input to register 2. Also, the serial input of register 1 shifted at this time is set to "0", while register 2
Clear the contents in advance. This shift is also performed on the register 4 at the same time, and "1" is added to the input of this register 4, but it is cleared in advance so that the initial value is all "0".

For example, if the lower 3 bits of the X-axis coordinate value 21 indicate "5" in this state,
The input data is shifted by five, and this new input data is stored across the first and second registers 1 and 2 as shown in Figure 6a, and register 4 also becomes as shown in Figure 6b. .

Also, read data 25 corresponding to write data 23, that is, one byte of data at one of the adjacent addresses to which new input data should be input, is input to register 3, and at this time, one byte of data is input to register 3.
If it is AAAAAAAAA, the contents of register 3 will be as shown in Figure 6c. The output of register 3 is applied to AND circuit 12 through complementer 6, and the output of register 4 is applied to AND circuit 12 through complementer 7 and OR circuit 9. As shown in FIG. 2, these complementers 6 and 7 receive a timing pulse from the main timing generation circuit 15 as a complement (valid "1" signal) to one input of each exclusive OR circuit 301, 302, ..., 30n. The outputs are passed through the OR circuits 401, 402, ..., 40n shown in FIG. 3, or directly to the AND circuits 601, 601, 40n shown in FIG.
602, . . . , 60n, respectively, are applied to different input terminals. In this way, the AND circuit 12 performs an AND operation on the outputs of the registers 3 and 4, resulting in data as shown in FIG. 6d. The data in FIG. 6d is led to OR circuits 10 and 11, and registers 1 and 2
is logically ORed with the output of In reality, each OR circuit 10, 11 is an OR circuit 50 as shown in FIG.
The outputs of the AND circuits 601, 602, . . . , 60n are led to one input terminal of the registers 1, 502, . That is, the OR circuit 10 overlaps the output of the register 1 and the ANDed data of the registers 3 and 4 obtained by the AND circuit 12, resulting in data as shown in FIG. 6e. This value is selected by the data selector 13 and guided to the register 5, and the data in FIG. 6e becomes the contents here. At this time, the data selector 13 passes only the output of the OR circuit 10, and the OR circuit 9 from the main oscillator 15, the complementers 6, 7, 8
The input to is "0".

In this way, the output of register 5 is the complementer 8
through the data address line 24,
Leads to random access memory 14, originally
Store it at the address that contained the data AAAAAAAA.

Next, read the data BBBBBBBB stored at the address next to AAAAAAAAA and input it to register 3. And similar to the above process,
The complement of the output of register 3 and the contents of register 4 (FIG. 6b) is ANDed. This process consists of complementer 7 and AND circuit 1.
2, and the data shown in FIG. 6f is obtained. Next, the output of the AND circuit 12 and the contents of the register 2 are led to the OR circuit 11, where they are superimposed, and the result is led to the register 5 by the data selector 13, whose contents are shown in FIG. It becomes like this. This data is transferred to random access memory 14 via data line 24.
Guided by this, this data is stored at the address where BBBBBBBB was originally located. Then, the data of *** that was to be newly written is embedded in the random access memory 14 as shown in FIG. 6h, and the writing operation is completed.

(b) Data erasure Provide data that makes the dot to be erased a valid “1”.

(a) In the case of this erasure, each register 1, 2, and 4 is shifted in the same manner as explained in (a). If the number of shifts is "5", the contents of registers 1 and 2 will be as shown in FIG. 7a.
In other words, 5 to 7 in register 1, 0 in register 2
Erasure data of 11000101, where "1" means erasure, is input to 4. Also, the contents of register 4
The result is shown in FIG. 7b, which is the same as in (a). On the other hand, the random access memory 14 contains data AAAAAAAA as shown in FIG. Then, the signal line 29 is enabled by the output of the main timing generation circuit 15, and the register 3 is activated by the first complementer 6.
The complement of the output of is retrieved. Simultaneously with this complement, the signal line 30 becomes valid, and the output of the register 4 obtained through the first OR circuit 9 is led to the AND circuit 12, where an AND is taken, and its contents are transferred to the second OR circuit 10. is overlapped with the output of register 1, and data selector 13
and is input to the register 5 by a signal via a signal line 31 from the main timing circuit 15. Since the signal line 29 is active at this time, the output of the register 5 is further complemented by the third complementer 8 and written to the random access memory 14 through the data line 24. At this time, the complement of register 5 (assumed to be 1) is as shown in Figure 7d.
It becomes AAAAA00A.

On the other hand, the data stored in the register 2 is also overlapped with the output of the AND circuit 12 by the third OR circuit 11, as explained in (a), and sent to the register 5 through the data selector 13, and then sent to the third complementer 8. The complement is taken by . The complement in this case (taken as 2) is as shown in Figure 7e.
BB0B0BBB and is written to the random access memory 14 via the data line 24. As a result, as shown in FIG. 7f, the portion into which the erase data has been input becomes 00ABB0B0, and the desired dot is erased.

(c) Overlap storage of data In this case, the so-called data clipping operation based on the output of the register 4 is not performed, but the write operation described in (a) can be performed. In other words, all the outputs of the first OR circuit 9 are made valid by the signal from the signal line 30 of the main timing generation circuit 15, and the data in register 1 and the data in register 3 are written in a superimposed manner. By writing data in which the data in register 2 and the data in register 3 are overlapped, partial overlap storage is performed in the random access memory 14.

In this way, if this data processing method is used, by shifting and inputting data from any part of the coordinate axes according to its position, partial rewriting, partial dot-by-dot erasure, and Partial overlapping memory can be done arbitrarily.

For example, when applied to a display device, it is possible to write from any coordinate point as long as it has refresh memory for one screen.
Moreover, data can be erased, and line segments in graphic operations (erasing arbitrary areas on the screen) can be performed with a single signal. In other words, if the same erase signal that has been written so far is applied from the outside, the data that has been written so far can be erased. Furthermore, since it is possible to overwrite text, it is also possible to display symbols such as x on ruled lines or characters, which greatly improves usability.

Furthermore, if applied to a printer, it becomes possible to print in any format, similar to a display device.

As described above, according to the present invention, it is possible to provide a data processing method that enables writing, erasing, and overlapping storage from arbitrary coordinate axes while operating in units of a fixed word length.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a data processing method according to an embodiment of the present invention, FIG. 2 is a block diagram showing the complementer in FIG. 1, and FIG. 3 is a block diagram showing the first OR circuit in FIG. FIG. 4 is a diagram showing the second and third OR circuits in FIG. 1; FIG. 5 is a diagram showing the AND circuit in FIG. 1. , FIG. 6 is a diagram for explaining the rewriting operation of the data processing method of FIG. 1,
FIG. 7 is a diagram for explaining the erasing operation of the data processing device of FIG. 1. 1, 2, 3, 4, 5...Register, 6, 7, 8
... Complementor, 9, 10, 11 ... OR circuit, 12
...AND circuit, 13...Data selector, 14
... Random access memory, 15 ... Main timing generation circuit, 18 ... Clock generation circuit.

Claims (1)

[Scope of Claims] 1. In a data processing method in which writing and erasing are performed using a randomly accessible storage memory with a predetermined constant word length, a second shift register that is provided in series with the first shift register and has a capacity of the constant word length, and input address data is placed in the middle of the constant word length at an adjacent address of the memory. means for shifting the new input data when a position is specified and storing the new input data in the first and second shift registers so as to correspond to adjacent addresses in the memory; means for reading the data at the matching address and cutting out the newly inputted dot portion; and inputting each adjacent one-word length data from which the required dot portion has been cut out by this means into the first and second shift registers. A data processing method comprising means for superimposing stored data and writing it into the memory. 2. Claim 1, characterized in that the read data at adjacent addresses is written into the memory in a superimposed manner with the data stored in the first and second shift registers without being cut out. Data processing method described in section.