JPS6129554B2 - - Google Patents

Description

[Detailed Description of the Invention] (1) Field of Application of the Invention The present invention relates to the shape of impurity concentration distribution of a diffusion device in a semiconductor device and its formation method, and relates to a structure with high breakdown voltage, wiring with low resistance, easy workability, The present invention also relates to a semiconductor device with stable element characteristics and a method for manufacturing the same.

(2) Prior Art With the miniaturization of semiconductor devices, it is required to form a diffusion layer with a shallow depth, and there is a tendency for impurities with a small diffusion coefficient to be used for this purpose. At this time, since the impurity concentration of the formed junction changes rapidly, the breakdown voltage of the junction decreases. This phenomenon not only ultimately leads to a reduction in the operating power range of the device, but also shortens the stable operation life of the device.

(3) Purpose of the Invention Therefore, the present invention provides a method for manufacturing a semiconductor device with a high breakdown voltage structure, in which impurities with a large diffusion coefficient are diffused at a low concentration at the junction interface in order to alleviate the gradient of impurity concentration at the junction. The purpose is to provide.

(4) General description of the invention In particular, when diffusing impurities twice at high concentration and once at high concentration in order to realize a miniaturized semiconductor device, the gate electrode is used twice in a self-aligned manner. A manufacturing method is used in which the electrode widths are also different. 900 as a way to change the gate electrode width.
A low-temperature oxidation method below ℃ is used.

(5) Examples Hereinafter, the present invention will be explained in detail with reference to examples. Two examples will be described.

In the first embodiment, a semiconductor device and its manufacturing method will be described in A and B of FIG. In A of Fig. 1, an oxide film is formed on the substrate 1 by thermal oxidation at 1000°C for 60 minutes.
After depositing polycrystalline silicon containing a high concentration of phosphorus to a thickness of 4000 Å, a gate insulating film 2 and a gate electrode 3 are formed using photoresist processing technology, and then phosphorus is added as an impurity at an accelerated voltage.
The figure shows the formation of diffusion layer regions 4-1 and 4-2 with a final diffusion depth of 0.2 μm after ion implantation of 1×10 ¹⁴ cm ⁻² at 40 keV and a heat treatment process. B in FIG. 1 shows the subsequent manufacturing process; first, oxide films 5-1 and 5-2 with a thickness of 500 Å are formed on the substrate by a wet oxidation method at 750°C. At this time, since polycrystalline silicon contains impurity phosphorus at a high concentration, an oxide film 5-3 with a thickness of 3000 Å is formed around the gate electrode 3. After that, arsenic is ion-implanted at 1×10 ¹⁶ cm ^-2 at an acceleration voltage of 150 KeV, and after a heat treatment process, diffusion layers 6-1 and 6-2 with a final diffusion depth of 0.4 μ are formed, and a MOS type electric field is formed. This shows how the effect transistor has been realized. At this time, since the diffusion layers 4-1 and 4-2 in contact with the gate electrode 3 are formed shallowly and with low concentration, the impurity concentration gradient at the junction interface is gentle, and the electric field concentration due to the operating bias is alleviated at the edge of the drain region. It's structured. Therefore, higher voltage resistance of the element has been achieved.

In the second embodiment, a semiconductor device and its manufacturing method will be described in A and B of FIG. The only difference from the first embodiment is the shape of the diffusion layer and its formation method, and only this point will be described in detail. In Figure 2A, diffusion regions 4-1 and 4-2 diffuse phosphorus to a low concentration of 1×10 ¹⁸ cm ^-3 so that the final diffusion depth after the heat treatment process is 0.4μ. This is up to the point where it was formed. Furthermore, in B of FIG. 2, the diffusion regions 6-1 and 6-2 are exposed to the
The figure shows how a MOS field effect transistor was realized by implanting 5×10 ¹⁵ cm ^-2 ions at 150 KeV and forming the final diffusion depth to 0.3 μ after a heat treatment process. At this time, since the diffusion layers 4-1 and 4-2 in contact with the gate electrode 3 are formed with a low concentration, the gradient of impurity concentration in the junction boundary layer exceeds 0.2μ, so the electric field is concentrated due to the operating bias at the end of the drain region. has become a relaxed structure. Therefore, higher voltage resistance of the element has been achieved.

Although two embodiments have been described above, it must be noted that various modifications may be made based on the spirit of the present invention. For example, a bidirectional DSA can be created by simply going through the same manufacturing process as the second embodiment.
It is possible to manufacture MOS transistors with this structure.
However, in this case, a P-type substrate with a relatively high resistance of 150 Ωcm is used as the substrate shown in Figure 2, and a P-type impurity such as boron is finally diffused at a concentration of 10 ¹⁷ cm ^-3 to form a low concentration layer. Form to a depth of approximately 1.0μ. The MOS transistor with this bidirectional DSA structure not only has improved drain breakdown voltage, but also has a shorter channel length, which is more than twice that of the conventional structure, as the effective channel length is determined approximately by the diffusion depth of the P-type impurity. The device operation speed has been increased.

(6) Summary As explained above, according to the present invention, a high breakdown voltage of the device has been realized, and in a MOS field effect transistor with a channel length of 5μ, the breakdown voltage of the device of the conventional structure has been improved.
This structure reduces the voltage from 13.0V to 15.5V, achieving a nearly 20% increase in voltage resistance. This improvement will maximize the element
When used at 8V, this corresponds to an improvement of more than 10 times the stability of device characteristics or operating life.

Further, according to the present invention, when forming the impurity distribution of the high breakdown voltage structure, the gate electrode is used twice in a self-aligned manner, thereby realizing a high-density design. Compared to the past,
This can be achieved with a gate area of 1/1.5 to 1/2.
Furthermore, since it is self-aligning, variations in the high voltage resistance effect can be reduced and uniform characteristics can be achieved.

[Brief explanation of the drawing]

FIGS. 1A and B and FIGS. 2A and B are cross-sectional views showing a MOS field effect transistor provided by the present invention.

Claims (1)

[Claims] 1. Using a gate electrode for a field effect transistor as a mask, impurities at a first concentration are implanted into the surface of a semiconductor substrate to form a first impurity region, and then the gate electrode is oxidized to form a first impurity region. Using the oxidized gate electrode as a mask, a second impurity having a concentration higher than the first concentration is implanted into the substrate surface to form a second impurity region deeper than the first impurity region. . A method of manufacturing a semiconductor device, comprising forming a source or drain region made of a second impurity region. 2. The method of manufacturing a semiconductor device according to item 1, wherein the gate electrode is formed of polycrystalline silicon into which impurities are implanted. 3 Using the gate electrode for a field effect transistor as a mask, impurities at a first concentration are injected into the surface of the semiconductor substrate to form a first impurity region, and then the gate electrode is oxidized, and the gate electrode of the oxide is used as a mask. implanting a second impurity at a concentration higher than the first concentration into the substrate surface to form a second impurity region shallower than the first impurity region within the first impurity region; A method of manufacturing a semiconductor device, comprising forming a source or drain region made of first and second impurity regions. 4. The method of manufacturing a semiconductor device according to item 3, wherein the semiconductor substrate is subjected to heat treatment after forming the first impurity region and before forming the second impurity region. 5. The method of manufacturing a semiconductor device according to item 3, wherein the gate electrode is made of polycrystalline silicon doped with impurities.