JPS6129557B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a junction field effect transistor, particularly a high frequency junction field effect transistor made of gallium arsenide (Ga.As).

The element that essentially determines the frequency characteristics of a field effect transistor (hereinafter abbreviated as FET) as an element is the speed at which the carrier transmits the channel length.

In order to improve the frequency characteristics of FETs, materials that allow the carrier to quickly transmit the channel length, such as gallium arsenide (GaAs), have been developed, and many attempts have also been made to shorten the channel length. ing. However, with currently widely used photoetching processes, it is difficult to reduce the channel length to less than about 1 μm.

SUMMARY OF THE INVENTION The present invention provides a new manufacturing method for manufacturing FETs whose channel lengths are significantly narrower than those of conventional FETs using conventional photoetching processes.

For that purpose, the method for manufacturing a semiconductor device of the present invention includes sequentially stacking first and second mask films on the surface of a semiconductor substrate, and partially removing the first and second mask films. A window with a step-like cross section is formed at the boundary between the first and second mask films, and the substrate surface in the region of the window is removed to form an eave shape between the first and second mask films. After forming a V-groove, an epitaxial layer is formed on the inner wall of the V-groove, and an insulating layer is partially formed on the epitaxial layer using the first, for example, second mask film as a mask. After removing the second mask film, a gate metal layer is partially deposited on the insulating layer and the epitaxial layer using the first mask film as a mask, and a gate metal layer is formed between the gate metal layer and the epitaxial layer. The invention is characterized in that a shot key barrier contact is formed between the two, and examples thereof will be described in detail below.

According to the present invention, the following steps are taken.

(1) As shown in Figure 1, the thickness is approximately 3.0 [μm] on an N ⁺ type gallium arsenide (Ga・As) substrate 1.
The thickness of the semi-insulating gallium/arsenic layer 2 is approximately
A 1.0 [μm] N ⁺ type gallium/arsenic layer 3 is continuously grown. Next, a silicon dioxide (SiO _{2 ) layer 4 with a thickness of about 0.5 [μm] is further applied on top of the silicon dioxide (SiO 2} ) layer 4.
A 0.5 [μm] silicon nitride Si ₃ N ₄ layer 5 is deposited by a method such as sputtering.

Note that the silicon dioxide layer 4 will be used later as a first mask material, and the silicon nitride layer 5 will be used as a second mask material.

(2) Next, as shown in FIG. 2, after opening a window 6 with a width of, for example, 3 [μm] in the silicon nitride layer 5,
Using the silicon nitride layer 5 as a mask material, the underlying silicon dioxide layer 4 is etched. By this etching, the silicon dioxide layer 4 is overetched to form an undercut portion 7, and a window 6' having a reverse stepped cross section is formed. Note that the step width δ ₁ of the undercut portion 7 is
Adjust the etching time to 0.5 [μm].

Thereafter, using the silicon dioxide layer 4 and the silicon nitride layer 5 as masks, the N ⁺ type gallium/arsenic layer 3, the semi-insulating gallium/arsenic layer 2, and the N ⁺
Etching the molded gallium arsenide substrate 1 using, for example, a KOH-based anisotropic etching solution,
A V groove 8 having a V-shaped cross section is formed. After that V
An N-type gallium-arsenic layer 9 is epitaxially grown on the inner surface of the groove 8. Note that the thickness of the N-type gallium-arsenic layer 9 is about 0.2 to 0.5 [μm].

(3) Next, as shown in FIG. 3, a silicon dioxide layer is sputtered in a direction perpendicular to the substrate, and silicon dioxide 10 is deposited on the bottom of the V-groove 8. Note that the width D ₁ of the deposited silicon dioxide layer 10 is approximately the same as the width of the window 6 .

(4) Next, after peeling off the silicon nitride layer 5, which is the second mask film, as shown in FIG.
A gate metal layer 11 is formed at the bottom of trench 8 . A portion 12 where this gate metal layer 11 and the N-type gallium arsenide layer 9 are in contact constitutes a gate portion due to Schottky barrier contact, and the gate length Lg is Lg=δ ₁ /Cosθ... It is determined by ……………(1). However, Cos θ is the cosine of the angle between the wall surface of the V-groove 8 and the substrate surface.

(5) Next, after peeling off the silicon dioxide layer 4, which is the first mask layer, a silicon dioxide layer is deposited on the entire surface by chemical vapor deposition (CVD), and then electrode windows are made by a well-known method. , conduct electrode wiring. FIG. 5 is a cross-sectional view after electrode wiring is done, and in the figure, 13 is a silicon dioxide layer covering the surface, 14 is a gold/germanium layer, and 14 is a gold/germanium layer.
The drain electrode layer made of gold maintains ohmic contact with the N-type gallium arsenide region that will become the drain region. Reference numeral 15 denotes a source electrode layer made of gold/germanium-gold provided on the back surface of the N ⁺ type gallium/arsenide substrate 1, and maintains ohmic contact with the substrate 1. 16 is a gate electrode wiring provided on the gate metal layer 11.

In this way, a large number of N
After the FET elements of the channel are separated one by one, the source electrode wiring 15 is bonded to the stem of the package with a solder material, and then the gate terminal in the package and the gate electrode are connected with a lead wire, and the drain terminal and Connect the drain electrodes with a lead wire, and either cover the lid or seal with a resin mold.

A reverse bias voltage is applied between the gate electrode of the FET element formed as described above and the N-type gallium-arsenide layer 9 according to an input signal to change the conductance of the N-type gallium-arsenide layer 9. urge

As explained in detail above, according to the manufacturing method of the present invention, the step width of the window provided on the V-groove can be made extremely small, so the gate length formed using this step width can also be reduced compared to conventional FETs. It can be done very quickly. In addition, the windows and V-grooves with a reverse stepped cross section can be formed using a conventional photo-etching process, making it easier to manufacture FETs, and the manufactured FETs can operate at higher frequencies than conventional FETs. It has many effects, such as:

[Brief explanation of the drawing]

1 to 5 are process cross-sectional views showing one embodiment of the present invention. In the figure, 1 is an N ⁺ type gallium arsenide substrate, 2 is a semi-insulating gallium arsenide layer, 3 is an N ⁺ type gallium arsenide layer, 4 and 13 are silicon dioxide layers, and 5
is a silicon nitride layer, 6 and 6' are windows, 7 is an undercut portion, _δ1 is a step width, 8 is a V-groove, 9 is an epitaxially grown N-type gallium arsenide layer, 10 is silicon dioxide, 11 1 is a gate electrode layer, 14 is a drain electrode, and 15 is a source electrode.

Claims (1)

[Claims] 1. First and second mask films are sequentially stacked on the surface of a semiconductor substrate, and the first and second mask films are partially removed to form a stepped portion at the boundary between the first and second mask films. Forming a window with a reverse stepped cross section,
After removing the substrate surface in the region of the window to form a V-groove that overhangs the first and second mask films, forming an epitaxial layer on the inner wall of the V-groove;
An insulating layer is partially formed on the epitaxial layer using the first and second mask films as masks, and then, after removing the second mask film, the first mask film is replaced with a mask film. A method of manufacturing a semiconductor device, comprising depositing a gate metal layer partially on the insulating layer and on the epitaxial layer to form a shot key barrier contact between the gate metal layer and the epitaxial layer. .