JPS6129558B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a junction field effect transistor.

Junction field effect transistor (hereinafter referred to as J-
Abbreviated as FET. ), the mutual conductance (gm), which is an important parameter, becomes higher when the resistivity of the channel region is lower. However, in general, when it comes to withstand voltage, the higher the resistivity, the higher the withstand voltage.
It was difficult to manufacture a J-FET of It can be easily inferred that in order to avoid such inconveniences, good results can be obtained by increasing the impurity concentration in the channel region and lowering the impurity concentration in the drain region. For this purpose, the conventional J-FET had a structure as shown in the structural step diagram in FIG. However, the accuracy of the channel thickness 2a is controlled by the accuracy of the epitaxial process, and the thickness tep1 of the epitaxial layer 6
There was a variation of more than a few percent. 2a is a fraction of tep1, and since the first gate region 8 is formed by diffusion or ion implantation from the surface of the epitaxial layer, there is an inconvenience that the variation in 2a is several tens of percent or more. .

The object of the present invention is to create a J-FET with high breakdown voltage and high gm that is less affected by such process variations.
Furthermore, the objective is to provide a J-FET that is more reliable and cheaper than conventional J-FETs.

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below according to embodiments thereof using drawings.

FIG. 2 is a cross-sectional view of a region structure showing an embodiment of the J-FET of the present invention. 1 is an N ⁺ type silicon layer connected to the drain electrode D. 2 is an N ^- type silicon substrate with a drain region, and 3 is a P type buried gate region with at least one slit or hole 4 provided in the center thereof. 5 is an N ⁺ type buried channel region, 6 is an N type epitaxial layer, 6' is a channel region, 7 is a P type gate extraction region, 8 is a P type first gate region, 9 is an N ⁺ type source region, 1
0 is a silicon oxide layer. The P-type buried gate region 3 and the P-type gate extraction region constitute a second gate region. In such a structure, the impurity concentration of the drain region 2 can be lowered, and at the same time, the impurity concentration of the buried channel region 5 and the channel region 6' can be reduced.
The impurity concentration of each can be easily controlled,
It can be set high.

FIG. 3 is a diagram showing the expansion of the space charge layer 11 when a high voltage is applied to the J-FET shown in FIG. 2. As can be seen from this diagram, the drain-gate breakdown voltage is It is determined by the withstand voltage of the PN junction formed by the buried gate region 3. In other words, the first gate region 8, the buried channel region 5, and the channel region 6' hardly contribute to the drain-gate breakdown voltage. Therefore, even if the impurity concentration of the buried channel region 5 and the channel region 6' is increased, the drain-gate breakdown voltage can be increased, and the gate-source breakdown voltage can also be increased by increasing the impurity concentration of the buried channel region 5 and the channel region 6'. Because the resistivity of the layer 6 was lowered, the surface of the N-type epitaxial layer 6, that is, the upper P-type first gate region 8 and the N ⁺
In the structure of the present invention, since the buried channel region 5 is provided, the resistivity of the N-type epitaxial layer 6 can be increased compared to the conventional N-type epitaxial layer 6. The upper P-type first gate region 8- does not depend on the inter-region distance.
The channel region 6' is determined by the distance from the buried channel region 5 to the buried gate region 3, and the gate-source breakdown voltage can be higher than that of the conventional one. Furthermore, gm has conventionally depended on the resistivity of the N-type epitaxial layer 6, which defines the withstand voltage between the gate and source regions, but according to the present invention, by providing the highly doped buried channel region 5, it can be made higher than before. Become. Also, the channel length is that of conventional J-FET.
Similarly, since it can be set relatively freely, it is also possible to increase the output resistance by increasing the channel length.

Additionally, in general, the drain-source current I _DS is generated in the channel region 6' shown in FIG. 1 in the conventional structure.
It is determined using the pinch-off voltage V _p expressed by the impurity concentration NeP1 of the epitaxial layer and the distance 2a between the upper P-type first gate region 8 and the buried gate region 3 as parameters. That is, V _p OC (2a) ² NeP1 ...... I _DP = I _DSS (1-V _G /V _p ) ² ...... V _G ; Gate voltage I _DP ; Drain current in the saturation region I _DSS ; Drain current when gate voltage V _G =0.

However, as shown in the formula, V _p is proportional to the product of the square of the distance 2a and the impurity concentration NeP1 of the epitaxial layer, and in the conventional structure, the epitaxial thickness tep1
When depositing on a silicon substrate, there is a variation of several percent or more in terms of accuracy.
When (2a) is controlled by XJ, the variation in tep1 almost becomes the variation in 2a, which in turn becomes the variation in V _p or _{the variation in I DP (} I _{DSS )} . )
The control of the J-
It was not possible to provide FET. In order to improve this variation in V _p and provide a cheaper J-FET, it is necessary to reduce the variation in V _p , and as a result, the variation in (2a) does not have a direct effect on V _p . Just find a way. The method is to partially form a buried channel region 5 on the buried gate region 3 under the upper P-type second gate region 8, as shown in FIG. 2, so that the following relationship holds true. be.

NeP1<<NC …………… NC; Impurity concentration of buried channel region 5 When the structure shown in _{FIG .} OC(2a) ²・NC), the variation in V _p becomes the variation in the concentration NC in the buried channel region 5, and NC
can be easily controlled. Also, conventional and V
If the _p standards are the same, (2a) in Figure 2 is equivalent to (2a) in Figure 1 because of the relationship NC>>NeP1.
become smaller. In other words, I _DS and gm depend on the concentration of the buried channel region 5.

As described in detail above, it is possible to increase the withstand voltage between the drain and source and between the gate and source in the process, and it is also easier to control in design and manufacturing, resulting in high GM and high reliability. The provision of J-FET will be realized.

Next, the J-FET manufacturing method of the present invention will be explained.

FIGS. 4a to 4c are cross-sectional views showing the process steps for manufacturing the J-FET of the present invention. Thickness 10 ^-3 cm to 10 ^-1 cm
For example, an impurity concentration of about 10 ¹³ to 10 ¹⁵ atoms/cm ³ is applied to one surface of the N ^- type silicon substrate 2.
An N ⁺ type silicon layer of ¹⁰¹⁷ atoms/cm ³ or more is formed by thermal diffusion or the like (FIG. 4a). Next, a P-type diffusion region 3' is partially formed on the other surface of the N ^- type silicon substrate 2. This P-type diffusion region 3' is subjected to thermal effects in subsequent steps and ultimately becomes a P-type buried gate region 3. The P-type buried gate region 3 has one slit or hole 4 having a predetermined width, and the width is such that when a reverse bias is applied between the N ^- type silicon substrate 2 and the P-type buried gate region 3, A voltage that is preferably about twice the target threshold voltage V _T or at least more than V _T (about 0.3 to 5 V)
The width is such that the slit or hole 4 is closed in the space charge region formed at the PN junction. Next, an N ⁺ type buried channel region 5' is formed, with an impurity concentration NO of about 10 ¹⁶ to 10 ¹⁸ atoms/cm ³ , and is partially formed on the P type buried gate region 3' (the fourth Figure b), then the N-type epitaxial layer 6
is deposited, but its impurity concentration NeP1 is 10 ¹⁵
The thickness is preferably about 10 ¹⁷ atoms/cm ³ and the thickness is about 10 ^-4 to 10 ^-3 cm. When forming a relatively thin N-type layer,
In addition to epitaxial growth, methods such as ion implantation are also possible. Next, P
In order to electrically connect the type diffusion region 3' from the surface, the P type lead-out region 7 is formed to a depth equal to or more than the thickness tep1 of the N type epitaxial layer. The P-type gate lead-out region 7 has a closed band shape or a modified shape thereof, and the inner N-type epitaxial layer 6 surrounded by the region 7 is connected to the outer N-type layer 6 or the N ^- type silicon substrate 2. are connected only by the slit or hole 4 formed by the P-type push-in region 3', and everything else is surrounded by the P-N junction (Fig. 4c). . Next, a P-type impurity is buried in the inner N-type region 6 and diffused inside the width of the channel region 5' to form a P-type first gate region 8. The P-type first gate region 8 is one of the gate regions of the J-FET, and must be formed in the shape of a slit or a band surrounding the hole 4 above the P-type buried gate region 3, which is one of the gate regions. Not necessarily. Furthermore, the distance between the P-type first gate region 8 and the P-type buried gate region 3 determines the V _p or voltage V _T of the J-FET, and is 1×10 ^-5 to 3×
Although it must be controlled to about 10 ^-4 cm ² , this becomes easy with this structure. Next, an N ⁺ type impurity concentration is diffused into the inner N type epitaxial layer 6 to form P type regions 7 and 8 in the remaining regions and separated by the P type first gate region 8.
In the area where there is no slit at the bottom or hole 4
An N ⁺ type source region 9 is formed. N ⁺ type source region 9 is for facilitating ohmic contact with a source electrode to be formed later. Next, by forming the silicon oxide layer 10 for surface protection, the first gate electrode G1, the source electrode S, the second gate electrode G2, and the drain electrode D, the J-
The FET wafer process is now complete (Figure 2).

For simplicity, G1, G2, S, and D are used as symbols representing both the respective electrode terminals and metal electrodes.

FIG. 5 is a cross-sectional view of a region structure showing another embodiment of the J-FET of the present invention, in which a first gate region 8' is formed extending over the entire upper surface of the slit or hole.

It goes without saying that the J-FET of the present invention may be used with the first gate electrode G1 and the second gate electrode G2 short-circuited.

Although the N-channel case has been described above with reference to embodiments, it is obvious that the present invention can be applied to the P-channel case or to semiconductors other than silicon.

According to the present invention, a junction field effect transistor can be obtained that has a high breakdown voltage, a high GM, is easy to manufacture in a wafer process, is inexpensive, and has high reliability.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of the basic structure of a conventional junction field effect transistor, FIG. 2 is a sectional view of a region structure showing an embodiment of the present invention, and FIG. Figures 4a to 4c are cross-sectional views showing the method of manufacturing the J-FET of the present invention in order of steps, and Figure 5 is a diagram showing the spread of the space charge layer when a high voltage is applied. FIG. 3 is a step-up diagram of a region structure showing an example. D...Drain electrode, S...Source electrode, G1...First gate electrode, G2...Second gate electrode, 1...N ⁺
silicon layer, 2...N ^- silicon layer, 3', 3...P-type buried gate region, 4...slit or hole, 5...
N ⁺ type buried channel region, 6... N type epitaxial layer, 6'... Channel region, 7... P type drawn out second gate region, 8', 8... P type first gate region, 9... N ⁺ type source region , 10... silicon oxide layer, 11... space charge layer.

Claims (1)

[Claims] 1. A second gate region consisting of a buried gate region of another conductivity type having a slit or hole buried in a semiconductor substrate of one conductivity type, and a gate lead-out region of another conductivity type provided from the periphery of the buried gate region to the surface of the semiconductor substrate. a first conductivity type semiconductor region surrounded by the second gate region, and a first conductivity type semiconductor region surrounded by the second gate region.
A gate region and a high concentration source region of one conductivity type are provided, the one conductivity type semiconductor region outside the second gate region is a drain region, and the buried gate region has a high concentration buried channel region opposite to the first gate region. A junction field effect transistor characterized by being provided with.