JPS6130358B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a storage device used in a flat panel display device such as a liquid crystal television or an electro-chromic display. This paper relates to a storage device that has been improved by combining.

For example, a laminated liquid crystal matrix panel that can generally display images including halftones is known as shown in Denshi Kagaku, published in June 1979, pages 83 to 84.

Such a laminated liquid crystal matrix panel has a display IC array formed with a memory device with one transistor and one capacitance per pixel as shown in FIG. In order to use one electrode of each of the above capacitances as a reflective electrode of a liquid crystal device, a seal (not shown), a liquid crystal layer (not shown), a transparent electrode (not shown), and a front glass plate (not shown) are installed. They were formed in this order. According to such a stacked liquid crystal matrix panel, the video signal output from the data bus drive circuit 4 is supplied to the data bus group B of the display IC cell 1, and the address bus drive circuit 5 is supplied to the address bus group A.
If you supply the scanning signal output from the MOS transistor, the scanning signal will switch on the MOS transistor.
As a result, the video signal voltage is stored in the capacitor 3, so by having the charge voltage stored in each capacitor 3, blinking pixels according to the charge voltage can be projected on the panel, and such pixels can be arranged in a matrix. For example, if 240 x 240 pixels are provided, images containing halftones can be reproduced in those panel images.

However, in the case of such a display device, the number of pixels must be set to 240 x 240, for example, in consideration of the resolution.
(57600), the screen dimensions for these devices are 36 mm x 48 mm (equivalent to 2.4 inches), and when forming the above display device, a storage device equivalent to at least 2.4 inches is required. Therefore, in order to form a memory device equivalent to 2.4 inches, only one memory chip can be manufactured even with a 75 mm diameter wafer, and it is necessary to form these memory cells. In this case, unless a yield of nearly 100% is achieved for one wafer, the price of the storage device becomes very high.

Generally, the memory device shown in FIG. 1 has one MOS transistor 2 and one capacitor 3 formed in series between a data bus B and a reference potential point (earth) on a wafer (substrate), and a transistor A data bus drive circuit 4 and an address bus drive circuit constitute each memory cell 1 by connecting the gates of 2 to the address bus A, and also generate a video signal (data) and a scanning signal (address signal) on the same wafer. However, if a failure occurs in a part of either the data bus drive circuit 4 or the address bus drive circuit 5, this problem occurs even though each memory cell 1 is normal. The storage device becomes defective.

That is, if a mask defect occurs for some reason or dust gets mixed in during the manufacturing process, a failure will occur in the data bus drive circuit 4 and the address bus drive circuit 5. For example, if the number of pixels of the liquid crystal is arranged in a 320 x 240 array with a pitch of 150 microns each, the yield in the data bus drive circuit 4 and address bus drive circuit 5 can be calculated by referring to the formula for deriving the yield of LSI. can.

That is, the number of elements of the data bus drive circuit 4 corresponding to the above array arrangement scale is 8000 elements, the occupied area is 29.6 mm ² , and the element density is 270 elements/mm ² , and the yield Y _A of this circuit 4 is approximately 0.7, or 70 It will be about %. On the other hand, the number of elements in the address bus drive circuit 5 is
5760 elements, the occupied area is 28.8 cm ² , the element density is 200 elements/mm ² , and the yield Y _B of this circuit 5 is also about 0.7, that is, about 70%. Therefore, in the conventional device, the yield Y for both the data bus drive circuit 4 and the address bus drive circuit 5 being good products is
is, Y = Y _A × Y _B = 0.7 × 0.7 ≒ 0.5 (50%) Therefore, as can be understood from the above results, the yield of the memory device with the conventional configuration is low even if all memory cells are good. is 50% and 2
One of the pieces is defective. As a result, product prices have become extremely high.

The present invention relates to a storage device devised in view of the above-mentioned drawbacks, and its purpose is to provide a storage device that can prevent a decrease in yield caused by mask defects or dust mixed in during the manufacturing process. This is what we provide.

Another object of the present invention is to provide a memory device that aims to reduce manufacturing costs by preventing a decrease in yield.

According to the present invention, the feature is that equal data for a data bus group and an address bus group,
A pair of data bus drive circuits and an address bus drive circuit are formed that generate address signals in synchronization with each other, and each of the pair of data bus drive circuits and address bus drive circuits has common parts and non-conforming parts due to circuit characteristics. Divide the common parts into multiple block parts, and divide the non-common parts into multiple block parts.
Of the opposing block parts in a pair of data bus drive circuits and address bus drive circuits, the block part that is good is set to the operating state, and the other block part is set to the disabled state. Details thereof will be apparent from reference to the circuit diagrams of one embodiment according to the present invention shown in FIGS. 2-4.

FIG. 2 shows an embodiment of the present invention, and parts corresponding to those of the conventional device shown in FIG. 1 are given the same reference numerals, and the explanation thereof will be omitted. In the storage device shown in FIG. 2, a pair of data bus drive circuits 4 ₁ , 4 are provided at both ends of the data bus groups B ₁ to B _o , each generating equal video signals in synchronization with each other.
₂ are formed, and the video signal generated in one data bus drive circuit ₄₁ is generated from the lower end side of the data bus group _B1 to _Bo in the other data bus drive circuit _{42 in} FIG. The video signals are supplied from the upper ends of the data bus groups B ₁ -B _o , respectively. Similarly, address bus group A ₁
A pair of address bus drive circuits 5 ₁ and 5 ₂ that generate equal scanning signals in synchronization with each other are formed at both ends of ~A _n , respectively, and the scanning signal generated by one address bus drive circuit 5 ₁ is teeth,
In FIG. 2, the scanning signals generated in the other address bus drive circuit 52 are supplied from the right end side of the address bus groups A ₁ -A _n , and the scanning signals generated in the other address bus drive circuit ₅₂ are supplied from the left end side of the address bus groups A ₁ -A _n , respectively. It's becoming like that.

Further, the pair of data bus drive circuits 4 ₁ , 4 ₂
Each of them is roughly divided into a common part S and a non-common part P in terms of circuit characteristics. Among these, the common section S is a circuit section common to each data bus B, and is composed of, for example, a shift register. On the other hand, the non-common part P is connected to each data bus B.
It is a set of circuit parts formed in one-to-one correspondence with each other, and is composed of a plurality of data latch circuits, output buffer circuits, etc. to which output signals from the common part S are supplied. This non-common portion P is divided into blocks such as block portions P ₁ , . . . , or an invalid state, that is, a state in which the output state is high impedance. Similarly, each of the pair of address bus drive circuits 5 ₁ and 5 ₂ also has a common section S.
and a non-common part P. Among these, the non-common part P is a set of circuit parts formed in one-to-one correspondence with each address bus A, and is divided into blocks like block parts P ₁ , . . . P 〓 for every two address buses. There is. And each of these block parts P ₁ ,...
...P〓 can also be independently set to an operable state or an invalid state.

In the storage device configured as described above, immediately after manufacturing, a pair of data bus drive circuits 4 ₁ , 4 ₂
All the block parts of one of the circuits 4 _{1
P 1 , . _}
〓 is set to the operable state. Therefore, after manufacturing, the quality of all _the block parts P _{1 ,} . . . , P ₁ , . do. As a result of this determination, if there is a defective block, it is set to an invalid state and the corresponding block section of the other data bus drive circuit ₄₂ or address bus drive circuit ₅₂ is set to an operable state. As a result, each memory cell 1
is driven by _a good _{one of} the pair of block parts _{P 1 ,} . . . Furthermore, a pair of address bus drive circuits 5 ₁ , 5 at both ends of the address bus groups A ₁ to A _n
The block portions P _{1 ,} . . .

In addition, if the common part S of the data bus drive circuit 4 ₁ or the address bus drive circuit 5 ₁ is defective after manufacturing, the data bus drive circuit 4 of the other data bus drive circuit 4 1 is defective.
₂ , each memory cell 1 is driven by using the address bus drive circuit ₅₂ .

Let us now calculate the yield in the apparatus of the present invention. Note that the conditions are that the number of memory cells is 320 x 240, and they are arranged at a pitch of 150 microns, as in the conventional case.

The yield Y _B of the data bus drive circuit 4 ₁ or 4 ₂ is 0.7 as before, the yield Y _BS of the common part S is 0.95, and the yield Y _BP of the non-common part P is 0.75.
become. Also, the yield Y _A of the address bus drive circuit 5 ₁ or 5 ₂ is 0.7, the yield Y _AS of the common part S is 0.95, and the yield Y _AP of the non-common part P.
becomes 0.75.

Therefore, the yield Y _B ^* of the data bus drive circuits 4 ₁ , 4 ₂ and the yield Y _A ^* of the address bus drive circuits 5 ₁ , 5 ₂ of the storage device according to the present invention are as follows. However, N is the number of block units in each of the data bus drive circuits 4 ₁ and 4 ₂ (N=n/2), and M is the number of block units in each of the address bus drive circuits 5 ₁ and 5 ₂ (M=m/2). ).

Here, when N=M=4, Y _B ^* and Y _A ^* are each 0.956. Therefore, the yield Y ^* of all bus drive circuits is Y ^* =Y _B ^* ×Y _A ^* ≈0.914 (91.4%).

In this way, according to the present invention, the conventional yield is 50%
%, it reached 91.4%, and the difference is obvious at a glance. Furthermore, if the yield is improved, manufacturing costs can be reduced.

FIG. 3 shows a part of each block portion of each data bus drive circuit 4 ₁ , 4 ₂ and address bus drive circuit 5 ₁ , 5 ₂ . As shown in the figure, the terminal portion includes two tri-state buffer circuits 10,
11, and when the control signal C is set to a high level, the output state becomes a high impedance state, and the block section is set to an invalid state. On the other hand, when the control signal C is set to a low level, each of the input signals X ₁ and X ₂ is output as is, and the block section is set to an operable state. In addition,
FIG. 4 shows the tri-state buffer circuit 10,
FIG. 11 is a specific circuit configuration diagram of No. 11, which is composed of four transistors 21 to 24 and one inverter 25.

Furthermore, the present invention is not limited to the above embodiments; for example, in the above embodiments, in each pair of data bus drive circuits 4 ₁ , 4 ₂ and address bus drive circuits 5 ₁ , 5 ₂ , a corresponding pair of blocks We have described the case where one of the block sections that is in good condition is set to the operable state, but when the data bus or address bus is disconnected, it is also possible to set both the corresponding pair of block sections to the operable state. Accordingly, a storage device that is originally defective can be made into a non-defective product. In addition, each non-common part P
In the above, a case has been described in which blocks are created for every two data buses and address buses, but blocks may be created for every two or more buses.

As described above, according to the present invention, a storage device is provided that can prevent a decrease in yield caused by mask defects or dust mixed in during the manufacturing process, and can reduce manufacturing costs. can.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram of a conventional storage device, FIG. 2 is a circuit configuration diagram of an embodiment of the present invention, FIG. 3 is a circuit diagram showing a part of it, and FIG. 4 is a specific diagram of FIG. 3. It is. DESCRIPTION OF SYMBOLS 1...Memory cell, 2...MOS transistor, 3...Capacitor, ₄₁ , ₄₂ ...Data bus drive circuit, ₅₁ , ₅₂ ...Address bus drive circuit, S...Common part, P... Uncommon parts.

Claims (1)

[Claims] 1 a plurality of memory cells and an address bus group for transmitting address signals to each of the plurality of memory cells;
A data bus group for transmitting data to each of the plurality of memory cells, and a pair of equal address signals are generated in synchronization with each other, and each of the pair of address signals is transmitted to one end side and the other end side of the address bus group. A pair of address bus drive circuits output data to each address bus, and the non-common parts are divided into multiple blocks, and each block can be set to an operable state or a disabled state independently, and a pair of equal data are generated in synchronization with each other. At the same time, each pair of data is output to one end and the other end of the data bus group, and the non-common parts are divided into a plurality of blocks, and each block is independently set to an operable state or an invalid state. 1. A storage device comprising a pair of data bus drive circuits.