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JPS6130425B2 - - Google Patents
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JPS6130425B2 - - Google Patents

Info

Publication number
JPS6130425B2
JPS6130425B2 JP55104823A JP10482380A JPS6130425B2 JP S6130425 B2 JPS6130425 B2 JP S6130425B2 JP 55104823 A JP55104823 A JP 55104823A JP 10482380 A JP10482380 A JP 10482380A JP S6130425 B2 JPS6130425 B2 JP S6130425B2
Authority
JP
Japan
Prior art keywords
external connection
semiconductor element
connection line
circuit board
printed circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP55104823A
Other languages
Japanese (ja)
Other versions
JPS5730396A (en
Inventor
Toshio Kumai
Shigeru Oomori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP10482380A priority Critical patent/JPS5730396A/en
Publication of JPS5730396A publication Critical patent/JPS5730396A/en
Publication of JPS6130425B2 publication Critical patent/JPS6130425B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Description

【発明の詳細な説明】 本発明はセラミツク基板上に実装した半導体素
子をプリント回路基板に接続のため急加熱したと
きも熱ストレスによる影響を受けることの少ない
半導体素子の外部接続線に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an external connection line for a semiconductor element that is less affected by thermal stress even when the semiconductor element mounted on a ceramic substrate is rapidly heated for connection to a printed circuit board.

半導体素子のプリント回路と接続するため、基
板に実装するとき通常はセラミツク基板を使用し
ている。それは基板の表面平滑性、耐熱性、熱放
散性、電気絶縁性、寸法安定性などをすべて良好
にするためであつて、例えばアルミナのセラミツ
ク板としている。第1図に示す従来構成の基板に
おいて1は半導体素子2はセラミツク基板を示し
ている。一方このようなセラミツク基板の装着さ
れるプリント回路基板は成形加工性、価格に有利
なガラス繊維強化のプラスチツク材とすることが
多く、表面に銅箔を接着し、またセラミツク基板
用のスルーホールを設けている。第1図において
3はプリント回路基板、4は銅箔、5はスルーホ
ールを示す。セラミツク基板2上の半導体素子1
と外部接続線6とは薄膜または厚膜導体により接
着される。外部接続線6と半導体素子1とを接続
するときは幅1〜2mmの金めつきした金属製台を
置き、はんだ片を挾んで外部接続線6を近接さ
せ、加熱炉の中を通して半田を溶かし接続した
り、半田ごてにより半田を溶かして接続されてい
る。なお外部接続線6の形状は側面から見てL形
の例を示してあるが、コ字形セラミツク基板2を
挾み込む形状とすることもある。このような半導
体素子1の実装基板2をプリント回路基板3に装
着するとき外部接続線6をプリント回路基板3の
スルーホール5に貫通し、実装基板の反対側を溶
融半田槽に浸漬し、プリント回路基板3上の銅箔
4と外部接続線6を固着させる。第1図7は半田
固着部を示している。半田槽浸漬のときプリント
回路基板3は熱膨脹係数が比較的大であるため、
半田槽からの熱は急激に基板3に伝導し、図面の
左右側を上方に曲げる力が加わる。外部接続線6
は半田固着部7のため固着されているからプリン
ト回路基板3に生じた熱ストレスは外部接続線6
を介しセラミツク基板2に伝達され、セラミツク
基板2と半導体素子1との間の剥離、しわ、割れ
を生じさせ、半導体素子の電気的特性に悪影響を
及ぼすようになる。
Ceramic substrates are usually used when mounting semiconductor devices on substrates in order to connect them to printed circuits. This is to improve the surface smoothness, heat resistance, heat dissipation, electrical insulation, and dimensional stability of the substrate, and is made of, for example, an alumina ceramic plate. In the conventional substrate shown in FIG. 1, reference numeral 1 indicates a semiconductor element 2 which is a ceramic substrate. On the other hand, the printed circuit board on which such a ceramic board is mounted is often made of glass fiber-reinforced plastic material, which is advantageous in moldability and cost. Copper foil is bonded to the surface, and through holes for the ceramic board are made. It is set up. In FIG. 1, 3 is a printed circuit board, 4 is a copper foil, and 5 is a through hole. Semiconductor element 1 on ceramic substrate 2
and the external connection line 6 are bonded by a thin film or thick film conductor. When connecting the external connecting wire 6 and the semiconductor element 1, place a gold-plated metal stand with a width of 1 to 2 mm, sandwich the solder piece, bring the external connecting wire 6 close together, and pass it through a heating furnace to melt the solder. They are connected by soldering or by melting the solder with a soldering iron. Although the shape of the external connection line 6 is shown as an L-shape when viewed from the side, it may also be shaped to sandwich the U-shaped ceramic substrate 2. When mounting the mounting board 2 of such a semiconductor element 1 on the printed circuit board 3, the external connection wire 6 is passed through the through hole 5 of the printed circuit board 3, and the other side of the mounting board is immersed in a molten solder bath. The copper foil 4 on the circuit board 3 and the external connection wire 6 are fixed. FIG. 17 shows the solder fixing portion. Since the printed circuit board 3 has a relatively large coefficient of thermal expansion when immersed in the solder bath,
Heat from the solder bath is rapidly conducted to the board 3, and a force is applied that bends the left and right sides of the drawing upward. External connection line 6
is fixed due to the solder joint 7, so the thermal stress generated on the printed circuit board 3 is transferred to the external connection wire 6.
This is transmitted to the ceramic substrate 2 through the ceramic substrate 2, causing peeling, wrinkles, and cracks between the ceramic substrate 2 and the semiconductor element 1, and adversely affecting the electrical characteristics of the semiconductor element.

本発明の目的は前述の欠点を改善し、プリント
回路基板に急に加えられた熱によるストレスのた
め半導体素子の受ける影響を少なくした半導体素
子の外部接続線を提供することにある。
SUMMARY OF THE INVENTION It is an object of the present invention to provide an external connection line for a semiconductor device, which overcomes the above-mentioned drawbacks and reduces the effects on the semiconductor device due to stress caused by heat suddenly applied to a printed circuit board.

以下図面に示す本発明の実施例について説明す
る。第2図は第1図と対応して示す本発明の第1
実施例であつて、第1図と同一符号は同様のもの
を示す。8は本発明により設けた外部接続線6の
たわみ部であつて、熱ストレスによるそりの影響
を吸収する部分である。たわみ部8を設けたこと
により半田槽に浸漬したとき発生した急激な熱ス
トレスを吸収できるから、プリント回路基板3の
そりが発生してもセラミツク基板2と半導体素子
1に影響を与えない。なおセラミツク基板2の側
方で外部接続線6と接している所をP1とし(接
着剤等により互に固着している必要はない)、ス
ルーホール5の一端で半田固着部7となつている
所を点P2としたとき、たわみ部8を設ける位置
は点P1と点P2の中間で、たわみ部の方向セラ
ミツク基板2の下側となることが望ましい。そし
てたわみ部8を除いた外部接続線6はP1,P2
を一直線状に結ぶ形としておくことが好適であ
る。それはスルーホール5の間隔がプリント回路
基板製造時に標準仕様化されているから、それに
適合させたセラミツク基板2と外部接続線6の位
置・形状のとき自動装着することも容易であり、
且つ前述の熱ストレスによる影響を受けなくなる
からである。
Embodiments of the present invention shown in the drawings will be described below. FIG. 2 shows the first embodiment of the present invention corresponding to FIG. 1.
In the embodiment, the same reference numerals as in FIG. 1 indicate the same things. 8 is a flexible portion of the external connection line 6 provided according to the present invention, and is a portion that absorbs the influence of warping due to thermal stress. Since the provision of the flexible portion 8 can absorb the sudden thermal stress generated when immersed in the solder bath, even if the printed circuit board 3 warps, it does not affect the ceramic substrate 2 and the semiconductor element 1. The side of the ceramic substrate 2 where it touches the external connection line 6 is designated P1 (there is no need for them to be fixed to each other with adhesive or the like), and one end of the through-hole 5 is the solder fixed part 7. Assuming that the position is a point P2, the position where the bending part 8 is provided is preferably between the points P1 and P2, and the direction of the bending part is on the lower side of the ceramic substrate 2. The external connection wires 6 excluding the bending portion 8 are P1 and P2.
It is preferable to connect them in a straight line. This is because the spacing between the through holes 5 is standardized at the time of manufacturing the printed circuit board, so it is easy to automatically mount the ceramic board 2 and the external connection wire 6 in a position and shape that match that.
This is also because it is not affected by the heat stress mentioned above.

またたわみ部8を設けた外部接続線を使用した
とき、セラミツク基板2の上部に従来と同様な配
置の寸法で他のプリント回路基板を設けると、基
板同志の軽い接触のときなどにたわみ部8がプリ
ント回路基板3の銅箔4と接触することがある。
そのため第2図に破線で9と示すようにプラスチ
ツク等の絶縁物を介在させる。またはさらにセラ
ミツク基板2と半導体素子1を保護するため、第
3図に1点鎖線で10と示すように絶縁キヤツプ
を設けることがあつて、該キヤツプの高さ(セラ
ミツク基板の側方で測つた高さ)を十分高くする
ことも良い。
Furthermore, when using an external connection line provided with a flexible portion 8, if another printed circuit board is provided on top of the ceramic substrate 2 with the same dimensions as the conventional one, the flexible portion 8 may come into contact with the copper foil 4 of the printed circuit board 3.
Therefore, an insulating material such as plastic is interposed as shown by the broken line 9 in FIG. Alternatively, in order to further protect the ceramic substrate 2 and the semiconductor element 1, an insulating cap may be provided as indicated by the dashed line 10 in FIG. It is also good to make the height (height) sufficiently high.

次に本発明において基板そりに基因する熱スト
レスの吸収部としてはたわみ部を設けることの外
にその個所の導電性ゴムを挿入すること等があ
る。
Next, in the present invention, as a part for absorbing thermal stress caused by substrate warpage, in addition to providing a flexible part, conductive rubber may be inserted in that part.

このようにして本発明によると極めて簡易な構
成によりセラミツク基板の受ける熱ストレスの影
響を除去することができ、半導体素子使用の機器
の製造時、不良品発生の確率を大きく低下させる
効果がある。
In this way, according to the present invention, the effects of thermal stress on a ceramic substrate can be eliminated with an extremely simple configuration, and the probability of producing defective products can be greatly reduced when manufacturing equipment using semiconductor elements.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の半導体素子実装基板をプリント
回路基板に装着する構成を示す図、第2図は本発
明の第1実施例を示す図、第3図は第2図の変形
図である。 1……半導体素子、2……セラミツク基板、3
……プリント回路基板、4……銅箔、5……スル
ーホール、6……外部接続線、7……半田固着
部、8……たわみ部。
FIG. 1 is a diagram showing a configuration for mounting a conventional semiconductor element mounting board on a printed circuit board, FIG. 2 is a diagram showing a first embodiment of the present invention, and FIG. 3 is a modification of FIG. 2. 1... Semiconductor element, 2... Ceramic substrate, 3
...Printed circuit board, 4...Copper foil, 5...Through hole, 6...External connection wire, 7...Solder fixed part, 8...Bending part.

Claims (1)

【特許請求の範囲】 1 セラミツク基板2に実装された半導体素子1
に対し外部接続線6を接合し、該外部接続線6は
プリント回路基板3に設けた貫通孔5を通過して
該基板上の回路と接続されている半導体素子の外
部接続線において、 該外部接続線6には他方の外部接続線に近い内
側方向にたわんだたわみ部8を設け、 且つ外部接続線の該たわみ部8とプリント回路
基板3との間に電気的絶縁物9を設けたことを特
徴とする半導体素子の外部接続線。 2 サラミツク基板2に実装された半導体素子1
を対し外部接続線6を接合し、該外部接続線6は
プリント回路基板3に設けた貫通孔5を通過して
該基板上の回路と接続されている半導体素子の外
部接続線において、 該外部接続線6には他方の外部接続線に近い内
側方向にたわんだたわみ部8を設け、 且つセラミツク基板2と外部接続線たわみ部8
とを含んだ高さよりも高い形状で、半導体素子1
も全体的に被冠するキヤツプ10を設けることを
特徴とする半導体素子の外部接続線。
[Claims] 1. Semiconductor element 1 mounted on ceramic substrate 2
An external connection line 6 is connected to the external connection line of the semiconductor element, which passes through a through hole 5 provided in the printed circuit board 3 and is connected to a circuit on the board. The connecting wire 6 is provided with a bent portion 8 that is bent inwardly near the other external connecting wire, and an electrical insulator 9 is provided between the bent portion 8 of the external connecting wire and the printed circuit board 3. An external connection line for semiconductor devices characterized by: 2 Semiconductor element 1 mounted on Saramic substrate 2
An external connection line 6 is connected to the external connection line of the semiconductor element, which passes through a through hole 5 provided in the printed circuit board 3 and is connected to a circuit on the board. The connection wire 6 is provided with a bending portion 8 that bends inward toward the other external connection wire, and the ceramic substrate 2 and the external connection wire bending portion 8 are provided.
The semiconductor element 1 has a shape that is higher than the height including the
1. An external connection line for a semiconductor device, characterized in that it is provided with a cap 10 that covers the whole of the semiconductor device.
JP10482380A 1980-07-30 1980-07-30 External connecting wire for semiconductor element Granted JPS5730396A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10482380A JPS5730396A (en) 1980-07-30 1980-07-30 External connecting wire for semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10482380A JPS5730396A (en) 1980-07-30 1980-07-30 External connecting wire for semiconductor element

Publications (2)

Publication Number Publication Date
JPS5730396A JPS5730396A (en) 1982-02-18
JPS6130425B2 true JPS6130425B2 (en) 1986-07-14

Family

ID=14391113

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10482380A Granted JPS5730396A (en) 1980-07-30 1980-07-30 External connecting wire for semiconductor element

Country Status (1)

Country Link
JP (1) JPS5730396A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1089266A (en) * 1996-09-17 1998-04-07 Toyoda Mach Works Ltd Vane pump

Also Published As

Publication number Publication date
JPS5730396A (en) 1982-02-18

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