JPS6130436B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor diode element, particularly a high voltage diode element, formed in a semiconductor thin film on a dielectric insulating substrate.

In recent years, silicon on sapphire (Silicon on Sapphire =
High-quality semiconductor substrates made by epitaxially growing silicon single crystal films on dielectric insulating substrates such as SOS (SOS) substrates have become available at low cost, and research and development of semiconductor devices using such substrates is flourishing. It is carried out in

For example, silicon-on-sapphire (hereinafter referred to as
When configuring a semiconductor integrated circuit device on a substrate (abbreviated as an SOS substrate), a PN junction diode is an important component. In particular, this type of semiconductor device with complete isolation of each element is essentially suitable for high-voltage operation circuits. It is desired to obtain a diode element. In this case, an n+pp+ type diode is formed corresponding to the conductivity type of the substrate used.

In addition, as mentioned above, the diodes formed on the SOS substrate are completely isolated from each other, so by connecting multiple diodes formed on the same substrate in series, it is easy to A diode with high breakdown voltage can be obtained.

By the way, in general, the reverse breakdown voltage of a PN junction diode depends on the depletion layer width that expands when voltage is applied, in other words, it depends on the impurity concentration distribution in the p and n regions. It was necessary to use a low impurity concentration semiconductor film that can be easily expanded. That is, in FIG. 1, when a p+ region 13 and an n+ region 14 are formed on an n-type semiconductor thin film 12 on a dielectric insulating substrate 11 to form a high voltage diode, the n-type semiconductor film 12 is The impurity concentration Nsub is
It was necessary to select a lower value depending on the desired withstand voltage. For example, even when considering an ideal silicon planar PN junction, in order to obtain a reverse breakdown voltage of 750V or more,
Assuming that the dielectric breakdown voltage of silicon is 3×10 ⁵ ×V/cm, a low impurity concentration silicon epitaxial film region 12 with a length of 25 μm or more is required, and the impurity concentration in that region is 7×10 ¹⁴ cm. It needed to be around ^-3 or less. In actual devices, it is necessary to take local electric field concentration into consideration and to select a value with a margin. In addition, especially in SOS substrates, the lifetime of the minority carrier is generally 0.1 due to insufficient crystallinity.
~1nsec compared to that of bulk silicon,
It is known to be very small. Therefore, SOS
When the diode on the substrate is forward biased, conductivity modulation due to the injection of electrons and holes from both high impurity concentration electrode regions 13 and 14 cannot be expected, and in this case, the low impurity concentration silicon epitaxial film region 12 acts as a series resistance where the forward current is large.

That is, in order to increase the reverse breakdown voltage of the diode, the spacing between the high impurity concentration electrode regions 13 and 14 is widened, and the silicon epitaxial film region 12
If the impurity concentration of the diode was designed to be lower, the forward characteristics of the diode would be significantly degraded.

For example, in the example above, the length is 25μm and the thickness is 2μm.
Considering an n-type silicon epitaxial film region 12 of 7×10 ¹⁴ cm ⁻³ in m, this region constitutes a series resistance of about 25 KΩ per 100 μm width.

An object of the present invention is to alleviate the dependence of the reverse breakdown voltage on the impurity concentration of the semiconductor thin film region 12, which is the drawback of the conventional art, and to provide a large degree of freedom in design.
The object of the present invention is to provide a semiconductor diode element with low series resistance when forward biased.

According to the present invention, each of the semiconductor layers provided on the dielectric insulating substrate has the same first layer as the semiconductor layer.
and a high impurity concentration region having a second conductivity different from that of the semiconductor layer, and an insulating protective film that breaks through the semiconductor layer. In the surface portion of the semiconductor layer under the insulating protective film between the first and second conductive high impurity concentration electrode regions,
A low impurity concentration region having a second conductivity different from the conductivity of the semiconductor layer is configured in contact with an end of a high impurity concentration electrode region having a second conductivity, and the second conductivity When the reverse voltage increases, the impurity concentration and the distribution in the depth direction of the low concentration region with Due to the depletion layer generated, the entire region in the direction perpendicular to the direction of the two high impurity concentration electrode regions becomes a depletion layer, and the first conductivity is transferred from the high impurity concentration electrode region having the second conductivity. A semiconductor diode element is obtained, in which the depletion layer region extending toward the high impurity concentration electrode is selected to be maximum in the same direction.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In the following, embodiments of a semiconductor diode element using an SOS substrate as a semiconductor thin film material on a dielectric insulating substrate will be described in detail with reference to the drawings.

Embodiment 1 FIG. 2a is a diagram for explaining an embodiment of the present invention. First, as a semiconductor thin film, the film thickness is 1~
An n-type silicon epitaxial film 22 with a thickness of 1.5 μm and impurity concentrations of approximately 2×10 ¹⁵ cm ^-3 and approximately 7×10 ¹⁵ cm ^-3 is formed on the sapphire substrate 21, and the n-type silicon epitaxial film 22 is formed on the sapphire substrate 21.
type silicon epitaxial film 22, a high impurity concentration p+ electrode region 23, a high impurity concentration n+ electrode region 24, and a silicon thermal oxide film 2 as an insulating protective film.
5 and metal Al wiring 26 were provided. These steps are similar to standard steps for manufacturing SOSMOS transistors. The p-type low impurity concentration region 27 extending from the p+ electrode 23 is formed by using a photoresist as a mask for ion implantation and implanting boron ions into the same area at an acceleration voltage of 40 KeV through the silicon thermal oxide film 25 with a thickness of about 1300 Å. Formed. Afterwards, the implanted ions are activated and the ion implantation is annealed at 500°C for approximately 30 minutes in a nitrogen atmosphere.
Heat treatment was carried out for 30 minutes. Figure 4 shows a silicon epitaxial film with an impurity concentration of approximately 2×10 ¹⁵ cm when the length of the p-type low impurity concentration region 27 by ion implantation is 30 μm and the interfusion between the high concentration electrode regions is 40 μm.
This is an example showing the relationship between reverse breakdown voltage and ion implantation amount in a ^-3 diode. The reverse breakdown voltage of a diode without ion implantation is approximately 150V, but a diode with boron ion implantation of approximately 3×10 ¹² cm ^-2 exhibits a maximum reverse breakdown voltage of 800V.
For a higher ion implantation amount, the reverse breakdown voltage decreased again.

A diode with the same structure formed on a silicon epitaxial film with an impurity concentration of about 7 x 10 ¹⁵ cm ^-3 can also achieve a maximum reverse breakdown voltage of 750 to 800 V by implanting boron ions at about 6 x 10 ¹² cm ^-2 . The reverse breakdown voltage decreased at ion implantation doses before and after that. Further, the reverse breakdown voltage of each diode varied in proportion to the length of the p-type low impurity concentration region 27, and the longer the same length, the greater the reverse breakdown voltage. On the other hand, for a certain length of p-type low impurity concentration region 27, the silicon epitaxial film impurity concentration is approximately 2×10 ¹⁵
In a cm ^-3 diode, the ion implantation amount is approximately 3×
10 ¹² cm ^-2 , and in a diode with a silicon epitaxial film impurity concentration of 7 x 10 ¹⁵ cm ^-3 , when the ion implantation amount is about 6 x 10 ¹² cm ^-2 ,
The highest reverse breakdown voltage was obtained for each.

Example 2 In FIG. 2b, the thickness of the semiconductor thin film is 4 to 4.
A p-type silicon epitaxial film 22' with a thickness of 1.5 μm and an impurity concentration of approximately 2×10 ¹⁶ cm ^-3 is placed on a sapphire substrate 2.
A high impurity concentration n+ electrode region 23', a high concentration p+ electrode region 24', and an insulating protective film are formed on the p-type silicon epitaxial film 22' by the same method as in Example 1. A silicon thermal oxide film 25' and an Al wiring 26' were provided. The n-type low impurity concentration region 27' extending from the n+ electrode 23' is
As in Example 1, phosphorus was ion-implanted into the same area at an acceleration voltage of 100 KeV using a photoresist as a mask, and then ion-implanted in nitrogen.
Heat treatment was performed at 500°C for 30 minutes.

Also in the n+pp+ type diode having a length of 30 μn type low impurity concentration region 27' in this example, by implanting approximately 8×10 ¹² cm ^-2 of phosphorus ions,
A device with a reverse breakdown voltage of 700V or more was obtained.

Similarly to the p+nn+ type diode of Example 1, the reverse breakdown voltage of the n+pp+ type diode of this embodiment also has an optimum ion implantation amount and is proportional to the length of the n-type low impurity concentration region 27'. showed a dependence.

Example 3 FIG. 3 shows that a low impurity concentration region 37 is a high concentration p
3 shows an example of a semiconductor diode having a structure formed astride between + and high concentration n+ electrode regions 33 and 34.

In this example, an n-type epitaxial film 32 having a thickness of 1 to 1.5 μm and an impurity concentration of about 2×10 ¹⁵ cm ^-3 is formed on a saphire substrate 31 as a semiconductor thin film, and first the n-type silicon epitaxial film 32 is formed on a sapphire substrate 31. Yaru membrane 3
2, a high concentration p+ electrode region 33, a high concentration n+ electrode region 34, and a silicon thermal oxide film 35 as an insulating protective film were formed.

Next, the silicon thermal oxide film 35 with a thickness of about 1300 Å
Boron ions were implanted into the entire silicon epitaxial film at a dose of approximately 1×10 ¹² cm ^-2 at an acceleration voltage of 40 KeV, and heat treatment was performed at 950° C. for approximately 30 minutes in a nitrogen atmosphere. A p-type low impurity concentration region 27 was formed, and finally, an Al wiring 36 was formed.

In the semiconductor diode of this example in which the spacing between the high impurity concentration p+ and n+ electrodes 33 and 34 was 30 μm, a reverse breakdown voltage of about 600V was obtained.

In this example, a mask process for ion implantation is not required, and the manufacturing process is simpler than the elements of Example 1 and Example 2. Since it is in contact with the high concentration electrode region 34 having the first conductivity, it is necessary to prevent local electric field concentration between the two.
For example, it is necessary to control the impurity concentration distribution, such as by lowering the maximum value of the impurity concentration in the resistive impurity concentration region 37. Also, for the same reason, the low impurity concentration region 3
7 and the total amount of effective impurity ions in the silicon epitaxial film at the bottom of the same region in Examples 1 and 2.
It is necessary to control more accurately than in the case of

As is clear from the above embodiments, in the semiconductor diode device according to the present invention, the reverse breakdown voltage is higher than that of the silicon epitaxial film provided adjacent to the high concentration electrode region, which has a different conductivity than the silicon epitaxial film. Due to the effect of the low impurity concentration region having a conductivity different from that of the silicon epitaxial film that is the base of the device, the present invention allows for high reverse breakdown voltage while maintaining high reverse breakdown voltage. It becomes possible to select the impurity concentration of the silicon epitaxial film serving as the base of the diode element over a wide range.

The basic principle of the present invention is that between the low impurity concentration region and the silicon epitaxial film below the region,
By considering the effect of the depletion layer expanding in the epitaxial film thickness direction, the following explanation can be given using FIG. 2a of Example 1 as an example. That is, the effective total amount of impurity ions in the low impurity concentration region 27 considering the equivalent charge density at the interface with the insulating protective film and the interface with the dielectric insulating substrate, and the opposite polarity in the silicon epitaxial film 22 below the region. By selecting the total amount of effective impurity ions to be equal to each other, when a reverse voltage is applied to the semiconductor diode element according to the present invention and a depletion layer expands between the pn junctions, the low impurity concentration region 27
Almost all of the electric force edges emitted from impurity ions can be terminated by impurity ions of opposite polarity in the silicon epitaxial film below the same region. In this case, under a constant voltage, the low impurity concentration region 2
7 and the entire area including the silicon epitaxial film at the bottom of the same region simultaneously becomes a depletion layer due to the depletion layer expanding in the epitaxial film thickness direction. Here, the total silicon epitaxial film thickness is determined by considering the impurity concentration and its distribution in the film thickness direction in the diode element so that the electric field strength in the depletion layer that spreads in the epitaxial film thickness direction does not exceed the dielectric breakdown field strength of silicon. Of course, you should choose accordingly. Due to the above effect, between the high impurity concentration electrode regions 23 and 24 to which a voltage higher than a certain reverse voltage is applied, the entire region in the film thickness direction with a length approximately corresponding to the length of the low impurity concentration region 27 becomes a depletion layer. Therefore, the depletion layer region acts like an intrinsic region in a so-called pin structure diode at a voltage higher than the reverse voltage, so that the high reverse voltage semiconductor diode element of the present invention is realized. That is, in the semiconductor diode element according to the present invention, at a constant reverse voltage or higher, between the high concentration p+ and n+ electrodes 23 and 24,
It is only necessary to realize a fully depleted region that should absorb the voltage increase above the certain reverse voltage, and as shown in the embodiment, the reverse breakdown voltage of the semiconductor diode element is directly determined by the low impurity concentration region 27. Therefore, it does not depend on the impurity concentration of the silicon epitaxial film below the region, but rather depends on the length of the low impurity concentration region 27 which determines the length of the total depletion layer region. For example, when the film thickness and impurity concentration of the silicon epitaxial film 22 are given as in this embodiment, the low impurity concentration region 27 has a total effective impurity ion amount in the same region that ultimately contributes to the depletion layer. and the silicon epitaxial film 22 at the bottom of the same area.
Impurity ions of appropriate polarity and amount may be introduced by a method such as ion implantation so that the total amount of effective impurity ions therein is approximately equal to each other.

As described below, according to the present invention, when a diode element is formed in a semiconductor thin film on a dielectric insulating substrate, the film thickness and impurity concentration of the semiconductor thin film (i.e., the total amount of impurity ions in the film) are as follows: As long as the full depletion layer in the film thickness direction can be achieved, a wide range of choices can be made, so for example,
At the same time, a p-type or n-type field effect transistor is formed on the SOS substrate, and at the same time, on the SOS substrate,
A high voltage semiconductor diode element can be formed. For example, enhancement mode pMOS transistors often use a substrate concentration of 1 to 5 x 10 ¹⁵ cm ^-3 , while nMOS transistors often use substrate concentrations of about 1 to 4 x 10 ¹⁶ cm ^-3 . , when forming a semiconductor diode element according to the present invention, the low impurity concentration region 37 of the diode element,
If an appropriate optimum amount of impurity ions is introduced into 27' or 37, the low impurity concentration region 2
The semiconductor diode element having a reverse breakdown voltage corresponding to the length of 7, 27' or 37 can be formed. Furthermore, the specific resistance of the n-type SOS film having an impurity concentration of about 7×10 ¹⁵ cm ^-3 in Example 1 is the same as the specific resistance of the n-type SOS film having an impurity concentration of about 7×10 ¹⁴ cm ^-3 in the example described above. This is about one-tenth of the total. As is clear from these examples, in the semiconductor diode element of the present invention having the same reverse breakdown voltage,
Compared to a pn junction diode element, the forward series resistance can be significantly lowered, and the forward direction characteristics of the diode can be improved.

By the way, in this example, an SOS substrate was used as a semiconductor thin film on a dielectric insulating substrate, but the substrate material in the present invention does not necessarily have to be an SOS substrate. It may be a dielectric insulating isolation substrate such as a silicon single crystal thin film formed through a film. Furthermore, the semiconductor thin film may be made of something other than silicon.

Further, in the present invention, it is sufficient that the PN junction of the thin diode is depleted in the film thickness direction over a certain length during reverse bias.
In order to realize the structure of the present invention, various manufacturing steps such as first forming the low impurity concentration region 27 and then providing the insulating protective film 26 are required, without going through the manufacturing steps shown in this embodiment. It goes without saying that the following modifications are possible. Furthermore, although the diagrams of this embodiment show the case where each high impurity concentration electrode region reaches the dielectric insulating substrate, when implementing the present invention, the electrode regions do not necessarily reach the dielectric insulating substrate. It is clear from the above description of the operation that there is no need to do so.

[Brief explanation of the drawing]

Fig. 1 is a schematic cross-sectional view showing a conventional example, Fig. 2 a,
b, FIG. 3 is a cross-sectional schematic diagram showing an embodiment of the present invention;
FIG. 4 is a diagram for explaining the relationship between the reverse breakdown voltage and the amount of ion implantation in a diode. In each figure, 11 is a dielectric insulating substrate, 12 is an n-type semiconductor film, 13 is a p+ semiconductor region, and 14 is an n-type semiconductor film.
+ semiconductor region, 15 is oxide film, 21, 21', 3
1 is a sapphire substrate, 22, 22', 32 are epitaxial films, 23, 23', 33 are high impurity concentration electrode regions, 24, 24', 34 are high impurity concentration electrode regions of opposite polarity, 25, 25', 35 are high impurity concentration electrode regions. Silicon thermal oxide film, 26, 26', 36 are Al wiring, 27,
27' and 37 indicate low impurity concentration regions, respectively.

Claims (1)

[Claims] 1. A semiconductor layer provided on a dielectric insulating substrate,
Two independent electrode regions each consisting of a high impurity concentration region having the same first conductivity as the semiconductor layer and a high impurity concentration region having a second conductivity different from the semiconductor layer and covering the semiconductor layer. a second highly conductive high impurity concentration electrode region between the first and second conductive high impurity concentration electrode regions under the insulating protective film; A low impurity concentration region having a second conductivity different from the conductivity of the semiconductor layer is configured in contact with an end of the impurity concentration electrode region, and the impurity concentration of the low concentration region having the second conductivity is When the reverse voltage increases, the depletion layer formed between the low concentration region with the second conductivity and the semiconductor layer region with the first conductivity below the same region causes the two The entire region in the direction perpendicular to the high concentration electrode region is made into a depletion layer, and the depletion layer region extends from the high concentration electrode region having the second conductivity toward the high concentration electrode having the first conductivity. but,
A semiconductor diode element, characterized in that the semiconductor diode element is selected such that it is maximized in the same direction. 2 The semiconductor layer provided on the dielectric insulating substrate is
The semiconductor diode element according to claim 1, which is an n-type semiconductor. 3 The semiconductor layer provided on the dielectric insulating substrate is
The semiconductor diode element according to claim 1, which is a p-type semiconductor. 4 The low impurity concentration region having second conductivity is
2. The semiconductor diode element according to claim 1, which is constructed astride between two high impurity concentration electrodes having second and first conductivities. 5 The low impurity concentration region having second conductivity is
The semiconductor diode element according to claim 1, which does not reach the high concentration electrode region having the first conductivity.