JPS6130476B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a line monitoring system, particularly a time division transmission system in which a plurality of remote terminals are cascaded via a digital line, in which the status of a subscriber transmitted from the remote terminal is monitored. In addition to providing a status memory for storing information, an indicator bit indicating that a transmission error has occurred is set and stored in the status memory, and the master station can read the contents of the status memory to update the line. This invention relates to a line monitoring system that performs monitoring.

Time division transmission systems are known in which a plurality of remote terminals are cascaded via one digital line. In such a system, each remote terminal transmits status information of its own subscribers to the master station using a predetermined control channel on one frame, for example, and
On the master station side, a state memory is provided to store the above-mentioned state information, and its contents are updated when new state information is transmitted.

Although the present invention is not conditioned on the use of the above-mentioned control channel, the state information is stored in the state memory as described above, and the master station detects the state by reading the contents of the state memory. In such a system, if a transmission error occurs when transmitting the state information, erroneous data will be stored in the state memory, and the reliability of the read state information will be lost. For this reason, a system in which the master station checks the line status separately each time may be considered, but the processing procedure would be complicated.

The purpose of the present invention is to easily solve the above-mentioned problems, and when the above-mentioned status information is transmitted, it checks for transmission errors and writes whether or not there is a transmission error in the status memory. The purpose is to monitor the line at the same time as reading the data. Therefore, in the line monitoring system of the present invention, a plurality of remote terminals are cascade-connected via a common digital line, each of the remote terminals has one or more subscribers, and the digital line is an interface. In a time division transmission system connected to a master station via a face circuit, status information of subscribers belonging to the remote terminal is transmitted from each of the remote terminals, and the status information is stored on the master station side. It is equipped with a status memory that updates the stored contents in accordance with the new status information transmitted above, and when a transmission error occurs regarding the status information transmitted from each remote terminal, the fact is recorded in the status memory. and the state memory stores the original state information without being updated with the transmitted new state information when the transmission error occurs. It is characterized by This will be explained below with reference to the drawings.

Fig. 1 shows the configuration of an embodiment of a time division transmission system to which the present invention is applied, Fig. 2 is an explanatory diagram illustrating a mode of transmitting status information via a control channel, and Fig. 3 shows a conventional interface circuit. FIG. 4 shows the configuration of an embodiment of the interface circuit section used in the present invention.

In Fig. 1, 1 is the master station, 2 is the interface circuit, and 3-0 to 3-3 are the remote stations, respectively.
Terminals, SUB ₀ and SUB ₁ are remote terminals respectively.
Subscribers connected to terminal 3-0...
SUB ₆ or SUB ₇ are each remote terminal 3
-3 is connected to the subscriber; 4 represents the digital line;

Generally, a plurality of remote terminals 3-0 to 3-3 are cascade-connected via one digital line 4, and subscription is established by transmitting and receiving control information between the master station 1 and each remote terminal 3. person
A system for communicating between the SUB and the master station 1 is adopted.

In the case of such a system, the so-called out-channel method and the in-channel method are known for transmitting the control information, and the following description will be made assuming that the out-channel method is adopted. In the case of the out-channel method, as shown in FIG _.
A control information channel for transmitting control information is allocated to the control information channel, and the control information is transmitted using the control information channel. Each control information channel has a capacity that can store, for example, 8-bit information, and control information is transmitted in the following format, for example. That is, (A) in the control channel belonging to frame #0 shown in FIG. One bit of control information (8 bits in total) is transmitted, and (B) 8 subscribers connected to the remote terminal 3-1 ( 1 bit worth of control information for each subscriber (total 8
(C) Similarly, in the control channel belonging to frame #3 shown in FIG. 2, eight subscribers (group 0) connected to the remote terminal 3-3 (D) One bit of control information (8 bits in total) is transmitted for each subscriber related to the remote terminal 3-0 on the control channel belonging to the next #0 frame shown in Figure 2. One bit of control information (total of 8 bits) is transmitted for each subscriber for the next eight subscribers (referred to as the first group of subscribers). In the control channel belonging to frame #1, remote terminal 3-
The next 8 subscribers connected to 1 (the 1st
One bit of control information (8 bits in total) is transmitted for each subscriber regarding the group), and so on. Note that the above control information does not mean only state information as referred to in the present invention, but for the sake of simplicity, the description will be continued assuming that the above control information is immediate state information.

FIG. 3 shows an example of the configuration of a conventional interface circuit section corresponding to the interface circuit section 2 shown in FIG. Reference numerals 2 and 4 in the figure correspond to those in FIG. 1, 5 is a state memory, 6 is a serial-to-parallel conversion circuit, 7 is an address register, 9 is a data register, 10 is an address counter, 1
1 represents a decoder, and 12 and 13 each represent an AND circuit. Also, M ₀ is remote terminal 3
-0, _M1 represents the state information storage section corresponding to remote terminal 3-1, and _M3 represents the state information storage section corresponding to remote terminal 3-3. .

As explained with reference to FIG. 2, when the status information is transmitted, the time of each frame
AND circuits 12 and 13 are enabled to be turned on by the slot _T0 period signal. Then, the contents of the address counter 10 are counted up in synchronization with the bit clock that divides the time slot _T0 period. Assuming that the contents of counter 10 are all zero at the beginning, when 8 bit clocks are input, counter 1
The contents of 0 are "111, 00, 00..." from the left in the diagram. The illustrated decoder 11 decodes the contents of the remote terminal number RT corresponding section and reads the contents of the status information storage section M ₀
The address corresponding to the subscriber group 0 is accessed. On the other hand, at this time, the 8-bit status information converted into parallel information by the serial/parallel conversion circuit 6 is supplied to the status memory 5 via the AND circuit 12, and is stored at the address corresponding to the 0th group of subscribers in the storage section _M0. written to. That is, 8-bit information in the control channel belonging to frame #0 shown in FIG. 2 is written to the above address.

Next, at time slot _T0 in frame #1 shown in FIG. 2, when eight bit clocks are input, the contents of the counter 10 become "111, 10, 000...". As a result, the 8-bit status information transmitted in the #1 frame is written into the address corresponding to the subscriber of the 0th group in the status information storage section _M1 of the status memory 5. Thereafter, data is written in the same manner, and at the next #0 frame shown in FIG. 2, the contents of the counter ₁₀ become "111, 00, 100..." Status information is written to the address corresponding to the subscriber of the group.

As described above, the written status information is read by accessing the status memory 5 using address information, and the status information is detected at the master station 1. However, if a transmission error occurs during the transmission of the status information, the status information becomes unreliable.

Therefore, in the case of the present invention, attention is paid to the fact that an error check is performed on the transmitted information when the information is transmitted as described above, and the fact that a transmission error has occurred is stored in the state memory 5. This allows the master station to easily monitor the line status.

FIG. 4 shows an embodiment of the configuration of an interface circuit section used in the present invention. Codes 2, 4, in the figure
5, 6, 7, 9, 10, 11, 12, 13 are the third
Corresponding to the figure, 14 is an error check circuit, 15
16 and 17 are AND circuits, 18 is an OR circuit, and F ₀ to F ₁ are transmission error indicating bit storage areas.

Also in the case of the present invention, status information is transmitted from each remote terminal 3-0 to 3-3 as described with reference to FIGS. 1 to 3, and is stored in the status memory 5. There is no change in the content being updated. The above status information is still read out on the master station side. However, in the case of the present invention, when the above status information is received, the status information is checked by the error check circuit 14. Then, only when no error occurs, the AND circuit 12
is turned on, and the contents of the state memory 5 are updated. However, if an error has occurred, error check circuit 14 issues a logic "1", turns off AND circuit 12, and turns on AND circuit 17. At the same time, the output of the error check circuit 14 is written in the area F _i as a transmission error display bit. That is, the status information received when an error occurs is prevented from being written to the memory 5 by the AND circuit 12, and the original status information stored in the memory 5 is transferred through the AND circuit 17 together with the transmission error indication bit. is written to a predetermined location.

On the other hand, on the master station side, as described above, the contents of the status memory 5 are repeatedly read out to detect the status information of each subscriber. Therefore, if the transmission error indication bit is set in the read data, the parent station can easily detect that a transmission error has occurred and generate an alarm. Also, the read data at this time shows the original state information, that is, the state information before the error occurred. If erroneous data is written to the memory, erroneous processing may occur, such as the status bit of a channel that is supposed to be communicating erroneously indicating disconnection. In the present invention, by retaining the data before the error, it is possible to prevent erroneous processing due to a temporary error. Therefore, it becomes easy to deal with the above-mentioned transmission error.

As described above, according to the present invention, the line status can be easily monitored and no processing is performed based on erroneous status information.

[Brief explanation of the drawing]

Fig. 1 shows the configuration of an embodiment of a time division transmission system to which the present invention is applied, Fig. 2 is an explanatory diagram illustrating a mode of transmitting status information via a control channel, and Fig. 3 shows a conventional interface circuit. FIG. 4 shows the configuration of an embodiment of the interface circuit used in the present invention. In the figure, 1 is the master station, 2 is the interface circuit section,
3 is remote terminal, SUB is subscriber, 4
5 is a digital line, 5 is a state memory, 10 is an address counter, 14 is a transmission error check circuit, and 15 is a buffer register.

Claims (1)

[Claims] 1. A plurality of remote terminals are cascaded via a common digital line, each of the remote terminals has one or more subscribers, and the digital line is connected to the master station via an interface circuit. In the time-division transmission system to be connected, each of the remote terminals transmits the status information of the subscriber belonging to the remote terminal, and the master station stores the status information and receives the new status information that is transmitted. A state memory is provided for updating stored contents in accordance with the above, and when a transmission error has occurred with respect to the above state information transmitted from each of the above remote terminals, this fact is stored as a display bit on the above state memory, The line monitoring system is characterized in that, when the transmission error occurs, the state memory stores the original state information without being updated with the new state information that has been transmitted.