JPS6130798B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a telephone line signaling device, and more particularly to a conversion device for extending the time width of a dial pulse signal.

In international communication lines, regular telephone lines are set up between line control stations and relay stations in each country to facilitate business discussions regarding line operation and maintenance. For example, in the international submarine cable relay system, which is a type of international communications, it is possible to conduct business meetings over telephone lines between all line control stations and submarine cable landing stations connected to this system.

Rather than setting up different telephone lines between each office, such meeting telephone lines are set up in such a way that all stations share one specific telephone line channel that can send and receive, and each station is uniquely identified. A number is assigned so that any station can be called by dialing the identification number. (Such a system is called an omnibus system.) When setting up such an omnibus meeting telephone line, it is necessary to unify the signaling system for dialing, and usually international calls are based on the CCITT recommendations. Compliant. However, the exchanges used differ depending on the circumstances of each country, and dialing may not be possible because the signal conditions do not match. In such a case, a speaker is always connected to the channel assigned to the meeting telephone line and the other party is called by voice.

The present invention has been made in view of the above-mentioned circumstances, and an object of the present invention is to provide a dial signal conversion device with a simple configuration that enables dialing even if the dial signal conditions are different. This converts T ₁ to T ₂ (increases the time), and the principle is to sample the input dial pulse signal, write the sampled value to memory with a fast clock, read it from memory with a slow clock, and then The purpose is to lengthen the dial pulse sending time by the speed ratio. Conventionally, there are speed converters for dial pulses that use the same principle, but because there are strict regulations on the timing between the write clock and the read clock, the timing pulse generation circuit is complicated, and all information (sample value ) required a considerable amount of memory capacity to read after writing, and was accompanied by a time delay.

The feature of the present invention is the sampling clock (CL _S ).
Read mode and write mode can be set according to the level of the memory. When in write mode, the state of the input dial pulse from input terminal 1 is written to the specified address, and when in read mode, the contents of the specified address are read out. 13, a first counter 9 that specifies the address of the memory 13 in the write mode, a second counter 10 that specifies the address of the memory 13 in the read mode, and a write clock (CL _W ) that increments the first counter 9.
and a circuit 4 that generates a read clock (CL _R ) for incrementing the second counter 10.
and a dial pulse detector 11 that starts each of the circuits at the beginning of the input diamond pulse and stops the operation of each of the circuits when the second counter 10 reaches a predetermined value, The dial pulse signal converter is such that the relationship CL _S ≫ CL _W > CL _R is satisfied between the speeds of each clock. The fact that each clock (CL _S , CL _W , CL _R ) can be set arbitrarily within the range that satisfies the above inequality, and that the output pulse can be read before all bits of the input pulse have been written is completed. This is an important feature of the invention.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows the concept of the present invention. In the figure, (1) is a dial pulse signal (time length T ₁ ) that is the input to the device according to the present invention, and (2) is a dial pulse signal (time length T ₂ , T ₂ >T ₁ ) that is the output of the device. This shows the case when number 14 is dialed.

FIG. 2 shows an embodiment according to the present invention, in which 1 is an input terminal, 2 is an output terminal, and 3 is a write clock.
CL _W generation circuit, 4 readout clock CL _R generation circuit, 5 sampling clock CL _S generation circuit,
6, 7, 8 are gate circuits, 9 is write clock
A counter 10 counts the read clock CL _W and specifies the memory address. 11 is a counter that counts the read clock CL _R and specifies the memory address. 11 is set at the beginning of the input dial pulse (t ₀ in Figure 1). Open gates 6, 7, 8 and counters 9, 10
is initialized (setting the contents of the counter to 0), and is reset by the carry pulse of counter 10 (occurs at time _t1 in Figure 1), and the diamond pulse detection operates to close gates 6, 7, and 8. In this case, the diamond pulse detector indicates the section _T2 in FIG. 12 is the sampling clock
A read/write selector which alternately outputs the outputs of counters 9 and 10 to the memory 13 by _CLS , and outputs the output of the memory 13 to the latch circuit 14 only when the memory 13 is in read mode; 13 is a sampling clock _CLS 14 is a memory 1 that is input via a read/write selector 12 (for example, μPD2102 manufactured by NEC Corporation can be applied).
This is a latch circuit for holding the output information of No. 3 for only the period of the sampling clock _CLS .

A time chart is shown in FIG. 3 to facilitate understanding of the operation of this embodiment. In the figure, 1 is an input dial pulse signal, dotted lines and solid arrows indicate sample values, solid arrows are sample values that ultimately remain in the memory 13, 2 is CL _S , 3 is CL _W , 4 is
CL _R , 5 indicates the output dial pulse signal.

Next, the operation will be explained. Dial pulse detector 1
When the start of the dial pulse train is detected by 1, gates 6, 7, and 8 open, and at the same time, counters 9 and 1 open.
0 is initialized. The memory 13 alternately repeats the read mode R and the write mode W by the sampling clock _CLS , and the state of the input dial pulse signal in the write mode W is "0".
Or "1" is written to the memory address specified by the counter 9, effectively sampling the input dial pulse signal and writing it to the memory.
In the subsequent read mode R, the memory contents are read from the memory address specified by the counter 10 and sent to the latch circuit 1 via the read/write selector 12.
4, and the latch circuit 14 outputs the same next state to the output terminal until the next read mode. Starting from the point where the initialized counters 9 and 10 both specify address 0, the sample value of the input dial pulse is stored in the memory 13 until counter 9 specifies address 1 using the write clock CL _W.
is repeatedly written to address 0 in read mode R.
Then, the counter 10 repeatedly reads out the state of the same address 0 until address 1 is designated by the read clock _CLR , and that state appears at the output terminal. It can be seen here that the time delay between the input dial pulse and the output dial pulse is only the time of 1 read mode R for the first bit.

As mentioned above, the speed of each clock is in the relationship CL _S ≫ CL _W > CL _R , so counter 9
is incremented faster than the counter 10 and specifies the 1st address, and the sample value immediately before specifying the 1st address remains at the 0th address, and in read mode R, the sample value at the 0th address remains until the counter 10 specifies the 1st address. The status will continue to be output. The input dial pulse will therefore appear at the output terminal stretched by the ratio of the write clock speed CL _W to the read clock speed CL _R . From now on, the above operation will be repeated.

The required capacity of the memory 13 is determined in advance by the time width _T1 and the write clock _CLW shown in FIG. When the counter 10 finishes specifying the last address, it is assumed that the dial pulse processing has ended, and the dial pulse detector 11 is reset and the gates 6, 7, and 8 are closed. The designation of the last address is detected, for example, by an overflow of the counter 10.

As explained above, according to the present invention, there is no need to synchronize each clock, and CL _S ≫ _{CL W} > CL _R
Any speed can be selected in the range of Since no special circuit is required for this purpose, it is possible to realize a compact dial pulse conversion device with a high overall processing speed and a simple configuration.

As an example, CL _S is 5KHz and CL _W is 133
If Hz and CL _R are set to 106Hz, the input dial pulse will be elongated by about 25% (133/106=1.25) and output.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of the basic concept of the present invention, FIG. 2 is a configuration example of a dial pulse signal converting device according to the present invention, and FIG. 3 is an explanatory diagram of the operation of the device shown in FIG. 2. 1...Input terminal, 2...Output terminal, 3...Write clock ( _CLW ), 4...Read clock ( _CLR ), 5...Sampling clock ( _CLS ), 6, 7, 8... ...gate, 9...first counter, 10...second counter, 11...dial pulse detector, 12...read/write selector,
13...Memory, 14...Latch.

Claims (1)

[Claims] 1 Read mode and write mode can be set according to the level of the sampling clock (CL _S ). When in write mode, the state of the input dial pulse from input terminal 1 is written to the specified address, and when in read mode, it is possible to set the read mode and write mode. A memory 13 that reads the contents of a designated address, and a first counter 9 that designates an address in the write mode of the memory 13.
, a second counter 10 that specifies an address in the read mode of the memory 13, and a first counter 9.
a circuit 3 for generating a write clock (CL _W ) for incrementing the second count, a circuit 4 for generating a read clock (CL _R ) for incrementing the second count 10, and starting each of the above circuits at the beginning of the input dial pulse; It has a dial pulse detector 11 that stops the operation of each of the above-mentioned circuits when the second counter 10 reaches a predetermined value, and between the speeds of each of the above-mentioned clocks, CL _S >> CL _W > CL _R A dial pulse signal converter characterized in that the following relationship is satisfied.