JPS6131522B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention is utilized to reproduce correct digital data from the read output of a magnetic storage device. The present invention relates to a signal reading method in which one data logical value (for example, "1") is set when a signal waveform reaches an upper or lower peak.

〔overview〕

The present invention is a reading method that reads digital data corresponding to the peak position from an input signal having positive and negative peaks, which differentiates the input signal with respect to time, detects the position where the differentiated output becomes zero level, and further differentiates the input signal from the differentiated output. is sliced by the first positive/negative threshold (±V ₁ ), and this slice output is integrated by a leakage integration circuit that is reset each time the differential output reaches zero level, and this integral output is determined by the second threshold (V ₂ ). ), by using the zero level of the differential output as the reading output, it is possible to perform error-free reading even when the input signal is a series of "1" or "0". It is.

[Conventional technology]

In a digital magnetic storage device such as a magnetic tape device or a magnetic disk device, the signal waveform read by the magnetic head is an analog signal waveform as shown in FIG. It is necessary to correctly reproduce digital data by setting the peak position of this signal waveform, which appears alternately upward and downward in synchronization with a predetermined clock signal, as "1" and the others as "0".

The basic method of conventional reading is to time-differentiate this input signal and detect the point where the differential value becomes zero as a peak.

[Problem that the invention seeks to solve]

However, as shown in FIG. 1A, in the case of a signal with a low recording density and a series of "0"s, the differential amount becomes zero even at the position of the arrow in the figure, and an error occurs. To correct this, we set the detection condition to be that this input signal crosses the zero level between one peak and the next peak, and set the point where the differential value becomes zero as "1". There is a way. According to this method, as shown in Figure 1B, in a signal with a high recording density and a series of "1"s, there is no zero crossing between the peaks at the points indicated by arrows in Figure 1B, so this can be overlooked and an error can be made. becomes.

In order to improve this problem, there are known methods of slicing the signal or monitoring the average level of the signal amplitude to determine peaks with amplitudes greater than a predetermined value. In order to achieve high accuracy over a wide range, the circuit configuration has to be quite complex.

The present invention is an improvement on this, and an object of the present invention is to provide a reading method that can correctly detect data even when the input signal is considerably distorted, with a simple circuit configuration.

[Means for solving problems]

The present invention provides a reading method for reading digital data corresponding to the peak position from an input signal having positive and negative peaks, which includes a differentiating circuit 3 that differentiates the input signal with respect to time, and a position where the output of this differentiating circuit reaches zero level. a zero level detection circuit 4 for detecting a zero level, slicing circuits 6, 7, 8 for slicing the output of the differentiating circuit using a first positive/negative threshold (±V ₁ ); A leakage integration circuit 10 that is reset each time the voltage reaches the level, and whose discharge time constant is larger than the charging time constant, and a comparison circuit 11 that detects that the output of this leakage integration circuit exceeds a second threshold (V ₂ ). and an AND circuit 12 which performs a logical product of the output of this comparison circuit and the output of the zero level detection circuit.

[Effect]

The circuit of the present invention also differentiates the input signal with respect to time, detects the point at which the differential value becomes zero level as a peak, and outputs data (for example, "1". However, after the differential value becomes zero, Next, in order to ensure that the level difference of the input signal is greater than a predetermined level until this differential value becomes zero again, this differential value is integrated by an integrating circuit that is reset each time the differential value becomes zero. That is, this integral output indicates the level difference of the input signal from when the differential value becomes zero to when it becomes zero again.The condition is that this integral output exceeds a predetermined value.

However, this alone cannot necessarily remedy the error when the input signal continues to have "0"s. For this reason, the differential value input to the above-mentioned integrating circuit is sliced using positive and negative thresholds, and the above-mentioned integrating circuit is also used as a leakage integrating circuit to perform incomplete integration. ,
The integral value decreases due to leakage, and the differential value of zero at this time is excluded so as not to be treated as data. A specific example of this operation will be explained in detail in the next embodiment.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 2 is a block diagram showing one embodiment of the present invention. In FIG. 2, reference numeral 1 is a magnetic head, 2 is an amplifier circuit, 3 is a differential circuit, 4 is a zero level detection circuit, 5 is a one shot circuit, 6 and 7 are comparison circuits, 8 is a NOR circuit, 9 is a one shot circuit, 1
0 is an incomplete integration circuit with reset, 11 is a comparison circuit, and 12 is an AND circuit.

The output of the magnetic head 1 is an input signal to this circuit, which is applied to a differentiating circuit 3 via an amplifier circuit 2. This output is given to each input of a zero level detection circuit 4 and two comparison circuits 6 and 7.
The comparison inputs of the comparison circuits 6 and 7 are supplied with voltages +V ₁ and -V ₁ that provide positive and negative slice levels, respectively. The outputs of these two comparison circuits 6 and 7 are led to the input of a NOR circuit 8, and the output thereof is given to the input of an integration circuit 10.

On the other hand, the output of the zero level detection circuit 4 is given to the input of a one-shot circuit 5, and this output is led to one input of another one-shot circuit 9 and an AND circuit 12. The output of this one-shot circuit 9 is coupled to the reset input of an integrating circuit 10. The output of this integrator circuit 10 is the comparator circuit 1
1 comparison input. This comparison circuit 11
The comparison input of is supplied with a voltage V ₂ which provides a comparison reference. This output is led to one input of AND circuit 12.

FIG. 3 is a circuit diagram showing an example of the configuration of the incomplete integration circuit 10 with reset. Drawing code 13, 14
is an open collector type inverter, 15, 17
is a resistor, 16 is a diode, and 18 is a capacitor. That is, this integrating circuit receives the signal e as an input and performs leak type integration while repeating reset using the reset signal f. Its output becomes an inverted output.

The operation of the circuit configured as described above will be explained using the waveform time chart shown in FIG. FIGS. 4a to 4i are waveform diagrams of points with corresponding symbols indicated by crosses in FIGS. 2 and 3. FIGS.

The input signal a obtained from the magnetic head 1 is amplified to an appropriate amplitude by an amplifier circuit 2, and differentiated with respect to time by a differentiator circuit 3. The waveform becomes the one shown in FIG. 4b, and is supplied to the zero level detection circuit 4. The inversion position of the output c of the zero level detection circuit 4 corresponds to the peak position of the input signal a, and the one-shot circuit 5 produces a peak output d at this inversion position. Furthermore, the one-shot circuit 9 operates at the trailing edge of this peak output d, and a reset signal f for the integrating circuit 10 is generated. Note that the output pulse widths T ₁ and T ₂ of both one-shot circuits 5 and 6 are set sufficiently small with respect to the minimum data interval.

On the other hand, the output b of the differentiating circuit 3 is also given to the comparators 6 and 7, and compared with the positive and negative slice levels ±V1, and the logical sum is taken by the NOR circuit 8 to obtain the output e. This becomes a signal for identifying whether the differential output b is within ± _V1 or outside. That is, in FIG. 4, when the signal e is at the lower level (-1) in the figure, the output b is between ±V1, and when it is at the upper level ( ₀ ), it is outside.

In the incomplete integration circuit 10 with reset, this signal e is integrated while being repeatedly reset by the reset signal f. The output waveform is a waveform whose sign is inverted from that of the signal e, as shown in FIG. 4g.

As shown in FIG. 3, this integrator circuit 10 inputs a signal e and inverts it with a charging time constant: R ₁ +R ₂ /R ₁ +R ₂ C and a discharging time constant: R ₂ C until a reset signal f appears. It will be incompletely integrated. Note that from the above relationship, charging time constant < discharging time constant.

This integrated output g is compared with the voltage +V ₂ in a comparison circuit 11 to obtain a comparison output h. This comparison output h is matched with the peak output d by the AND circuit 12 and becomes the read data output i.

This comparison output h is a signal that guarantees a level difference from one peak to the next peak of the input signal a. In other words, in the case of a high recording density signal in which "1"s are continuous in the input signal a, "0"s frequently appear in the differential waveform b, and the integrating circuit 10 is frequently reset. Since the discharging time constant of the integrating circuit 10 is larger than the charging time constant as described above, the discharging time constant does not matter if reset is performed frequently. Therefore, since the integral output of the integrating circuit 10 is a value obtained by inversely integrating the differential value of the input signal a, it represents the level difference from one peak to the next peak of the input signal a. Therefore,
By appropriately setting the charging time constant of the integrating circuit 10 and the comparison voltage V ₂ of the comparator circuit 11, it is possible to guarantee a level difference from one peak to the next peak of the input signal a.

On the other hand, in the case of a low recording density signal in which the input signal a has a series of "0"s, the differential output of the input signal a reaches the zero level, as shown by the arrow in Figure 1A or Figure 4A. It becomes "0". Since the integrating circuit 10 is reset every time the differential output becomes "0",
It is also reset at the point indicated by the arrow above, which is not the peak. Therefore, when the differential value of the input signal is reset and integrated in this way, the integrated output will represent the level difference from one peak to the zero level of the input signal, and the level difference from the zero level to the next peak. . In other words, the height of the peak relative to the zero level is guaranteed.

However, if things remain as they are, the zero level of the differential value (arrow shown in Figure 4 d) that occurs when input signal a continues to have "0" and input signal a reaches zero level will be valid as data "1". I get used to it. For this reason, the integrating circuit 10 is of a leak type. That is, if the discharge time constant of the integrating circuit 10 is made small to some extent, the integrating circuit 10 will not maintain its output state, and its output level will gradually decrease when the input to the integrating circuit 10 disappears. This is represented by the fact that the upper right corner of the integral waveform in FIG. 4g is missing. At the point indicated by the arrow in FIG.
Since the voltage falls below V ₂ , the differential value "0" at this time, that is, the pulse indicated by the arrow in FIG. 4d, does not become data.

Furthermore, regarding the differential value input to this integrating circuit 10, the part where the value is near the zero level and its sign is not determined is removed, and the differential value becomes valid only when it swings significantly in the positive or negative direction. I did it like that. That is, as shown by the arrow in FIG. 1A, when the input signal has a series of "0"s and its differential value is near zero, the input to the integrating circuit 10 is set to zero and no integration is performed, and the above-mentioned procedure is performed. The integrated output level is ensured to decrease due to the effect of discharge leakage. Even in this way, the integrating circuit 10
It does not matter much that the output of can guarantee the amplitude of the input signal a. That is, whether integration is performed or not when the differential output b is near the zero level, since the input level of the integrating circuit 10 is small, there is no significant effect on the integral output for guaranteeing the amplitude level.

For this purpose, as shown in FIG. 4b, the differential output b
When is inside ±V ₁ , the output signal e is sliced to zero. In this way, by making the integrating circuit 10 a leak type and slicing its input differential value, even when the input signal a has a series of "0"s, the differential value "0" is erroneously converted into data "1" will no longer be used.

Note that the method of the present invention is based on the slice level (±
There are elements that require adjustment in the settings of V ₁ ) and the time constant of the integrating circuit. However, by setting this according to the clock period and level of each individual signal, it is possible to adjust and set it so that no errors occur for all possible data combinations of practical input signals in one device. Is possible. Moreover, this adjustment setting is fixed for one type of system, and once designed, there is no need to make adjustments in individual devices.

〔Effect of the invention〕

As explained above, in the reading method of the present invention, the value obtained by differentiating the input signal is input, the integrating circuit for guaranteeing the amplitude of the input signal is a leak type, and the input signal is sliced. Even when a signal has a series of "1"s or "0"s, error-free reading can be performed over a wide range of recording densities.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the waveform of a read signal in a magnetic storage device, FIG. 2 is a block configuration diagram of an embodiment of the present invention,
FIG. 3 is a circuit diagram showing an example of an incomplete integration circuit with leakage, and FIG. 4 is a time chart for explaining the operation of the above embodiment. 1...Magnetic head, 2...Amplifying circuit, 3...Differentiating circuit, 4...Zero level detection circuit, 5, 9...One shot circuit, 6, 7, 11...Comparing circuit, 8
...NOR circuit, 10...Incomplete integration circuit with leak, 12...AND circuit.

Claims (1)

[Claims] 1. A reading method for reading digital data corresponding to the peak position of an input signal having positive and negative peaks, which includes a differentiating circuit 3 for time-differentiating the input signal, and an output of this differentiating circuit having a zero level. A zero level detection circuit 4 detects the position where
Slice circuits 6, 7, 8 that slice by V ₁ )
The output of this slice circuit is reset every time the output of the differentiating circuit becomes zero level, and the leak integration circuit 10 has a discharging time constant larger than a charging time constant.
and a comparison circuit 11 that detects that the output of this leakage integration circuit exceeds the second threshold (V ₂ ).
and an AND circuit 12 which performs a logical product of the output of the comparison circuit and the output of the zero level detection circuit.