JPS6131555B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to memory devices, and more particularly to high speed sense circuits constructed within memory integrated circuits.

In a large-capacity memory integrated circuit, the number of sense circuits increases, so the power product of each sense circuit also increases, which poses a problem. Generally, reducing the power product of the sense circuit has the disadvantage of increasing the sensing time of the state of the storage cell, increasing the cycle time of the storage integrated circuit.

The present invention has been made to solve the above-mentioned drawbacks, and by providing a plurality of sense circuits that minimize the electrical connection time to the memory cells and using them sequentially, the apparent operation of the sense circuits is improved. This is to save time. Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 1 shows an embodiment of the present invention, in which 1 is an address receiver, 2 is an address decoder, 3 is a read latch, 4 is a write latch, 5 is a storage cell group, and 6 is a write latch.
7 is a sense circuit group, 7 is a data driver, 8 is a data receiver, and 9 is a data latch. In this embodiment, the storage operation is pipelined and consists of five phases. Figure 2 shows this time chart. The address information is read into the address receiver 1 at the phase. If this operation specifies writing, the write data is read into the data receiver 8. The decoder 2 decodes the address information and sends it to the read latch 3. The write data is sent to data latch 9. The data of the memory cell 5 specified by the read latch 3 is taken into the sense circuit 6 according to the phase. When there is write data, the write data is taken into the sense circuit 6. Furthermore, the address information of read latch 3 is the address information of write latch 4.
sent to. In this phase, the data in the sense circuit 6 is rewritten into the memory cell 5 specified by the write latch 4. It is sent to the data driver 7 of the sense circuit 6 in phase.

FIG. 2 shows the operation regarding five pieces of address information. Although this storage operation requires time intervals of five phases for access time, data of any storage cell can be obtained in one phase cycle time.
For this purpose, each part constituting the storage device operates independently, and simultaneously performs storage operations for different addresses.

FIG. 3 shows details of the memory cell group 5 and sense circuit group 6 in FIG. 1. The memory cell group 5 consists of a large number of memory cells 5-1, 5-2,...5-n, and as shown in the figure, word lines a-1, a-2,...a-n,
Bit line b is connected. The sense circuit group 6 consists of three sense circuits 6-1, 6-2, 6-3,
each connected to bit line b via a gate,
configured to sense the state of the same storage cell. Each gate is opened by clocks ψ C-1 , ψ C-2 and ψ C-3 from the sense circuit selection circuit 10 via sense circuit selection lines C _-1 , _C-2 and _C-3 . Further, 3-1 is a read latch, 4-1 is a write latch, 9-1 is a data latch, 11 is a bit line potential setting circuit, and 12 is a comparison circuit. ψ _R , ψ _W , ψ
_S , _ψC , and _ψD operate at the timing shown in FIG. 4, and the basic timer is τ.

The operation of reading data from the memory cell group 5 to the sense circuit group 6 and writing to the memory cell group 5 will be described below.

Read operation: (1) Turn on the clock ψ _S and set the potential of bit line b to approximately the intermediate potential between the on-state and off-state potentials of the memory cell.

(2) Next, the sense circuit specified by the sense circuit selection circuit 10, for example 6-1, and the bit line b are electrically connected by turning on the clock ψ _C-1 .

(3) Then, by turning off the clock ψ _S and turning on the clock ψ _R , the state of the memory cell, for example 5-1, specified by the read latch 3 is taken into the sense circuit 6-1 through the bit line b.

(4) Next, the clocks ψ _C-1 and ψ _R are turned off to electrically disconnect the sense circuit 6-1 and the bit line b.

(5) The sense circuit 6-1 amplifies the storage cell state signal taken in during the period 2τ. At the same time, the information in read latch 3 is transferred to write latch 4.

(6) Clock ψ _C-1 turns on 2τ after turning off. At the same time, the clock ψ _W is turned on to rewrite the state in the specified memory cell 5-1.

(7) Next, clocks ψ _C-1 and ψ _W are turned off, and after electrically disconnecting bit line b, memory cell 5-1, and sense circuit 6-1, clock ψ _S is turned off.
Turn on. After that, the sense circuit 6-
The state signal amplified within 1 and the sense state output line d
Output through -1.

Write operation: In the above (3) phase, the clock ψ _D is turned on, the state of the data latch 9-1 is guided to the memory cell 5-1 and the sense circuit 6-1 through the bit line b, and the data latch 9-1 is Set the state of. Furthermore, the information in the write latch 4 of the read latch 3 is compared in the comparator circuit 12, and if a match is detected, the memory operation for the preceding data is started.
(6) Suppress phase operation. The meaning of this will be explained later. The other operations (1), (2), and (4) to (7) are the same as the read operation.

The storage device shown in FIG. 1 is as shown in FIG.
The memory cell group 5 is used in phases. However, since the memory cell group 5 is read into the sense circuit in the first half of the phase and written in the sense circuit in the second half, the memory cell group 5 is not used temporally overlappingly. On the other hand, sense circuits are used for phase, phase, phase. In order to cope with this, three sense circuits are provided and supported by sequentially using them as shown in FIG.

In the above operation, when ψ _C-1 is in the off state, the memory cell group 5 is electrically disconnected from the sense circuit 6-1, so the other sense circuits 6-2, 6
-3 can be electrically connected to the memory cell group 5. FIG. 5 shows this situation, where R and W indicate the connection state, respectively, and R is the phase (3) mentioned above;
W is (6) phase. In the figure, three sense circuits are sequentially used by sequentially turning on and off ψ _C-1 , ψ _C-2 , and ψ _C-3 . R _W is for write operation, W _SP is read latch 3 and write latch 4.
This is an example where the information matches, indicating that writing is suspended. This is clear from Figure 5,
If two consecutive addresses are the same and are specified in the order of writing and then reading, the read data becomes the data before writing. Therefore, this situation is detected by the comparator circuit 12 and writing is temporarily suspended.

As described above, according to the present invention, the electrical connection between the sense circuit and the memory cell group is minimized, and during the operation of the sense circuit, when it is not connected to the memory cell group, other Since the sense circuits can be connected in sequence, the sense circuits operate in multiple ways, which apparently reduces the operating time of the sense circuits.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention;
Figure 2 is a diagram explaining the operation of Figure 1, Figure 3 is a diagram showing details of the memory cell group and sense circuit group of Figure 1, and Figures 4 and 5 are diagrams explaining the operation of Figure 3. This is a diagram. 5... Memory cell group, 5-1, 5-2, 5-n...
...Storage cell, 6...Sense circuit group, 6-1, 6-
2, 6-3...Sense circuit, 10...Sense circuit selection circuit.

Claims (1)

[Claims] 1. In a memory device having a plurality of memory cells and a sense circuit that senses the state of the memory cell via a bit line and outputs the sense circuit, the plurality of sense circuits are connected to the same bit line through respective gates, A memory device characterized in that the plurality of sense circuits sequentially sense and output the states of the same memory cell.