JPS6131635B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit including a transistor having a structure that concentrates a main current in the center of a main current path.

In transistors that make up conventional integrated circuits, carriers flowing from one main electrode spread out in other directions due to diffusion while reaching the other main electrode, reducing the carrier's arrival rate and causing the carriers to reach the control electrode. This has the major disadvantage that the control effect by a certain base or gate is weakened and power is wasted.

The present invention eliminates the drawbacks of the transistors constituting the conventional integrated circuit described above, prevents the carriers flowing from one main electrode of the transistor from spreading, performs efficient control, and reduces power consumption. is intended to do.

Next, the present invention will be explained in detail with reference to the drawings. FIG. 1 is an example of drive and load transistors constituting a conventional integrated circuit. Main electrode 1
The carrier injected from the main electrode 3 spreads out as shown by the arrow in the figure due to lateral diffusion before passing through the base 2, and does not reach the main electrode 3 efficiently.
stomach.

FIG. 2 shows an example of a transistor included in the semiconductor integrated circuit of the present invention, in which the carrier from the main electrode 1 is thicker at the peripheral portion 21 of the base than the central portion 22. It concentrates on the main electrode 3 and efficiently reaches the main electrode 3 as shown by the arrow in the figure. This is because the depletion layer due to the diffusion potential in the peripheral part 21 of the base is expanding, so the carriers are concentrated, and even if the carriers enter the peripheral part 21, the carriers will move due to diffusion in the peripheral part 21. As a result, the speed decreases, and while moving through the thick part, the particles disappear due to recombination. Therefore, control efficiency by the base is increased, power consumption is reduced, and parasitic resistance present in the lateral direction of the gate is reduced. Furthermore, as is clear from the figure, even if the main current path is narrowed,
It also has the advantage that it is easy to make contact with the main electrode 3. These features are the same for all embodiments below.

FIG. 3 shows another embodiment of the present invention, in which the thick portion 21 of the base in FIG. 2 has a shape 23 projecting on both sides. This structure has an even greater effect of concentrating current.

FIG. 4 shows still another embodiment of the present invention, which has a structure having a peripheral portion 24 having a higher impurity density than the central portion 22 of the base. This embodiment also has the same effects as the previous embodiment, and furthermore, the base region can be made uniformly thin, reducing the stray capacitance of the element.
It also has features that are effective in making it thinner. If the structures shown in Figures 2 to 3 and Figure 4 are used in common, that is, there are thick parts and parts with high impurity density, or if the structure is thick and has parts with high impurity density, the current will be concentrated. Of course, the effect will be even higher.

The thin portion 22 at the center of the base in FIGS. 2 to 4 may be almost pinched off in the depletion layer, in which case the inventor of the present application
As proposed in the patent application ``Semiconductor Integrated Circuit'' filed on 2006, the object of the present invention can be better achieved because the carrier passes through the pinch-off portion at the same time as it has the characteristic of rising characteristics.

Although FIGS. 1 to 5 have described integrated circuits including bipolar transistors (hereinafter referred to as BPTs), the present invention is of course also applicable to integrated circuits including static induction transistors (hereinafter referred to as SITs). Integrated circuits including SIT are attracting attention for their ultra-high speed and ultra-low energy consumption.
As with BPT, it had the disadvantage that the current spread and control efficiency decreased.

FIG. 5 shows an integrated circuit including an SIT according to the present invention.
In the STI part, the peripheral part of the base in the case of BPT 2
It has a peripheral portion 41 of the gate corresponding to 1, 23, and 24. In this case, due to the same effect as in the above case, the current is concentrated in the central part 42 of the main current path as shown by the arrow in the figure, allowing more efficient gate control and further reduction in power consumption. realizable. When the gate of the SIT is used as a reverse bias, all carriers are concentrated in the path 42, and even when carriers are injected from the gate as a forward bias, the current can be concentrated in the same manner as in the case of the BPT. Of course, the same applies to the case where carrier injection from the gate is not performed as forward bias.

FIG. 6 shows still another embodiment of the present invention, in which the opposite conductivity type portion 11 in contact with the base center portion 22 is configured to have a lower impurity density than the portion 12 in contact with the base peripheral portion 21. In this structure, the carrier flows mostly through the central portions 11 and 22, allowing the current to be concentrated. Although FIG. 6 shows an example in which the base peripheral portion 21 and the substrate side 12 are in contact with each other, the same effect can of course be obtained even if another region is inserted between them.

Figure 6 is an example in which the structure of Figure 2 is used in parallel.
Of course, it can be applied to all of FIGS. 1 to 5.

FIG. 7 shows an example applied to the conventional type shown in FIG. 1, in which the central portion 11 in contact with the base has a lower impurity density than the peripheral portion 12, making it possible to achieve current concentration. This structure also has the advantage of being easy to manufacture.

In the above embodiments, the base or gate has been distinguished as a center part and a peripheral part for convenience, but of course it does not necessarily have to be in the center, and the names indicate the path of the main current. The effect of the present invention is greatest when the center portion is coaxial with the main electrode. Also, we are using a structure in which current flows almost perpendicular to the element surface as an example.
Of course, the present invention can be applied without being limited to this.

FIGS. 8a to 8f show an example of the manufacturing process of an embodiment of the present invention used as a driving transistor of a transistor I ² L (Integrated Injection Logic) having the structure shown in FIG. First, it is an n-type with a specific resistance of 0.005Ω-cm.
N-type on Si semiconductor substrate with specific resistance of 10 to 1KΩ-cm
(a), and a P-type region with a surface impurity density of 10 ¹⁵ to 10 ¹⁹ cm ^-3 is formed by selective diffusion.
(b), a region with a surface impurity density of /10 ¹⁵ to 10 ¹⁸ cm ^-3 is formed by selective diffusion in the P type (c), and a specific resistance of 10 to 1 K in the N type
A layer of Ω-cm was epitaxially grown (d) and selectively diffused with a surface impurity density of 10 ¹⁸ to 10 ²¹ cm ^-3 in P type.
(e), n-type selective diffusion with a surface impurity density of 10 ¹⁸ to 10 ²¹ cm ^-3 (f), and finally electrode attachment to complete the process.

FIG. 9 shows still another embodiment of the integrated circuit of the present invention, in which the transistor shown in FIG. 5 is used as a driving transistor in a portion 5 surrounded by a broken line in FIG.
An SITL (static
Injection Transistor Logic). Of course, this can also be manufactured by the same process as I ² L shown in FIG.

Although some embodiments of the present invention have been given above,
Of course, the present invention is not limited to these embodiments, but can also be applied to integrated circuits including transistors in which the main current flows approximately parallel to the element surface, to integrated circuits in which the carrier inflow direction operates in the opposite direction, to short-key type circuits, etc. It can be applied to a wide range of applications, such as transistors with electrodes such as MOS type. Further, the manufacturing process, specific resistance, conductivity type, semiconductor material, etc. are merely examples, and may be changed in various ways.

As described above, the present invention provides a structure that suppresses the spread of current passing through the main current path in a transistor in an integrated circuit. This is achieved by changing the shape.
By forming these structures of the present invention, it is possible to improve the control effect of the base or gate, reduce energy consumption, reduce parasitic resistance of the gate, etc., and at the same time, it is possible to enlarge the electrode extraction area and facilitate extraction. It has these advantages, and has extremely high industrial value in realizing the reform of semiconductor integrated circuits.

[Brief explanation of the drawing]

FIG. 1 is an example of a cross section of a transistor constituting a conventional integrated circuit, FIGS. 2 to 7 are cross-sectional views of an embodiment of a transistor constituting an integrated circuit of the present invention, and FIGS. FIG. 9 is a cross-sectional view showing an example of the manufacturing process of one embodiment of the present invention, and FIG. 9 is a cross-sectional view of still another embodiment of the present invention. 〓〓〓〓〓

Claims (1)

[Scope of Claims] 1. First and second semiconductor regions of a first conductivity type with high impurity density formed on a semiconductor substrate, and a small number of current paths flowing between the first and second semiconductor regions. A third semiconductor region of a second conductivity type and high impurity density formed to surround the common part is used as a control electrode, and a first semiconductor region in a region including the current path is used as a control electrode.
a fourth semiconductor region of a first conductivity type with a low impurity density disposed adjacent to the semiconductor region of the first conductivity type and a first conductivity type disposed adjacent to the second semiconductor region in the region including the current path; The fifth with low impurity density of
and a sixth semiconductor region of a second conductivity type connected to at least a common part inside the third semiconductor region in at least a common part of a plane perpendicular to the current path; and a seventh semiconductor region provided in the center of the sixth semiconductor region,
A semiconductor integrated circuit comprising a transistor configured to concentrate the current in the seventh semiconductor region. 2 the seventh semiconductor region is of the second conductivity type;
2. The semiconductor integrated circuit according to claim 1, wherein the thickness thereof is thinner than the thickness of the surrounding sixth semiconductor region. 3. The semiconductor integrated circuit according to claim 1 or 2, wherein the impurity density of the seventh semiconductor region is lower than the impurity density of the surrounding sixth semiconductor region. 4. The semiconductor integrated circuit according to claim 1, wherein the seventh semiconductor region is a first conductivity type low impurity density region.