JPS6131638B2 - - Google Patents
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- Publication number
- JPS6131638B2 JPS6131638B2 JP8850677A JP8850677A JPS6131638B2 JP S6131638 B2 JPS6131638 B2 JP S6131638B2 JP 8850677 A JP8850677 A JP 8850677A JP 8850677 A JP8850677 A JP 8850677A JP S6131638 B2 JPS6131638 B2 JP S6131638B2
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- Prior art keywords
- film
- electrode
- type semiconductor
- sio
- shows
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 239000004065 semiconductor Substances 0.000 claims description 56
- 239000002184 metal Substances 0.000 claims description 29
- 238000000034 method Methods 0.000 claims description 29
- 230000015572 biosynthetic process Effects 0.000 claims description 22
- 229920002120 photoresistant polymer Polymers 0.000 claims description 18
- 230000004888 barrier function Effects 0.000 claims description 16
- 238000004519 manufacturing process Methods 0.000 claims description 14
- 230000003647 oxidation Effects 0.000 claims description 14
- 238000007254 oxidation reaction Methods 0.000 claims description 14
- 230000015556 catabolic process Effects 0.000 claims description 6
- 230000001590 oxidative effect Effects 0.000 claims description 5
- 238000002048 anodisation reaction Methods 0.000 claims description 4
- 239000011248 coating agent Substances 0.000 claims 1
- 238000000576 coating method Methods 0.000 claims 1
- 238000004904 shortening Methods 0.000 claims 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 36
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 11
- 238000003486 chemical etching Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 7
- MUBZPKHOEPUJKR-UHFFFAOYSA-N Oxalic acid Chemical compound OC(=O)C(O)=O MUBZPKHOEPUJKR-UHFFFAOYSA-N 0.000 description 6
- 238000007743 anodising Methods 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 4
- 239000007864 aqueous solution Substances 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 239000003792 electrolyte Substances 0.000 description 2
- 235000006408 oxalic acid Nutrition 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000008151 electrolyte solution Substances 0.000 description 1
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 235000021419 vinegar Nutrition 0.000 description 1
- 239000000052 vinegar Substances 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
Description
【発明の詳細な説明】
本発明はシヨツトキ障壁型電極の製造方法に関
するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a shot barrier type electrode.
従来のシヨツトキ障壁型電極の製造方法はまず
n型半導体表面に該n型半導体とシヨツトキ接触
をなす金属層を被着し、該金属層上の電極形成部
分に通常のフオトレジスト法により電極形成のた
めのマスクを形成し、前記n型半導体表面上の該
金属層を化学エツチング法もしくは陽極酸化法に
より選択的に除去して、シヨツトキ障壁型電極を
形成しているが、化学エツチング法による従来の
製造方法は、全電極にわたつて均一な形状や幅に
制御することが極めて困難で、例えば幅が0.5〜
1.0μmの線状電極を形成しようとすると、電極
の形状に凹凸を生じたり、断線を生じたりする欠
点があり、かつ電極の寸法を特定の値に制御する
ことも困難であるなどの問題点があつた。一方、
陽極酸化法による従来の製造方法は、化学エツチ
ング法で問題となつたようなことは解決される
が、電極金属とともに該金属直下の半導体をも酸
化してしまい、したがつて半導体を全く酸化せず
に電極形成のためのマスク下の金属を陽極酸化し
て電極寸法を短縮することができない欠点があつ
た。 The conventional method for manufacturing a shot barrier type electrode is to first deposit a metal layer on the surface of an n-type semiconductor to make shot contact with the n-type semiconductor, and then to form an electrode on the metal layer using a normal photoresist method. The metal layer on the surface of the n-type semiconductor is selectively removed by chemical etching or anodic oxidation to form a shot barrier type electrode. With the manufacturing method, it is extremely difficult to control the shape and width to be uniform across all electrodes.
When trying to form a 1.0 μm linear electrode, there are problems such as unevenness in the shape of the electrode and disconnection, and it is also difficult to control the dimensions of the electrode to a specific value. It was hot. on the other hand,
The conventional manufacturing method using the anodic oxidation method solves the problems encountered with the chemical etching method, but it also oxidizes the semiconductor directly under the metal along with the electrode metal, and therefore does not oxidize the semiconductor at all. However, there was a drawback that it was not possible to shorten the electrode dimensions by anodizing the metal under the mask for electrode formation.
本発明の目的は前記の欠点、問題点を除去して
幅がサブミクロンオーダーのシヨツトキ障壁型電
極を一様な形状に選択的に形成でき、さらに電極
形成のためのマスク(電極形成マスクと称する)
の寸法より小さくできるシヨツトキ障壁型電極の
製造方法を提供することにある。 An object of the present invention is to eliminate the above-mentioned drawbacks and problems, to selectively form a short barrier type electrode with a width on the order of submicrons in a uniform shape, and to also provide a mask for forming the electrode (referred to as an electrode forming mask). )
An object of the present invention is to provide a method for manufacturing a shot barrier type electrode that can be made smaller in size than the above.
本発明によれば、n型半導体表面上に酸化力が
大きく、かつ該n型半導体とシヨツトキ接触をな
す金属層を被着し、該金属層表面上の電極形成部
分に陽極酸化のマスクたる絶縁被膜を被着し、陽
極に印加される電圧を前記シヨツトキ接触のブレ
〓〓〓〓〓
イクダウン電圧以下にしておこなう前記金属層の
陽極酸化と形成された酸化被膜の除去とを繰り返
しおこなつて電極形成部分を除く前記n型半導体
上の前記金属層を全て除去し、次に前記絶縁被膜
を除去することにより、n型半導体表面にシヨツ
トキ障壁型電極を均一な幅や形状に、常に制御性
再現性良く形成することができるシヨツトキ障壁
型電極の製造方法を得ることができる。 According to the present invention, a metal layer having a high oxidizing power and making a sudden contact with the n-type semiconductor is deposited on the surface of the n-type semiconductor, and an insulator serving as a mask for anodic oxidation is applied to the electrode formation portion on the surface of the metal layer. After depositing the film, the voltage applied to the anode is changed to the fluctuation of the shot contact.
The anodic oxidation of the metal layer performed below the take-down voltage and the removal of the formed oxide film are repeated to remove all of the metal layer on the n-type semiconductor except for the electrode forming portion, and then the insulating film is removed. By removing , it is possible to obtain a method for manufacturing a shot barrier type electrode that can always form a shot barrier type electrode with uniform width and shape on the surface of an n-type semiconductor with good controllability and reproducibility.
この発明は電極形成部分を掘り込んだリセス
(recess)構造にも適用でき、さらにn型半導体
表面に、該n型半導体と電子濃度が異なるn型半
導体導電層、さらにはp型半導体導電層を有する
構造にも適用できる。 This invention can also be applied to a recess structure in which the electrode formation portion is dug, and furthermore, an n-type semiconductor conductive layer having a different electron concentration from that of the n-type semiconductor, and furthermore a p-type semiconductor conductive layer are formed on the surface of the n-type semiconductor. It can also be applied to structures with
電極金属はn型半導体に対してシヨツトキ接触
をなすようなものが選ばれているので、陽極に印
加される電圧をシヨツトキ接触のブレイクダウン
電圧以下にする限り、該n型半導体は全く酸化さ
されず、電極金属だけが酸化される。 Since the electrode metal is selected to make a shot contact with the n-type semiconductor, as long as the voltage applied to the anode is below the breakdown voltage of the shot contact, the n-type semiconductor will not be oxidized at all. First, only the electrode metal is oxidized.
さらに絶縁被膜直下の金属をもさらに陽極酸化
し、形成された酸化被膜を除去することを繰り返
す場合であつても、n型半導体は全く酸化せず、
電極金属の寸法のみが短縮される。 Furthermore, even if the metal directly under the insulating film is further anodized and the formed oxide film is repeatedly removed, the n-type semiconductor will not oxidize at all.
Only the dimensions of the electrode metal are shortened.
次に、陽極酸化のための電極形成マスクの形成
方法について説明する。小さな寸法の電極形状の
製造には、電極の側面はできるだけ垂直であるこ
とが必要であるが、一般に取り扱いが容易なフオ
トレジスト膜は密着性が悪く、このような電極形
成マスクを用いて陽極酸化をおこなうと、電極金
属の側面は垂直にならずに緩い勾配を有してしま
う。このような場合には、あらかじめ電極金属表
面に薄い酸化被膜を形成したのちにフオトレジス
ト膜を被着して電極形成マスクとすると良い。 Next, a method for forming an electrode formation mask for anodic oxidation will be described. In order to manufacture electrode shapes with small dimensions, it is necessary that the sides of the electrode be as vertical as possible, but photoresist films, which are generally easy to handle, have poor adhesion, so anodization using such an electrode formation mask is difficult. If this is done, the side surfaces of the electrode metal will not be vertical but will have a gentle slope. In such a case, it is preferable to form a thin oxide film on the surface of the electrode metal in advance and then cover it with a photoresist film to serve as an electrode formation mask.
このように、本発明を用いると取扱いが容易な
フオトレジスト膜を電極形成マスクとして使用す
ることができ、制御性の良い電極を形成すること
ができる。 As described above, according to the present invention, an easy-to-handle photoresist film can be used as an electrode formation mask, and electrodes can be formed with good controllability.
以下本発明を図を用いて詳細に説明する。 The present invention will be explained in detail below using the drawings.
第1図は従来のシヨツトキ障壁型ゲート電極の
製造方法を説明するための図で、各主要工程にお
けるウエーハの断面図を示す。第1図aはn型
GaAs11(n=1×1017cm-3)表面に形成された
Al膜12を示す。第1図bは、該Al膜12上の
電極形成部分にCVF(Chemical Vapour
Deposition)法により形成した厚さ3000ÅのSiO2
膜13を示す。第1図cは該SiO2膜を電極形成
マスクとして前記Al膜12を電源電圧100V、電
流密度2mA・cm-2で陽極酸化しては形成された
酸化被膜を除去することを繰り返して除去した様
子を示す。第1図dは前記SiO2膜13下のAl膜
13の寸法をさらに短縮するために、該Al膜1
3の側面を陽極酸化しては除去することを繰り返
した様子を示す。このとき陽極酸化の電解液と接
触している前記n型半導体11表面も同時に陽極
酸化される。第1図eは前記SiO2膜13を除去
して得たAl電極を示す。この従来の製造方法に
よるシヨツトキ障壁型電極は化学エツチングによ
る従来の製造方法と比較してウエーハ全面にわた
つて均一で制御性が良いものが得られるが、n型
半導体表面の形状が変化する欠点があり、この欠
点を防止しようとすると電極の寸法を電極形成マ
スクの寸法以下に短縮することが不可能になる新
たな問題を生じた。 FIG. 1 is a diagram for explaining a conventional method of manufacturing a shot barrier type gate electrode, and shows cross-sectional views of a wafer in each main process. Figure 1 a is n type
Formed on the surface of GaAs11 (n=1×10 17 cm -3 )
The Al film 12 is shown. In FIG. 1b, CVF (Chemical Vapor
SiO 2 with a thickness of 3000 Å formed by
Membrane 13 is shown. Figure 1c shows that the Al film 12 was anodized using the SiO 2 film as an electrode formation mask at a power supply voltage of 100 V and a current density of 2 mA cm -2 , and the formed oxide film was removed by repeating the process. Show the situation. FIG. 1d shows that in order to further shorten the size of the Al film 13 under the SiO 2 film 13, the Al film 13 is
This shows how the sides of No. 3 were repeatedly anodized and removed. At this time, the surface of the n-type semiconductor 11 that is in contact with the electrolyte for anodic oxidation is also anodized at the same time. FIG. 1e shows an Al electrode obtained by removing the SiO 2 film 13. Compared to the conventional manufacturing method using chemical etching, the shot barrier type electrode produced by this conventional manufacturing method is more uniform and has better controllability over the entire wafer surface, but it has the disadvantage that the shape of the n-type semiconductor surface changes. However, if an attempt was made to prevent this drawback, a new problem occurred in that it was impossible to shorten the dimensions of the electrode to below the dimensions of the electrode forming mask.
第2図は本発明の第1の実施例を説明するため
の図で各主要工程におけるGaAsウエーハの断面
図を示す。 FIG. 2 is a diagram for explaining the first embodiment of the present invention, and shows cross-sectional views of a GaAs wafer in each main process.
第2図aはn型GaAs21(n=1×1017cm
-3)の全面にAl膜22を厚さ3000Åに被着した様
子を示す。 Figure 2a shows n-type GaAs21 (n=1×10 17 cm
-3 ) shows the state in which the Al film 22 is deposited to a thickness of 3000 Å on the entire surface.
第2図bは前記Al膜22表面にCVD法を用い
てSiO2膜を厚さ3000Å被着し、フオトレジスト
法により電極形成部分を除く該SiO2膜23をHF
系エツチング液で除去した様子を示す。 In Fig. 2b, a SiO 2 film with a thickness of 3000 Å is deposited on the surface of the Al film 22 using the CVD method, and the SiO 2 film 23 except for the electrode forming portion is coated with HF using the photoresist method.
This figure shows how it was removed using an etching solution.
第2図cは、該SiO2膜23を電極形成マスク
として、電源電圧15V、初期電流密度2mA・cm
-2の陽極酸化条件下、2.5%しゆう酸水溶液中で
Al膜22の酸化被膜の形成をおこなつては該酸
化被膜をCrC3、H3PO4およびH2OからなるAl2O3
液で化学エツチングして除去する工程で、まず前
記SiO2膜23直下の前記Al膜を除くn型GaAS上
のAl膜22が全て除去されるまで繰り返し行な
い、続いて該SiO2膜23直下の該Al膜22の側
面を陽極酸化しては形成された酸化被膜を除去す
ることを繰返し行なつてSiO2膜下のAl膜の寸法
を短縮した様子を示す。 FIG. 2c shows the SiO 2 film 23 used as an electrode formation mask at a power supply voltage of 15 V and an initial current density of 2 mA cm.
-2 in a 2.5% oxalic acid aqueous solution under anodizing conditions
When forming the oxide film of the Al film 22, the oxide film is made of Al 2 O 3 consisting of CrC 3 , H 3 PO 4 and H 2 O.
In the process of chemically etching and removing with a liquid, the process is first repeated until all of the Al film 22 on the n-type GaAS is removed except for the Al film directly below the SiO 2 film 23, and then the This figure shows how the dimension of the Al film under the SiO 2 film was shortened by repeatedly anodizing the side surface of the Al film 22 and removing the formed oxide film.
こゝでSiO2膜直下のAl膜の消耗深さは陽極酸
化による酸化被膜の電位降下の値から容易に計算
して求めることができるので、SiO2膜の寸法が
一定であるならば、Al電極の寸法を任意の値に
〓〓〓〓〓
制御できる。 Here, the depth of wear of the Al film directly under the SiO 2 film can be easily calculated from the value of the potential drop of the oxide film due to anodic oxidation, so if the dimensions of the SiO 2 film are constant, Set the electrode dimensions to any value〓〓〓〓〓
Can be controlled.
第2図dは前記SiO2膜23をHF系水溶液で除
去して得たAl電極24を示す。 FIG. 2d shows an Al electrode 24 obtained by removing the SiO 2 film 23 with an HF-based aqueous solution.
このように、本発明によれば、n型半導体を全
く酸化せずに、すなわちn型半導体表面の形状を
変化させずに電極を一様な形状に選択的に形成で
き、さらに電極形成マスクの寸法より小さな電極
をウエーハ全面にわたつて均一な寸法に制御性良
く形成できる。 As described above, according to the present invention, electrodes can be selectively formed in a uniform shape without oxidizing the n-type semiconductor at all, that is, without changing the shape of the surface of the n-type semiconductor, and furthermore, the electrode formation mask can be Electrodes smaller than the above dimensions can be formed with uniform dimensions over the entire surface of the wafer with good controllability.
第3図は本発明の第2の実施例を説明するため
の図で、各主要工程におけるGaAsウエーハの断
面図を示す。第3図の実施例は第2図と異なりn
型半導体表面の一部に該n型半導体導電層より電
子濃度の高いn+型半導体導電層が設けられてい
るようなウエーハである。 FIG. 3 is a diagram for explaining the second embodiment of the present invention, showing cross-sectional views of a GaAs wafer in each main process. The embodiment shown in FIG. 3 is different from that shown in FIG.
This is a wafer in which an n + -type semiconductor conductive layer having a higher electron concentration than the n - type semiconductor conductive layer is provided on a part of the surface of the n-type semiconductor conductive layer.
第3図aは、n型半導体31(n=1×1017cm
-3)の表面の一部に形成されたn型半導体導電層
(n=5×1017cm-3)および該n型半導体31の表
面全面に厚さ3000ÅのAl膜33を被着した様子
を示す。 Figure 3a shows an n-type semiconductor 31 (n=1×10 17 cm
-3 ) N-type semiconductor conductive layer (n=5×10 17 cm -3 ) formed on a part of the surface and an Al film 33 with a thickness of 3000 Å deposited on the entire surface of the n-type semiconductor 31. shows.
第3図bは電極形成部分の該Al膜33上に通
常のフオトレジスト法により厚さ3000ÅのSiO2
膜34を形成した様子を示す。 FIG. 3b shows SiO 2 with a thickness of 3000 Å formed on the Al film 33 in the electrode formation area using the usual photoresist method.
A state in which the film 34 is formed is shown.
第3図cは、該SiO2膜34を電極形成マスク
として電源電圧8V、電流密度2mA・cm-2で前
記Al膜33を陽極酸化としては形成された酸化
被膜を化学エツチングして除去することを繰り返
して除去し、さらに前記SiO2膜34直下のAl膜
33をも側面から除去して該Al膜33の寸法を
前記SiO2膜34以下に短縮した様子を示す。
こゝで陽極酸化の電源電圧はn+型半導体導電層
でのブレイクダウン電圧に電解液などでの電位降
下を加えた値以下に選んである。 FIG. 3c shows that the Al film 33 is anodized by using the SiO 2 film 34 as an electrode formation mask at a power supply voltage of 8 V and a current density of 2 mA·cm -2 to chemically etch and remove the formed oxide film. is repeatedly removed, and the Al film 33 immediately below the SiO 2 film 34 is also removed from the side, thereby reducing the dimension of the Al film 33 to be smaller than the SiO 2 film 34.
Here, the power supply voltage for anodic oxidation is selected to be less than the breakdown voltage in the n + -type semiconductor conductive layer plus the potential drop in the electrolyte, etc.
第3図dは、該SiO2膜を除去して得たシヨツ
トキ障壁型Al電極35を示す。このように本発
明によれば、n型半導体表面に該n型半導体と電
子濃度が異なるn型半導体導電層を形成したウエ
ーハにおいても、陽極酸化の電源電圧を、電子濃
度の大きいn型半導体のブレイクダウン電圧以下
にすることにより、n型半導体表面を全く変化せ
ずに、シヨツトキ障壁型電極をウエーハ全面にわ
たつて均一な方法に制御性良く形成できる。 FIG. 3d shows a shot barrier type Al electrode 35 obtained by removing the SiO 2 film. As described above, according to the present invention, even in a wafer in which an n-type semiconductor conductive layer having a different electron concentration from that of the n-type semiconductor is formed on the surface of the n-type semiconductor, the power supply voltage for anodization is changed to that of the n-type semiconductor having a higher electron concentration. By lowering the breakdown voltage to below the breakdown voltage, a shot barrier type electrode can be formed in a uniform manner over the entire wafer surface with good controllability without changing the n-type semiconductor surface at all.
第4図は本発明の第3の実施例を説明するため
の図で、各主要工程におけるGaAsウエーハの断
面図を示す。第4図の実施例は第2図とは異な
り、n型半導体表面の一部にP型半導体導電層が
形成されているようなウエーハである。 FIG. 4 is a diagram for explaining the third embodiment of the present invention, showing cross-sectional views of a GaAs wafer in each main process. The embodiment of FIG. 4 is different from that of FIG. 2 in that it is a wafer in which a P-type semiconductor conductive layer is formed on a part of the n-type semiconductor surface.
第4図aはn型半導体41(n=1×1017cm
-3)表面上の一部に形成されたP型半導体導電層
42表面上に通常のフオトレジスト法により厚さ
3000ÅのSiO2膜43を該P型半導体導電層42
を完全に被覆するように形成した様子を示す。 Figure 4a shows an n-type semiconductor 41 (n=1×10 17 cm
-3 ) The thickness of the P-type semiconductor conductive layer 42 formed on a part of the surface is
A 3000 Å SiO 2 film 43 is applied to the P-type semiconductor conductive layer 42.
This figure shows how it is formed so as to completely cover it.
第4図bは、該SiO2膜43と露出している前
記n型半導体41表面全面に形成した厚さ3000Å
のAl膜44を示す。 FIG. 4b shows a film with a thickness of 3000 Å formed on the entire surface of the SiO 2 film 43 and the exposed n-type semiconductor 41.
The Al film 44 of FIG.
第4図cは、前記n型半導体41表面上の該
Al膜44表面の電極形成部分に通常のフオトレ
ジスト法によりCVDによるSiO2膜45を3000Å
の厚さに形成した様子を示す。 FIG. 4c shows the difference on the surface of the n-type semiconductor 41.
A CVD SiO 2 film 45 with a thickness of 3000 Å is deposited on the electrode forming portion of the Al film 44 surface using the usual photoresist method.
The figure shows how it was formed to a thickness of .
第4図dは、該SiO2膜45を電極形成マスク
として電源電圧15V、電流密度2mA・cm-2で前
記Al膜を選択的に陽極酸化しては形成された酸
化被膜を化学エツチングで除去することを繰り返
して除去しさらに前記SiO2膜45直下のAl膜4
4をも該側面から同様に陽極酸化しては除去する
ことを繰り返して該Al膜44の寸法を短縮した
様子を示す。 FIG. 4d shows that the Al film is selectively anodized using the SiO 2 film 45 as an electrode formation mask at a power supply voltage of 15 V and a current density of 2 mA cm -2 , and the formed oxide film is removed by chemical etching. This process is repeated to remove the Al film 4 immediately below the SiO 2 film 45.
This figure shows how the size of the Al film 44 was shortened by repeating anodic oxidation and removal from the side surface of the Al film 44.
第4図eは、前記SiO2膜を除去して得たシヨ
ツトキ障壁型電極46を示す。このように本発明
によれば、n型半導体表面に形成されたP型半導
体導電層からなるウエーハにおいても、該P型半
導体導電層を絶縁層で被覆することにより第2図
の実施例と同様の効果を得ることができる。さら
に、第4図においては絶縁層で被覆する半導体導
電層をP型のものを用いて説明してきたが、該P
型半導体導電層を電子濃度が極めて高いn≧2×
1018cm-3のn+型半導体導電層に置換した場合であ
つても本発明の思想を適用できる。 FIG. 4e shows a shot barrier type electrode 46 obtained by removing the SiO 2 film. As described above, according to the present invention, even in a wafer consisting of a P-type semiconductor conductive layer formed on the surface of an N-type semiconductor, the P-type semiconductor conductive layer is covered with an insulating layer, so that the same method as in the embodiment shown in FIG. effect can be obtained. Furthermore, in FIG. 4, the semiconductor conductive layer covered with the insulating layer has been described using a P type semiconductor layer, but the P type
type semiconductor conductive layer with extremely high electron concentration n≧2×
The idea of the present invention can be applied even when replacing with an n + type semiconductor conductive layer of 10 18 cm −3 .
第5図は本発明の第4の実施例を説明するため
の図で、各主要工程におけるGaAsウエーハの断
面図を示す。第5図の実施例は第2図の実施例と
異なり、電極形成部分がリセス構造になつてい
る。 FIG. 5 is a diagram for explaining the fourth embodiment of the present invention, showing cross-sectional views of a GaAs wafer in each main process. The embodiment shown in FIG. 5 differs from the embodiment shown in FIG. 2 in that the electrode forming portion has a recessed structure.
第5図aはn型GaAs(n=1×1017cm-3)上
に、CVDによる第1のSiO2膜52をマスクとし
てリセスを形成した様子を示す。 FIG. 5a shows how a recess is formed on n-type GaAs (n=1×10 17 cm −3 ) using the first SiO 2 film 52 formed by CVD as a mask.
第5図bは該SiO2膜52と前記n型GaAsの表
面に厚さ3000ÅのAl膜53を形成した様子を示
〓〓〓〓〓
す。 FIG. 5b shows a state in which an Al film 53 with a thickness of 3000 Å is formed on the surface of the SiO 2 film 52 and the n-type GaAs.
vinegar.
第5図cは該Al膜53の全面にCVDにより
3000Åの厚さの第2のSiO2膜54を被着し、通
常のフオトレジスト法で該SiO2膜をリセス内に
該リセスの大きさ以下に選択的に残した様子を示
す。 FIG. 5c shows that the entire surface of the Al film 53 is coated by CVD.
A second SiO 2 film 54 with a thickness of 3000 Å is deposited, and the SiO 2 film is selectively left within the recess at a size below the recess using a conventional photoresist method.
第5図dは第2図cと同様に、前記第2の
SiO2膜54を電極形成マスクとして前記Al膜5
3を選択的に除去し、さらに該SiO2膜54直下
のAl膜53の寸法をも短縮した様子を示す。通
常、リセスの差部分のAl膜の厚さは他の部分よ
り薄いので陽極酸化の途中でリセス内のAl膜と
前記SiO2膜52(第1の)上のAl膜とが切断さ
れ、該SiO2膜上のAl膜が除去されずに残ること
があるが、このAl膜は次の工程で該SiO2膜とと
もに除去されてしまう。 FIG. 5 d shows, similar to FIG. 2 c, the second
The Al film 5 is formed using the SiO 2 film 54 as an electrode formation mask.
3 is selectively removed, and the dimension of the Al film 53 immediately below the SiO 2 film 54 is also shortened. Normally, the thickness of the Al film in the difference part of the recess is thinner than in other parts, so the Al film in the recess and the Al film on the SiO 2 film 52 (first) are cut during anodization, and the Al film on the SiO 2 film 52 (first) is cut. Although the Al film on the SiO 2 film may remain without being removed, this Al film will be removed together with the SiO 2 film in the next step.
第5図eは前記の第1および第2のSiO2膜を
全て除去して得たリセス構造におけるAl電極5
5を示す。このように本発明によればリセス構造
を有するn型半導体においてもn型半導体の表面
を変化させずに電極金属を一様な形状に選択的に
形成でき、さらに電極形成マスクの寸法より小さ
な電極をウエーハ全面にわたつて均一な寸法に制
御良く形成できる。 Figure 5e shows the Al electrode 5 in the recessed structure obtained by completely removing the first and second SiO 2 films.
5 is shown. As described above, according to the present invention, even in an n-type semiconductor having a recessed structure, electrode metal can be selectively formed into a uniform shape without changing the surface of the n-type semiconductor, and furthermore, the electrode metal can be formed in a uniform shape even in an n-type semiconductor having a recessed structure. can be formed with uniform dimensions over the entire wafer surface with good control.
第6図は本発明の第5の実施例を説明するため
の図で各主要工程におけるGaAsウエーハの断面
図を示す。第6図は第2図の実施例とは第2図b
以降の工程、特に陽極酸化のための電極形成マス
クの形成方法が異なる。 FIG. 6 is a diagram for explaining the fifth embodiment of the present invention, showing cross-sectional views of a GaAs wafer at each main step. Fig. 6 shows the embodiment of Fig. 2. Fig. 2b
The subsequent steps, especially the method of forming an electrode formation mask for anodic oxidation, are different.
以下の説明は第2図aと同じ工程の説明を簡略
にしておこなう。 The following explanation is a simplified explanation of the same process as in FIG. 2a.
第6図aはn型GaAs61(n=1×1017cm
-3)表面に4000Åの厚さにAl膜62を被着し、該
Al膜62表面に該Alの酸化被膜63を厚さ2000
Å形成した様子を示す。 Figure 6a shows n-type GaAs61 (n=1×10 17 cm
-3 ) An Al film 62 is deposited on the surface to a thickness of 4000 Å, and
The Al oxide film 63 is formed on the surface of the Al film 62 to a thickness of 2000 mm.
Å formation is shown.
第6図bは前記酸化被膜63上に電極形成部分
に形成したフオトレジスト膜(AZ1350、商標)
64を示す。 FIG. 6b shows a photoresist film (AZ1350, trademark) formed on the oxide film 63 at the electrode formation part.
64 is shown.
第6図cは、該フオトレジスト膜64を電極形
成マスクとして露出しているAl膜62を第2図
cと同様に電源電圧15V、初期電流密度2mA・
cm-2の陽極酸化条件下、2.5%しゆう酸水溶液中
でAl膜62の酸化被膜の形成を行なつては該酸
化被膜を化学エツチングして除去する工程で、ま
ず前記フオトレジスト膜64直下のAl膜62を
除くAl膜62が全て除去されるまで繰り返して
行ない、続いて該フオトレジスト膜64直下Al
膜62の側面を酸化しては形成された酸化被膜を
除去することを繰り返し行なつた様子を示す。 FIG. 6c shows the exposed Al film 62 using the photoresist film 64 as an electrode formation mask at a power supply voltage of 15V and an initial current density of 2mA, as in FIG. 2c.
In the step of forming an oxide film on the Al film 62 in a 2.5% oxalic acid aqueous solution under anodizing conditions of cm -2 and removing the oxide film by chemical etching, first, immediately below the photoresist film 64. This process is repeated until all of the Al film 62 except for the Al film 62 is removed, and then the Al film 62 directly under the photoresist film 64 is
This figure shows the process of repeatedly oxidizing the side surface of the film 62 and removing the formed oxide film.
第6図dは前記フオトレジスト膜64と2000Å
の前記Alの酸化被膜63を除去して得たAl電極
65を示す。このように本発明によれば、ゲート
金属表面に薄い酸化被膜を形成しておくことによ
り、取り扱いの簡単なフオトレジスト膜を電極金
属の陽極酸化のための電極形成マスクとして用い
ることができ、またn型半導体を全く酸化せずに
電極金属を一様な形状に選択的に形成でき、さら
に電極形成マスクの寸法より小さな電極をウエー
ハ全面にわたつて均一な寸法に制御性良く形成す
ることがきる。 FIG. 6d shows the photoresist film 64 with a thickness of 2000 Å.
An Al electrode 65 obtained by removing the Al oxide film 63 is shown. According to the present invention, by forming a thin oxide film on the gate metal surface, an easily handled photoresist film can be used as an electrode formation mask for anodic oxidation of the electrode metal. Electrode metal can be selectively formed into a uniform shape without oxidizing the n-type semiconductor at all, and electrodes smaller than the size of the electrode formation mask can be formed with uniform dimensions over the entire wafer with good controllability. .
上記の実施例を用いて説明したように従来の化
学エツチングを用いた電極の形成方法の欠点であ
つた電極形状の不均一性、および非制御性、さら
に従来の陽極酸化を用いて電極の形成方法の欠点
であつた半導体表面の酸化による形状変化など
は、本発明を用いることによつて全て解決され
る。また従来の化学エツチングでは、エツチング
液が均一に侵入しないために不可能であつた微細
な寸法のリセス構造内の電極形成の問題も、本発
明を用いると解決することができる。 As explained using the above example, the disadvantages of the conventional method of forming electrodes using chemical etching are the non-uniformity and uncontrollability of the electrode shape, and furthermore, the formation of electrodes using conventional anodic oxidation. The disadvantages of this method, such as shape change due to oxidation of the semiconductor surface, can all be solved by using the present invention. The present invention also solves the problem of forming electrodes in recess structures with minute dimensions, which was impossible with conventional chemical etching because the etching solution did not penetrate uniformly.
なお、本発明の実施例において電源電圧をシヨ
ツトキ接触のブレイクダウン電圧に電解液におけ
る電位降下分を加えた電圧より小さな値に選んで
説明している。また発明の実施例としてGaAsを
用いて説明してきたが、Si、GaP、InSbなどの他
の半導体材料を用いた半導体素子にも適用可能で
あることは言うまでもなく、さらに電極形成マス
クとしてCVD法によるSiO2膜とフオトレジスト
膜を用いて説明してきたが、電極金属または該電
極金属の酸化被膜と密着性の良い他の絶縁性材料
でも用いることができる。 In the embodiments of the present invention, the power supply voltage is selected to be a value smaller than the voltage obtained by adding the breakdown voltage of shot contact and the potential drop in the electrolytic solution. Although the invention has been explained using GaAs as an embodiment, it goes without saying that it is also applicable to semiconductor elements using other semiconductor materials such as Si, GaP, and InSb. Although the SiO 2 film and the photoresist film have been used in the explanation, other insulating materials that have good adhesion to the electrode metal or the oxide film of the electrode metal can also be used.
第1図a〜eは従来のシヨツトキ障壁型電極の
製造方法を説明するための図で、第2図a〜d、
第3図a〜d、第4図a〜e、第5図a〜e、第
6図a〜dはそれぞれこの発明の製造方法の第1
の実施例、第2の実施例、第3の実施例、第4の
実施例、第5の実施例を説明するための図で、そ
〓〓〓〓〓
れぞれ各主要工程におけるGaAsウエーハの断面
図を示す。
これらの図において、11,21,31,4
1,51および61はn型GaAs、32はn+型
GaAs導電層、12,22,33,44,53お
よび62はAl膜、63はAlの酸化被膜、13,
23,34,43,45,52および54は
SiO2膜、64はフオトレジスト膜、14,2
4,35,46,55および65はシヨツトキ障
壁型電極を示す。
〓〓〓〓〓
Figures 1a to 1e are diagrams for explaining a conventional method of manufacturing a shot barrier type electrode, and Figures 2a to d,
Figures 3 a to d, Figures 4 a to e, Figures 5 a to e, and Figures 6 a to d show the first manufacturing method of the present invention, respectively.
, the second example, the third example, the fourth example, and the fifth example.
A cross-sectional view of a GaAs wafer in each main process is shown. In these figures, 11, 21, 31, 4
1, 51 and 61 are n-type GaAs, 32 is n + type
GaAs conductive layer, 12, 22, 33, 44, 53 and 62 are Al films, 63 is Al oxide film, 13,
23, 34, 43, 45, 52 and 54 are
SiO 2 film, 64 is photoresist film, 14,2
4, 35, 46, 55 and 65 represent shot barrier type electrodes. 〓〓〓〓〓
Claims (1)
n型半導体とシヨツトキ接触する金属層を被着
し、該金属層表面の電極形成部分に絶縁被膜を被
着せしめ、陽極に印加される電圧が前記シヨツト
キ接触のブレイクダウン(break down)電圧以
下になるように前記絶縁被膜をマスクとして前記
金属層の陽極酸化と、形成された酸化被膜の除去
とを行つて該マスク下を除く前記n型半導体表面
の前記金属層を全て除去し、さらに該マスク下の
金属層の側面の陽極酸化と、形成された酸化被膜
の除去とをおこなつて該金属層の寸法を該マスク
の寸法以下に短縮し、次にマスクたる前記酸化被
膜を除去することを特徴とするシヨツトキ障壁型
電極の製造方法。 2 陽極酸化のための絶縁被膜の形成においてゲ
ート電極の表面に薄い酸化被膜を形成し、該酸化
被膜上のゲート電極形成部分にフオトレジスト膜
を形成し、該フオトレジスト膜を陽極酸化の絶縁
被膜とする特許請求の範囲第1項記載のシヨツト
キ障壁型電極の製造方法。[Scope of Claims] 1. A metal layer having a high oxidizing power and in direct contact with the n-type semiconductor is deposited on the surface of the n-type semiconductor, and an insulating coating is deposited on the electrode forming portion of the surface of the metal layer, Using the insulating film as a mask, the metal layer is anodized and the formed oxide film is removed so that the voltage applied to the anode is below the breakdown voltage of the shot contact. All of the metal layer on the n-type semiconductor surface except the bottom part is removed, and the side surface of the metal layer under the mask is anodized and the formed oxide film is removed to reduce the dimensions of the metal layer. A method for manufacturing a shot barrier type electrode, comprising shortening the electrode to a size smaller than that of a mask, and then removing the oxide film serving as a mask. 2. In forming an insulating film for anodic oxidation, a thin oxide film is formed on the surface of the gate electrode, a photoresist film is formed on the gate electrode formation portion on the oxide film, and the photoresist film is used as an insulating film for anodization. A method for manufacturing a shot barrier type electrode according to claim 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8850677A JPS5423375A (en) | 1977-07-22 | 1977-07-22 | Manufacture of schottky barrier type electrode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8850677A JPS5423375A (en) | 1977-07-22 | 1977-07-22 | Manufacture of schottky barrier type electrode |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5423375A JPS5423375A (en) | 1979-02-21 |
| JPS6131638B2 true JPS6131638B2 (en) | 1986-07-21 |
Family
ID=13944701
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8850677A Granted JPS5423375A (en) | 1977-07-22 | 1977-07-22 | Manufacture of schottky barrier type electrode |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5423375A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61103744A (en) * | 1984-10-25 | 1986-05-22 | Osaka Kiko Co Ltd | Tool exchanging device of machine tool |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4324259B2 (en) * | 1998-07-07 | 2009-09-02 | シャープ株式会社 | Manufacturing method of liquid crystal display device |
-
1977
- 1977-07-22 JP JP8850677A patent/JPS5423375A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61103744A (en) * | 1984-10-25 | 1986-05-22 | Osaka Kiko Co Ltd | Tool exchanging device of machine tool |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5423375A (en) | 1979-02-21 |
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