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JPS6131883B2 - - Google Patents
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JPS6131883B2 - - Google Patents

Info

Publication number
JPS6131883B2
JPS6131883B2 JP53140109A JP14010978A JPS6131883B2 JP S6131883 B2 JPS6131883 B2 JP S6131883B2 JP 53140109 A JP53140109 A JP 53140109A JP 14010978 A JP14010978 A JP 14010978A JP S6131883 B2 JPS6131883 B2 JP S6131883B2
Authority
JP
Japan
Prior art keywords
printed
printing
input
key
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP53140109A
Other languages
Japanese (ja)
Other versions
JPS5566020A (en
Inventor
Ichiro Sado
Shigeharu Kishimoto
Mitsuo Cho
Masayuki Sasaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP14010978A priority Critical patent/JPS5566020A/en
Priority to US06/087,706 priority patent/US4344147A/en
Publication of JPS5566020A publication Critical patent/JPS5566020A/en
Publication of JPS6131883B2 publication Critical patent/JPS6131883B2/ja
Granted legal-status Critical Current

Links

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  • Calculators And Similar Devices (AREA)
  • Input From Keyboards Or The Like (AREA)

Description

【発明の詳細な説明】 本発明は算式通りのキー操作で見易い印字結果
を得る事を目的とする。
DETAILED DESCRIPTION OF THE INVENTION An object of the present invention is to obtain easy-to-read printing results by operating keys according to formulas.

従来は、数字入力に続く命令キーで、同一行に
数字とマークを印字していた。しかしながら算式
通りにキーを操作して3−2=1を求める様な場
合同一行に3−が印字されるとあたかもマイナス
3の様に見え、従来の加算器方式との区別が明確
でなくなる。又、通常、義務教育で学習する書き
方とも異なる。
Previously, numbers and marks were printed on the same line by pressing the command key after entering numbers. However, if 3-2=1 is calculated by operating the keys according to the formula, if 3- is printed on the same line, it will look like minus 3, making it difficult to distinguish it from the conventional adder system. It is also different from the writing style that is normally learned in compulsory education.

本発明は上記の点に鑑み成されたもので以下図
面に従い説明を加える。
The present invention has been made in view of the above points, and will be explained below with reference to the drawings.

第1図は3−2=のキー操作時の印字フオーマ
ツト例である。Aはマイナスシンボルを全桁に打
ち、見易くしたものであり、Bは=マークを印字
して同一行に演算結果を印字したものである。
FIG. 1 shows an example of the print format when the 3-2= key is operated. In A, minus symbols are printed in all digits to make it easier to read, and in B, an = mark is printed and the calculation result is printed on the same line.

第2図は本発明ブロツク図である。 FIG. 2 is a block diagram of the present invention.

図中 INPは数字キー、小数点キー等の押下を
検知し2進化符号に変換するデコーダー、フリツ
プフロツプブロツク等で構成される入力部、Mは
入力数字格納レジスタ、I1,I2,I3,I
4,I5は各々+,−,×,÷,=キー押下を検知し
一定のパルスを発生する演算キー信号発生部、F
1,F2,F3,F4,F5はM内容が印字され
るに充分な時間、各入力信号を遅らせる第一の遅
延回路群、F6,F7,F8,F9,F10はプ
リンターが改行に要する時間以上、各入力信号を
遅らせる第二の遅延回路群、OR1はI1〜I5
のどれかに出力がある場合1信号を出力するオア
ゲート、G1は前述のCR1出力が1の時M内容を
数字印字回路に導く為のアンドゲート、OR2は
F1〜F5出力のどれかが1の時改行命令をプリ
ンターに与える為のオアゲートである。
In the figure, INP is an input unit consisting of a decoder that detects the press of a number key, decimal point key, etc. and converts it into a binary code, a flip-flop block, etc., M is an input number storage register, I1, I2, I3, I
4, I5 are arithmetic key signal generators that detect presses of the +, -, ×, ÷, and = keys and generate constant pulses, F
1, F2, F3, F4, and F5 are the first delay circuit group that delays each input signal for a time sufficient for the M content to be printed, and F6, F7, F8, F9, and F10 are longer than the time required for the printer to perform a line feed. , a second delay circuit group that delays each input signal, OR1 is I1 to I5
An OR gate that outputs a 1 signal if any of the outputs has an output, G1 is an AND gate that guides the M content to the number printing circuit when the CR1 output is 1, and OR2 is an AND gate that outputs a 1 signal if any of the F1 to F5 outputs is 1. This is an OR gate for giving a line feed command to the printer when .

又、図には示していないCPUはI5出力を受
け、演算結果を数字印字回路に導くものである。
Further, the CPU, which is not shown in the figure, receives the I5 output and leads the calculation result to the numeric printing circuit.

第2,3図、第4図Aから明らかなように、数
字3のMへの入力に続く演算キー□−の入力でI
2,OR1,G1の作動によりM内の数年3が印
字され、その後F2,OR2により改行が行なわ
れ、1行改行後に負の演算マーク印字信号F7が
プリンター駆動回路に与えられ左端に一記号を印
字する。
As is clear from Figures 2, 3, and 4A, by inputting the calculation key □- following the input of the number 3 to M, I
By the operation of 2, OR1, and G1, the number 3 in M is printed, and then a line feed is performed by F2, OR2, and after one line feed, a negative operation mark print signal F7 is given to the printer drive circuit, and one symbol is printed at the left end. Print.

以下数字2がMに入力され、□=キーのとき数字
2が−記号と同一行に、=記号と結果1が次行に
印字される。
Thereafter, the number 2 is input to M, and when the □= key is pressed, the number 2 is printed on the same line as the - symbol, and the = symbol and result 1 are printed on the next line.

以上の説明の如く、本方式は、従来の表示用演
算回路と印字駆動回路に第2図の様な回路を加え
ればよい事になり、容易に実現できる。第4図B
は従来の印字方法であり、本発明の方法がより見
易いことは明らかである。又、第1図Aのような
印字もI5出力をCPUで検知しマイナスを全桁
に打つて、然る後改行し結果を印字すればよい。
また演算子マークを左側に印字することは活字ド
ラムのマーク活字の位置を変えればよい。
As explained above, this system can be easily realized by adding a circuit as shown in FIG. 2 to the conventional display arithmetic circuit and print drive circuit. Figure 4B
is a conventional printing method, and it is clear that the method of the present invention is easier to see. Also, printing as shown in Figure 1A can be done by detecting the I5 output with the CPU, typing minus signs in all digits, then starting a new line and printing the result.
Also, printing the operator mark on the left side can be done by changing the position of the mark type on the type drum.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の印字例を示す図、第2図はそ
のブロツク図、第3図はそのタイミング図、第4
図Aは本発明印字順序を示す図、同B図は従来の
印字順序を示す図である。 M……レジスタ、G1……アンドゲート、OR
1,OR2……オアゲート、F1〜F10……遅
延回路。
Fig. 1 is a diagram showing a printing example of the present invention, Fig. 2 is a block diagram thereof, Fig. 3 is a timing diagram thereof, and Fig. 4 is a diagram showing a printing example of the present invention.
Figure A is a diagram showing the printing order of the present invention, and Figure B is a diagram showing the conventional printing order. M...Register, G1...And gate, OR
1, OR2...OR gate, F1-F10...delay circuit.

Claims (1)

【特許請求の範囲】[Claims] 1 印字式卓上計算機において、数字キー入力に
続く四則キーの1つの入力を検知し、入力した数
字を紙の右側に印字後改行して四則マークの1つ
をの左側に印字する事を特徴とする印字方式。
1 A print-type desktop calculator that detects the input of one of the four arithmetic keys following the number key input, prints the input number on the right side of the paper, then breaks a line and prints one of the four arithmetic marks on the left side. printing method.
JP14010978A 1978-11-10 1978-11-14 Printing system Granted JPS5566020A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP14010978A JPS5566020A (en) 1978-11-14 1978-11-14 Printing system
US06/087,706 US4344147A (en) 1978-11-10 1979-10-24 Electronic calculator with printer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14010978A JPS5566020A (en) 1978-11-14 1978-11-14 Printing system

Publications (2)

Publication Number Publication Date
JPS5566020A JPS5566020A (en) 1980-05-19
JPS6131883B2 true JPS6131883B2 (en) 1986-07-23

Family

ID=15261130

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14010978A Granted JPS5566020A (en) 1978-11-10 1978-11-14 Printing system

Country Status (1)

Country Link
JP (1) JPS5566020A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5759291A (en) * 1980-09-27 1982-04-09 Sharp Corp Printer type computer

Also Published As

Publication number Publication date
JPS5566020A (en) 1980-05-19

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