JPS6131901B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to diagnosis of a memory device, and particularly to diagnosis of address system of memory.

Conventionally, in diagnosing memory devices, a method has been used in which a specific pattern is written in a memory element and then read out. Therefore, if the read data is different from the written data, it is possible to determine whether the failure is due to a defective memory element or not.
Another drawback was that it was difficult to distinguish whether the problem was due to a defect in the memory drive circuit or not.

The present invention has been made in order to eliminate the above-mentioned drawbacks of the conventional technology, and an object of the present invention is to store address information or a part of the address information in the memory when accessing outside the memory mounting area when diagnosing a memory device. It is an object of the present invention to provide a new memory diagnostic method that facilitates diagnosis of memory address system by outputting the data.

The above object of the present invention is to provide a diagnostic method for a memory device, which includes: means for detecting an unimplemented address of a memory out of the entire address space of a memory; means for setting a memory device in a diagnostic mode; This is achieved by a memory diagnostic method characterized by comprising means for outputting address information or a part of the address information to the memory when an address on which the memory is not mounted is accessed while the memory is in the memory mode. Ru.

Next, a preferred embodiment of the present invention will be specifically explained with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. In the figure, reference number 1 indicates a memory drive circuit 2, a memory, 3 an address selection circuit constituted by, for example, a gate circuit, 4 an address detection circuit constituted by, for example, a decoder, an OR circuit, etc.;
Reference numeral 1 indicates a diagnosis instruction signal, 12 an address signal, 13 an address detection signal, and 14 a memory output.

An address signal 12 from a memory drive circuit 1 in the memory device is supplied to the memory 2, and only the contents of the memory designated by this address signal 12 and selected appear at the output 14 during normal operation.
During normal operation, accessing address spaces that are not implemented in memory is prohibited.
If accessed, a memory parity error or an interrupt signal (not shown) is generated to the host device.

Diagnosis instruction signal 11 for diagnosis from memory drive circuit 1
According to the instruction, when an address where no memory is mounted is accessed, the address detection signal 13 which is the output of the address detection circuit 4 becomes logic "1", and address information is output to the address selection circuit 3. Instruct. Address selection circuit 3
Then, all or part of the address information is output to the memory output 14 with the data widths aligned. If you access the address space where memory is implemented, you can access the memory normally.

Therefore, when diagnosing memory, for example,
If memory is installed in areas (a) and (c) in Figure 2, but not in area (b), then
The address area in (a) is accessed normally,
At this time, the contents of the memory 2 are outputted to the output 14. Next, when accessing the area (b), address information will appear, so by comparing the output, it is possible to determine whether or not the target address has been accessed to the memory. If different address information is output from the output 14, it can be determined that the memory drive circuit 1 has failed. As a result, it becomes easy to distinguish between a defective memory element and a defective memory drive circuit.

Although not shown in the figure, the address selection circuit 3 is designed to use part or all of the address to enlarge or reduce the data length to be output.

Furthermore, even in areas where memory is mounted, as shown in Figure 1, by outputting the address detection signal 13 to the memory 2, memory output is prohibited in the diagnostic mode, and the memory is treated as if it were a memory. It is also possible to easily implement a configuration in which the address is not implemented and the address is output instead.

As explained above, the present invention is capable of detecting memory defects and memory drive by configuring address information to be output from the memory when an address space in which no memory is mounted is accessed in the diagnosis mode of the memory device. This has the effect that circuit defects can be easily isolated.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention;
FIG. 2 is a diagram showing an example of a memory address space. DESCRIPTION OF SYMBOLS 1...Memory drive circuit, 2...Memory, 3...Address selection circuit, 4...Address detection circuit, 11...Diagnosis instruction signal, 12...Address signal, 13...Address detection signal, 14...Memory output, (a)...Memory implementation Address space, (b)...memory non-implemented address space, (c)
...Memory implementation address space.

Claims (1)

[Claims] 1. A diagnostic method for a memory device, comprising: means for detecting addresses where no memory is implemented in the entire address space of the memory; means for setting the memory device in a diagnostic mode; A memory diagnostic method characterized by comprising: means for outputting an address or a part of an address to a memory when accessing an address in which the address is not implemented.