JPS6132743B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for recording the amount of displacement, such as the traveling speed of an automobile, using a magnetic tape.

Traditionally, devices for recording the running distance of a car include pen-type recording devices and devices that record the speed of the car.
There are recording devices that use magnetic tape to write FM-modulated sine wave signals.

However, in the case of the above-mentioned pen-writing type recording device, since the recording paper is used, the recording paper can only be used once, and there is a drawback that the maintenance cost of the recording device is high. The recording accuracy is limited by physical constraints such as the thickness of the
There is a drawback that the accuracy of the data on the traveling speed within a short period of time is reduced. Furthermore, since it is a mechanical recording method, it is susceptible to vibrations and is extremely inconvenient as a vehicle-mounted recording device. Furthermore, it has been impossible to record with high accuracy the driving conditions immediately before a traffic accident, traffic violation, etc. In addition, all analysis and processing of the data recorded on the recording paper is carried out by specialized personnel.
Moreover, it had the disadvantage that it had to be done over a long period of time.

In addition, in the case of recording methods using magnetic tape, conventional methods record continuous analog signals, so high recording accuracy can be achieved, but the disadvantage is that the recording time is limited by the tape length. It was hot.

Another method of recording speed using a conventional magnetic tape, as described in Japanese Patent Publication No. 45-24556, uses a magnetic tape that rotates in proportion to the vehicle speed, and attaches a magnetic recording head to this magnetic tape. There is a magnetic recording method in which a reference frequency signal is added to the magnetic tape via a Therefore, when the vehicle speed is low, the rotational speed of the magnetic tape becomes low, which has the disadvantage that the recording density of the reference frequency signal on the magnetic tape becomes too dense and cannot be reproduced. Since the rotation speed of the tape increases, the recording density of reference frequency signals on the magnetic tape becomes too sparse, resulting in a decrease in recording accuracy.

In addition, this method has the disadvantage that since the reference frequency signal is recorded on an endless magnetic tape, only data for a fixed running distance is always recorded.

The present invention aims to solve the above-mentioned drawbacks of the conventional recording method.The present invention samples detected values such as the traveling speed of a car at predetermined sampling intervals, detects the detected values at each time, and stores the detected values in a register. By recording the displacement amount at each sampling time by comparing and calculating with the detected value detected in the next sampling, and recording the detected displacement amount on the magnetic tape recording device via the encoding circuit. , it is possible to record the detected value uniformly and with high precision regardless of the size of the detected value, and since the amount of displacement is detected and recorded, the bits required are smaller than when the detected value is recorded raw. The purpose of this invention is to provide a displacement recording method that reduces the number of magnetic tapes, improves the efficiency of using magnetic tape, and allows long-time recording.

The present invention will be described below with reference to embodiments shown in the drawings. In Fig. 1, numeral 1 is a vehicle speed sensor for also detecting the vehicle speed, which is a detected value, and as shown in Fig. 2, it is equally distributed on the shaft 1C, which rotates at a rotation speed proportional to the rotation of the axle. Permanent magnet 1A placed in
and a reed switch 1B which turns on and off repeatedly as the permanent magnet 1A approaches.
Generates a number of pulses proportional to the speed of the car.

Reference numeral 2 denotes a sampling gate circuit, which is composed of a resistor 2A, an inverter 2B, and a NAND circuit 2C. Then, a gate signal shown in FIG. 3a is sent from the control circuit 10 to be described later from the terminal 2b.
It is added to one input of the NAND circuit 2C. On the other hand, the vehicle speed signal shown in FIG. 3b from the vehicle speed sensor 1 is applied to the terminal 2a, and the resistor 2A and inverter 2B
As a result, an inverted vehicle speed signal is applied to one input of the NAND circuit 2C. Therefore, at time _t1 when the gate signal is at the "1" level within the period T shown in FIG. Also, at time _t2 when the gate signal is at the "0" level, the output of the NAND circuit 2C is maintained at the "1" level.

Then, counter 3 calculates time t ₁ within period T.
The number of pulses of the vehicle speed signal passing through the gate circuit 2 every (1 sec) is counted, and this counted value is vehicle speed data.

For example, in a vehicle speed sensor 1 that generates four pulses per revolution and rotates at a rotation speed of 637 [rpm], which is the same as the rotation speed of the axle, when the vehicle speed is 60.7 [Km/h], t If 43 pulses are counted in a time of ₁ = 1 [sec], this value is the vehicle speed 60.7
Since it corresponds to [Km/h], the count value 43 of counter 3 becomes vehicle speed data. After calculation and processing, this vehicle speed data is stored in the primary storage shift register 8, which will be described later.
After being held for t ₃ ), a pulse signal for clearing the counter 3 is applied from the control circuit 10 shown in FIG. 3 c at T ₉ shown in FIG. 3, just before the next sampling starts. It will be cleared. 4 is a register, which transfers the vehicle speed data held in the counter 3 after one sampling is completed to this register 4 at the timing T3 shown in Fig. _3e , and holds it during calculation and processing. It is. 5 is a similar register, and counter 3
Immediately before the vehicle speed data is transferred to register 4, the contents of register 4 are transferred to register 5 by a pulse at timing T2 shown in _FIG .
Similarly, it is held during arithmetic processing. Both register 4 and register 5 use 8-bit shift registers with parallel input and parallel output.

6 is an arithmetic circuit, which includes register 4 and register 5.
When the data held in is input and _the control signal shown in _FIG . In the meantime, the result of subtracting the contents of register 5 from the contents of register 4 is output together with the sign.

For example, the contents of register 5 are the vehicle speed 60.7.
Holding the count number 43 corresponding to [Km/h], 8
Bit binary high signal [0, 0, 1, 0, 1,
0, 1, 1], and the contents of register 4 are the vehicle speed.
The count number 41 corresponding to 57.9 [Km/h] is held and the binary signal is [0, 0, 1, 0, 1, 0, 0,
1], the output of the arithmetic circuit 6 is a binary signal [0, 0, 0] with a sign bit "0" representing a minus sign added to the beginning to represent -2 in decimal as the result of subtraction. ,0,0,0,0,
1, 0] outputs a 9-bit signal.

Also, if the number to be subtracted is smaller, that is, if the vehicle speed stored in register 4 is larger, a sign bit "1" indicating a plus is added to the sign bit, and for example, the contents of register 4 are The number of counts is 46, which corresponds to a vehicle speed of 64.3 [Km/h], and the binary signal is [0, 0, 1, 0, 1, 1, 1,
0] and the contents of register 5 are the count number as well.
43, [0, 0, 1, 0, 1, 0, 1, 1], the operation result is +3 in decimal, and the sign bit "1" representing plus in binary is added [1, 0 ,
0, 0, 0, 0, 0, 1, 1] is output.

Reference numeral 7 denotes a viewing device that checks the output of the arithmetic circuit 6 and reconfigures it so that the bit structure of the data is minimized for recording, and also adds a header bit to the beginning of each data to indicate data division. After that, the data is output serially to a shift register 8 for primary storage, which will be described later, and the shift register 8 for primary storage is By detecting just before and when the data is filled and outputting a detection signal to the control circuit 10, the timing for data transfer and recording from the control circuit 10 to the magnetic tape recording device 12, which will be described later, is generated. It has a visual function to make things easier. FIG. 4 is an electric circuit diagram showing the detailed configuration of this viewing device, and 7A is a check circuit for checking the number of bits of data to be stored, and 7A of R1 to R7 is a check circuit for checking the number of bits of data to be stored.
Consists of OR circuits. Here, the least significant bit is input to the OR circuit _R1 , and the other OR circuits _R2 , _R3 ......
High-order digits are input into _R7 in sequence.

Now, suppose the vehicle speed data output from the arithmetic circuit 6 is +5 in decimal and [1, 0, 0, 0, 0, 0, 1, 0, 1] is the input terminal in natural binary numbers including the plus sign. When input to nine input terminals _{sequentially from 7a to input terminal 7j at time T4 shown in Figure 3 ,} the output of the OR circuit of R2 _{and R1} below R3 becomes "1"; The outputs of ₄ to _R7 become "0" and are input to one input terminal of the NAND circuits _N1 to _N7 , respectively.

The 8th bit, which is the highest digit of the vehicle speed data, is input from the input terminal 7b and is directly sent to the NAND circuit _N8.
is input to one of the input terminals. Also, the third
When the timing pulse shown in FIG. 5a synchronized with T ₄ shown in the figure is applied from the input terminal 7p, nine pulses are applied to the viewing device 7 later at timing T ₅ as shown in FIG. 5b. Control circuit 7 inside
From F to inverter N ₀ and 8 NAND circuits N ₁ ~
NAND circuit _N9 outputs _a number equal to the number of digits below the highest digit containing "1" in the vehicle speed data plus 1 "0". A pulse that reaches the level is output. That is, the number of output pulses from the NAND circuit _N9 corresponds to the number of data output from the multiplexer 7E, and this data refers to the highest number of vehicle speed data in which "1" exists in one bit of the code. It is a few bits lower than the digit. Therefore, one extra pulse is unconditionally required for the sign bit.
A pulse is output from the NAND circuit _N9 , and this is stored in the counter 7C as the number of data. Then, the binary counter 7C counts the number of pulses and outputs the counting results from the output terminals of A ₂ , B ₂ , C ₂ , and D ₂ . ) Input to one of the input terminals of E ₁ to _{E 4} .

Next, when the control circuit 7F inputs the nine pulses shown in FIG.
Output in binary to terminals A ₁ to D ₁ . This counter 7D operates at the rising edge of the input pulse, so the address designation of the multiplexer 7E that receives signals from terminals _A1 to _D1 changes in synchronization with the rising edge of the above pulse, and the address corresponding to that address is changed in synchronization with the rising edge of the pulse. The inputs I ₀ to I ₈ are sequentially output from the terminal OT.

Counter 7C has a NAND circuit N ₉ in advance.
The number of pulses from the multiplexer 7E, that is, the number of data desired to be output from the multiplexer 7E is stored. Counter 7D is actually multiplexer 7
It stores the number of data output from counter E, and when the values of both counters 7C and 7D become equal, it indicates that the number of data to be output is equal to the number of output data. Whether these values are equal can be determined by the exclusive OR circuits _E1 to _E4 . In other words, the exclusive OR circuit outputs "0" when its two inputs are equal, and when all four sets of two inputs are equal, the outputs of the exclusive OR circuits E ₁ to _{E 4} are all "0", and the set input S of the flip-flop 7H is changed to "1" or "0" according to the logical sum of the determination results. Therefore, when the data numbers of the two counters 7C and 7D are not equal, "1" is assigned to the flip-flop 7H, and when the data numbers become equal, "0" is assigned to the flip-flop 7H. 7H is inverted. When this inverted signal is applied to the control circuit 7F, application of the pulse signal to the counter 7D is stopped.

As explained above, by detecting the number of data to be sequentially output from the multiplexer 7E and the number of data actually output, including the sign bit, by the flip-flop 7H, the pulse train signal ( By stopping the output (shown in FIG. 5e), the output of data is stopped. As a result, the values below the sign bit plus the highest order are sequentially output from the output terminal OT of the multiplexer 7E, and further output from the output terminals 7k and _7m via the NAND circuits _N10 and N11.

Here, the two NAND circuits N ₁₀ and N ₁₁ constitute a header circuit for inserting header bits to distinguish each data when storing it in a shift register for primary recording, which will be described later. Yes, multiplexer 7 as shown in Figure 5c.
NAND circuit 1 before the vehicle speed data is output from E.
By setting the inputs of 0 and 11 to "0" at the timing of _T6 , "1" is output to both output terminals 7k and 7m.

The shift registers 8A and 8B receive and store the output signals from the output terminals 7k and 7m, respectively, in response to the pulses shown in FIG. 5d. At this time, by masking the NAND circuits N ₁₀ and N ₁₁ by the signal shown in Fig. 5c at the timing of the first 1 bit in Fig. 5d, the outputs of the output terminals 7k and 7m are forced to " 1”, and as a result both registers 8
"1" is stored in A and 8B at the same time. These are used as header bits to divide data.

NAND circuit except when writing header bits
One of the input terminals of N ₁₀ and N ₁₁ is always held at "1" and its gate is open, so the output from multiplexer 7E passes through output terminals 7m to 7k as is. This means that positive vehicle speed data and inverted data are output.

Reference numeral 8 denotes a large-capacity register as an IC memory for temporary storage, and in this embodiment, two shift registers of 1024-bit complementary MOS IC are used.

Each shift register 8 has a viewing device 7.
The vehicle speed data from the output terminals 7m and 7k checked and reconfigured into the shortest number of bits and their inverted data are temporarily stored. Here, if the normal data is phase "1" (positive pulse logic) and the inverted data is phase "0" (negative pulse logic), the corresponding bits of both shift registers are the same except for the header bit. It will never become
Data is distinguished only by the fact that both header bits are "1".

Figures 5h and 5i show the waveforms of the shift register 8 when the phase is "1" and the phase is "0". 1, 1, 0, 0,
1, 1] Phase “0” is [1, 1, 0, 1,
0, 0, 1, 1, 0, 0], and these values are stored in the two shift registers 8.

Further, the clock signal for the shift register 8 is a 10 pulse signal shown in FIG.
It is synchronized with the read clock from multiplexer 7E shown in FIG.

9 is an encoding circuit that converts vehicle speed data into a code for recording on a magnetic tape. Here, in this embodiment, the NRZI recording system is used as the recording encoding system, and the reversal of the magnetic flux is recorded when the data bit is "1".

Reference numeral 10 denotes a control circuit, which sends control timing signals to each part of the device. and,
3 and 7 show control signals from the control circuit 10, FIG. 3a and FIG. 7c are gate signals applied to the gate circuit 2, and FIG. 3d
is the transfer signal applied to counter 5, Fig. 3e
is the transfer signal applied to counter 4, FIG.
7a shows a trigger signal applied to the arithmetic circuit 6 and the input terminal 7p of the viewing circuit 7.
3c and 7b are clearing pulse signals applied to the counter 3.

Further, FIG. 7d shows 1024 readout clock signals applied to the shift register 8 for temporary storage, and simultaneously applied to the encoding circuit 9 as clock signals for encoding.

Fig. 7e shows a control signal for driving the motor of the magnetic tape recording device 12 which is at a high level for time _t6 , and Fig.7f shows a solenoid control signal for magnetic tape feeding which becomes a high level for a time _t7 at _T10 . This signal is sent from the control circuit 10 to each part as a control signal.

11 is a power supply circuit for supplying voltage to each part of the device.

Reference numeral 12 denotes a magnetic tape recording device, which is a generally known data recorder that has a capstan motor and a pinch roller, and can intermittently run the tape by bringing the capstan and the pinch roller into contact with each other using a solenoid. It is.

Next, the operation of the system of the present invention in the above configuration will be explained. Now, when the car starts running, the permanent magnet 1A of the vehicle speed sensor 1 rotates in the direction of the arrow in FIG. 2 at the same number of rotations as the axle. reed switch 1
B is normally open, but the permanent magnet 1A
When the permanent magnet 1A approaches, it becomes a closed state, and as the permanent magnet 1A further rotates, it changes to an open state.

Here, as shown in FIG. 2, one end of the reed switch 1B is grounded, and the other end is connected to the gate circuit 2.
Further, this input terminal 2a reaches a power supply terminal 2e through a resistor 2A inside the gate circuit 2, and a voltage of +5V is constantly applied to this power supply terminal 2e.

Therefore, when the reed switch 1B turns on and off, the input terminal 2a of the gate circuit 2 moves up and down at a level between ground and +5V, and as a result, a number of pulses proportional to the speed of the car are output from the speed sensor 1. It will be output. Here, as described above, the generally known vehicle speed sensor 1 generates four pulses every time the axle rotates once.

This pulse signal is applied to the gate circuit 2, and the gate circuit 2 inputs the pulse signal to the counter 3 for a sampling time _t1 . The counter 3 obtains vehicle speed data by counting the number of pulses input at sampling time _t1 .

Now, consider the case where the vehicle speed changes according to FIG. 6V.

The time from T ₀ to T ₁ is the time indicated by t ₁ in Fig. 3a, and at time T ₁ , the count value n ₁ of the number of pulses corresponding to the vehicle speed V ₁ shown in Fig. 6 is displayed on the counter 3. will be held.

Next, the contents of register 4 are transferred to register 5 at timing T2 shown in _FIG .

In this case, since the vehicle speed starts from zero and all circuits are initially cleared, the contents of register 4 are all zeros.
Since this all-zero value is further transferred to register 5, this register 5 is still held at all zeros with n ₀ =0.

Next, the contents _n1 of the counter 3 are transferred to the register 4 at timing _T3 shown in FIG. Here, the timing of each transfer is determined by the timing pulses 3d and 3d applied from the control circuit 10.
Controlled by figure e. Then, in a state where the contents of registers 4 and 5 hold the sampling data for two times, the control signal shown in FIG. 3 f is applied from the control circuit 10 to the arithmetic circuit 6 at timing T ₄ shown in FIG. 3. Then, the arithmetic circuit 6 subtracts the contents of the register 5 from the contents of the register 4, adds a sign bit, and outputs the result as a 9-bit parallel signal. Now, vehicle speed sensor 1 is 637 [revolutions/revolutions] at 60 [Km/h].
When using a _generally known vehicle speed sensor such as
In this case, if V ₁ =4.2 [Km/h], the output n ₁ of the counter 3 will display 3. If we express this in natural binary numbers [0, 0,
0, 0, 0, 0, 1, 1]. Furthermore, the content zero of register 5 is [0, 0, 0, 0, 0,
0, 0, 0]. Therefore, in the arithmetic circuit, the result of subtracting the contents of register 5 from the contents of register 4 is +3 in decimal notation, and a sign bit "1" representing plus is applied to the beginning of the natural binary number [1, 0, 0, 0, 0, 0, 0, 1, 1] is output.

Then, at time 2T ₁ shown in FIG. 6, the vehicle speed V ₂ is output as the count output n ₂ of the counter 3, and the difference in vehicle speed at this time, V ₂ -V ₁ , that is, the count value n ₂ - n ₁ is output to the arithmetic circuit. It is output from 6.

Similarly, at each sampling timing 3T ₁ , 4T ₁ . . . shown in FIG. 6, vehicle speeds V ₃ , _{V 4} . ₂ ), (V ₄ − V ₃ )... are output sequentially.

In particular, during the period from 4T ₁ to 8T ₁ shown in FIG. 6, there is no change in the vehicle speed and the constant value V ₄ is maintained, so the speed difference is zero, and the output of the arithmetic circuit 6 in this case is The sign bit represents plus, and the data is all zeros, that is, [1, 0, 0, 0, 0,
0, 0, 0, 0] is output. The nine outputs of the arithmetic circuit 6 are connected to input terminals 7a to 7j of the viewing device 7 in sequence from higher order digits to lower order digits, with the sign bit first. The check circuit 7A of the viewing device 7 checks the data excluding the sign bit, and outputs "1" in all cases below the highest level of the "1" signal.

For example, if "1" is input to the input terminal 7b, that is, the data is +128, and the binary number including the sign bit is [1, 1, 0, 0, 0, 0,
0, 0, 0], N ₁ to N ₈
All input terminals from the check circuit 7A to the NAND circuit become "1". Then, from the internal control circuit 7F, nine pulses shown in FIG.
Nine positive pulses are output from the NAND circuit _N9 by being sequentially applied to the NAND circuits _N1 to _N8 and the inverter _N0 , and the binary counter 7
It is counted by C.

Also, as in the previous example, the vehicle speed data is +3 in decimal
In the case of , the binary number is [1, 0, 0, 0, 0,
0, 0, 1, 1], and since the inputs 7j and 7i of the OR circuits R ₁ and R ₂ are both "1", the outputs of both the OR circuits R ₁ and R ₂ are also "1". . At this time, the outputs of circuits R ₃ to _{R 7} are “0” and NAND
Three pulses are output from the circuit _N9 , and the counter 7C counts 3, and the [A ₂ , B ₂ , C ₂ ,
Outputs [1, 1, 0, 0] from the lower order digit to the D ₂ ] terminal. The relationship between the input and output of a binary counter is generally defined as A being the lowest digit and D being the highest digit, and each time an input pulse is given, 2
Count up from the lowest digit in base numbers. Following this example, this embodiment associates the [A ₂ , B ₂ , C ₂ , D ₂ ] columns with [1, 1, 0, 0]. next,
A negative signal (Fig. 5c) is applied from the control circuit 7F to one terminal of the NAND gates _N10 and _N11 , and while this negative signal is being generated, the signal shown in Fig. 5d is applied as described above. By applying one pulse of the write clock to the temporary storage shift register 8 shown in the figure, both NAND circuits N ₁₀ and N ₁₁ are used as header bits.
The output "1" is stored in the shift register 8.

After that, the counter 7 for driving the multiplexer
A pulse shown in Fig. 5e is applied from the control circuit 7F to D at the timing _T7 , and the multiplexer 7E synchronizes with the rising edge of this signal to sequentially read the vehicle speed data starting from the lowest digit with the sign bit at the beginning. Output.

As explained earlier, for example, if the vehicle speed data is +3 in decimal notation, [1, 1, 1] is output from the multiplexer 7E, and at this time, the counter 7D performs the counting operation described earlier. , when the count becomes equal to the value of the counter 7C, this is detected when the outputs of the exclusive OR circuits _E1 to _E4 all become "0" (at time _T3 shown in FIG. 5). . This results in
Flip-flop 7H is set, and the output of flip-flop 7H is inverted to "0" as shown in FIG. 5f. This inverted output signal is applied to the control circuit 7F, and as a result, the counters 7C, 7D and the clear terminals of the flip-flop 7H have enough time to cover the remaining 6 bits of clock before the next clock pulse is applied. The function of the viewing device 7, which is cleared by _t5 shown in FIG. 5, is to input the signal from the arithmetic circuit 6, convert it into the shortest data string, and output it to
It is to output serially from 7k and 7m,
Now in binary [1, 0, 0, 0, 0, 0, 0,
1, 1], the 2nd to 7th 6-bit “0” are deleted as meaningless data as explained above, and the lower-order bits start with the sign bit. As a result, 3 bits [1, 1, 1] are output from the multiplexer 7E, and one side of the shift register 8 for temporary storage, including the header bits output before that, is [1, 1, 1]. 1, 1, 1] is
[1, 0, 0, 0] is stored in the other one.

Note that when the variation in vehicle speed is zero, one of the shift registers 8 contains a header bit "1" and a +0 bit from which the irrelevant data has been deleted as described above.
[1, 0] corresponding to [1, 1, 0] plus [1, 1, 0]
However, the other side has header bits “1” and [0,
1] and [1, 0, 1] are stored.

At the end of the above sampling time T (T ₉ shown in Figures 3, 5, and 7), the third
A clear pulse shown in FIGS. c and 7b is sent from the control circuit 10 to clear the contents of the counter 3 and prepare it for the next sampling.

On the other hand, the control circuit 7F in the viewing device 7 has a built-in counter that accumulates the number of bits stored in the shift register 8 for temporary storage, and the counted value of this counter is 1024-10=1014. When the number of bits is exceeded, a trigger signal (not shown) is sent from the output terminal 7n to the control circuit 10.

In this case, one piece of data stored in the shift register 8 has a maximum of 10 bits. The reason is that
(header bit x 1) + (sign bit x 1) + (data bit x 8) = 10. Furthermore, the minimum length of one piece of data stored in the shift register 8 is 3 bits, so data with different numbers of bits are randomly packed in the shift register. Therefore, care must be taken when checking the storage capacity of the shift register. And the rest of the storage capacity is at maximum
Since 10 bits are required, if there is less storage capacity remaining, that is, when the number of bits already stored exceeds 1014 bits, a trigger signal is generated to transfer the stored contents to magnetic tape. to prevent data loss.

Next, in the present invention, we call the incremental operation,
Intermittent operation of a magnetic tape recording device will be explained. Upon receiving the above trigger signal, the control circuit 1
0 sends out the control signal shown in FIG _.
Thereafter, a solenoid control signal shown in FIG. 7f is applied to the solenoid for pressing the capstan and the pinch roller together, and this solenoid is turned on, so that the magnetic tape starts running on the head surface.

Then, after the rise time _t71 at which the tape speed becomes constant has elapsed, the vehicle speed data stored in the shift register 8 is read out, and the encoder circuit 9 reads out the vehicle speed data stored in the shift register 8.
After being converted using the NRZI recording signal system, the codes of phase "1" and phase "0" are synchronized and serially recorded on two different channels of the magnetic tape.

Since this device processes variable length data, it is necessary to separate individual pieces of data during recording. For this reason, header bits are determined as the delimiters. That is, data is recorded as normal data (phase "1") and its inverted data (phase "0"), and the portion that is common to both phases and is "1" can be identified as a header bit.

Therefore, in order to reproduce a data string from a magnetic tape, if a header bit in which both phase "1" and phase "0" of the read signal are "1" is detected, one of the header bits from that header bit to the next header bit is (phase “1”) data can be taken as displacement data. At this time, the other data (of phase "0") can also be used for data checking.

Here, while data is read from the shift register 8 for temporary storage and recorded on the magnetic tape, the counter 3 for counting vehicle speed pulses, each register 4, 5, the arithmetic circuit 6, and the viewing device 7 are operated by the control circuit 10. All its functions have been stopped by a signal.

Then, when the transfer to the magnetic tape is completed, the solenoid control signal is extinguished, the capstan and the pinch roller are released, the tape stops running, and the capstan driving motor is stopped. Thereafter, sampling, calculation, and temporary storage of the vehicle speed from _T0 shown in FIG. 3 are repeated.

Furthermore, data can be transferred to magnetic tape in a very short time, with a tape speed of 4.75 cm/sec.
c) With a known recording device, when the data recording density is 800 [pulses per inch (PPI)], 1024 bits can be recorded in a recording time of about 0.68 [sec]. Therefore, before the next calculation result is applied to the shift register 8, the contents of the shift register 8 are stored on the magnetic tape.

In the embodiment described above, the reference value of the displacement amount is
This is the value initially stored in the register 5, and if no particular setting is made, the value after the first sampling will be a random value. However, from the second time onwards, it is a difference between the sampled data. In this sense, the playback device only needs to discard the first data. Note that if the values of all counters and registers are cleared to zero when the power is turned on, as is generally done in digital circuits, the reference value of the first displacement amount data will be zero.

In the above-described embodiment, a vehicle speed sensor 1 that generates a number of pulses corresponding to the vehicle speed is used, but a vehicle speed sensor that generates a voltage value that corresponds to the vehicle speed is used, and this output is converted into a digital quantity. In addition, the detected value is not limited to vehicle speed, but may include things related to automobiles such as engine rotation speed, engine cooling water temperature, and engine oil pressure, as well as the operation of ships and aircraft. Any other variable detection value such as speed may be used.

Further, in the embodiment described above, the vehicle speed signal from the vehicle speed sensor 1 is input to the counter 3, and this vehicle speed signal is transferred to the register 4, and the stored contents of this register 4 and the previous vehicle speed signal are stored. Although the memory contents of other registers 5 are calculated by the arithmetic circuit 6, the counter 3 is also used as a register, and the count value of this counter 3 and the previous vehicle speed signal are stored in the other registers. If the contents are calculated by an arithmetic circuit, one register can be omitted.

Further, in the above-described embodiment, only the displacement amount is recorded for each sampling, but the vehicle speed sensor 1 detects the point in time when the vehicle speed is zero, and the signal of this zero vehicle speed is also recorded on the same track of the magnetic tape or on another track. Alternatively, the data may be recorded on the same track.

Further, in addition to the amount of displacement of the detected value such as the vehicle speed, other various data may be recorded on different tracks on the magnetic tape.

In the present invention, since the displacement amount of the detected value for each sampling is recorded in the magnetic recording device as variable length digital data from which invalid bits have been removed, the recording area of the magnetic recording device can be effectively utilized to record a large number of Data can be recorded.

In this case, the variable length digital data consists of a first phase consisting of the minimum display bit and a header bit for data distinction, and a header bit that is the same as the inverted signal of the minimum display bit, regarding each digital data representing the amount of displacement. It is formed with two channels from the second phase. Therefore, when reproducing recorded variable-length data, if you extract the point where both channels have the same bit (because that point exists only in the header bit), you can retrieve the displacement data consisting of the minimum display bit that follows. It has the excellent effect of being able to be taken out immediately.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing the configuration of the system of the present invention, Figure 2 is an electrical wiring diagram showing a specific example of the vehicle speed sensor and gate circuit used in the system of the invention shown in Figure 1, and Figure 3 is the diagram shown in Figure 1. A time chart for explaining the operation of the method of the present invention shown in the figure, FIG. 4 is an electric circuit diagram showing a specific example of the viewing device used in the method of the present invention shown in FIG. 1, and FIG. 5 is a book shown in FIG. 1. A time chart showing control signals to the viewing device and shift register for temporary storage used in the inventive system; FIG. 6 is a time-vehicle speed characteristic diagram for explaining the sampling time of the inventive system shown in FIG. 1;
FIG. 7 is a time chart for explaining the timing of driving the magnetic tape recording device and transferring data from the temporary storage shift register to the magnetic tape in the method of the present invention shown in FIG. 1...Vehicle speed sensor for detecting a detected value, 2...Gate circuit for sampling, 3...
Counter, 4...Register, 5...Register,
6... Arithmetic circuit, 8... Shift register forming IC memory for temporary storage, 9... Encoding circuit, 12
...magnetic tape recording device.

Claims (1)

[Claims] 1. Sampling the detected value at predetermined time intervals,
a register for storing each of the two detected values sampled at a predetermined time interval; a calculating means for calculating the displacement between the two detected values and generating displacement digital data representing the displacement; and the displacement digital. The first phase consists of receiving data, extracting its minimum display bit and adding a header bit for data distinction to it, and the second phase adding the same header bit as the header bit to the inverted signal of the minimum display bit. a converting means for generating variable length digital data; a memory for temporarily storing the variable length digital data; and a code for converting the digital displacement amount stored in the memory into a code signal for magnetic writing and recording it in a magnetic recording device. A displacement recording method comprising: encoding means; and timing means for incrementally operating a magnetic recording device when the encoding means is activated.