JPS6132749B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is intended for use in connection with a musical instrument, such that data forming a performance may be optionally recorded and reproduced later through the same instrument or another instrument. Pertains to data recording and retrieval devices.

It is well known that musical instruments such as pianos and organs can be controlled to reproduce musical expressions by means of prerecorded data. The most well-known form of pre-recorded data is the so-called "piano roll", which is essentially a punched roll having at least 88 channels that are read in parallel to control the operation of the piano keys. It is paper tape. Making known piano rolls is laborious and expensive, and they are difficult to make or make extensive changes to.

The latest developments in devices for recording performances for later reproduction record keypress data to tape in a time-multiplexed order of one or two channels, and then play the tape. In addition, a system and a tape recorder are used to reproduce the musical expression by demultiplexing. This system has the advantage of eliminating time wastage in creating piano rolls and of allowing both carefully and painstakingly pre-recorded performances as well as optionally pre-recorded performances to be reproduced as often as desired. ing.

Known tape recording systems involve the generation of a relatively constant frequency sinusoidal waveform that is divided into scan frames of predetermined length. Each scan frame consists of a series combination of 80 or more data units represented by sinusoidal cycles, each data unit being assigned to a certain count, and each count being assigned to a piano or organ key, or alternatively some number of data units. It represents an auxiliary function, such as an expression. Known systems amplitude modulate the sinusoidal waveform within each data unit of a scan frame so that high amplitude levels represent "sync" pulses, intermediate amplitudes represent "key on" signals, and low amplitude signals " It consists of an elaborate mechanism containing circuitry designed to represent the amount of clock.
Simply put, the count of sinusoidal transitions identifies a particular key within the scan frame, and the amplitude level of the waveform transition represents the particular function to be performed on that key, or the key function code is If not, the transition is used to resynchronize during decoding operations.

It is very difficult to use the precise amplitude modulation described above within a tape recording system, and the output signal amplitude is dependent on error-generating factors such as changes in tape speed, tape stretching, circuit drift, and other factors. Expensive and accurate recording equipment is typically required to minimize variation. Simply put, accurate data encoding and decoding using three or more different amplitude levels in very short serial data is a very difficult task.
This incurs unusual prices as far as home entertainment products are concerned.

It is an object of the invention to provide a data recording and retrieval device, in particular for use in connection with musical instruments such as pianos, in which performances can be arbitrarily recorded and reproduced. Furthermore, the apparatus is well suited for implementation with low cost home entertainment tape recording devices such as cassette tape recorders and tape decks. Typically, this is done by systems that use binary codes to record streams of data on a continuous recording medium, such as magnetic tape, and the recorded waveforms are divided into first and second relative It consists only of signal levels and relatively abrupt coded transitions between these levels, thus reducing the need for analog amplitude detection, threshold detection, or other absolute value monitoring devices in the code and demodulation system, as well as the need for absolute amplitude monitoring devices. Make it completely unrelated to level. In the preferred form, the data is recorded in a self-clocking binary waveform, and the keypress and clock signals are represented by the position of the transition between binary levels, and the level or amplitude itself is determined by how it is. It doesn't have any meaning whatsoever. Thus, a single channel tape can be used to record self-clocking data, from which key press data and clock data can be easily retrieved.

A further object of the present invention is to extend the data encoding by using transitional encoding so that auxiliary devices such as rhythmic accompaniment and video displays can be used to reproduce the performance. Provides the ability to operate or control recording waveforms synchronously with the recording waveform. Generally, this involves assigning certain data units within the scan frame for recording auxiliary drive data to the same transition code between binary signal levels as the music data itself, and separating such signals during demodulation. and using such signal to directly excite an auxiliary device,
This is achieved through control.

Further features and advantages of the invention will become readily apparent upon reading the following description. Although the present invention has been described with reference to a system for both recording and reproducing data forming a performance, the present invention is capable of recording a performance at one location and facility and transmitting the performance to another location. It should be noted that it is intended to be able to be reproduced or reproduced with equipment and equipment. Therefore, the effects of the present invention can be implemented in a reproduction system without any recording capability. In order to understand the invention as a whole,
Reference should be made to the accompanying drawings and description.

Referring to FIG. 1, a system 10 for recording and reproducing arbitrarily generated piano representations.
It is shown. This system 10 is particularly adapted for use in connection with a conventional piano (not shown) that has been modified only to include a key closing contact forming a switch 12, said switch 12 being It is closed to generate data in digital binary form each time a given key is pressed. This will be explained in more detail with reference to FIG. The piano further includes a petal switch 14 to indicate the use of "sustained" pedals, and a binary source 16 of expression signals generated in conjunction with playing musical expressions on the piano in a conventional manner. source 1
2, 14 and 16 can all be used by the performer during the performance of a musical expression to generate input signals, said signals occurring in various combinations based on a certain order, and the timing of which Determined by the player. The combination of signals includes a simultaneous combination of one key press signal when a single note is played during the musical expression and a key press signal when a chord or other note combination is played during the performance. Contains.

System 10 includes a multiplexer 20 whose function is a predetermined serial bit length (in this case 128 bits long).
and serialize the parallel input data from input data sources 12, 14, and 16 into this scan frame, i.e., the multiplexer 20 converts the parallel input data from all sources into The 128 data cells or bits are arranged in a predetermined numbered order as best shown in FIG. The selected data formats are: 8 bits for the synchronization word; 72 bits for the piano keyboard switch 12; 1 bit for the persistent data; 12 bits for the expression data.
It includes an allocation of 12 bits for data to drive a CRT display, such as lyrics and musical scores, and 15 bits for auxiliary functions such as rhythmic accompaniment and various other operations.

The serialized data from multiplexer 20 is in a code format known as non-return to zero (NRZ), where positive transitions between binary signal levels represent a "1" and negative transitions represent a binary signal. “0”
It represents. Those familiar with data and coding principles will recognize that NRZ codes are not inherently self-clocking since long strings of bits of the same binary value are characterized by the absence of any transitions. It should be obvious. This is (1)
The frequency response of the receiver circuitry must still reach bit rates from DC, and (2) a separate clock signal is encoded or recorded on a second recorder track to separate the read operation from a data stream or scan frame. This creates several problems, including the need to synchronize the data cells with their actual locations. On the other hand, NRZ codes have the advantage of high data density, and it is therefore desirable to maintain this advantage of high density to the extent possible. Encoder 26 combines clock information from timing device 22 with serialized NRZ data from multiplexer 20 and guarantees between binary signal levels for most or all of the data cells of each scan frame. The following eight steps include providing data to the storage medium 24 in a code or format that causes a transition to occur.
It is preferable to take the form explained with reference to the drawings.
This code format has at least two advantages: (1) the data stream is self-clocking and therefore does not require a separate clock signal on the second recording media channel; and (2) The scan frame data is contained in transitions rather than signal amplitudes or levels. These two advantages result in high data code accuracy, high data storage density, and substantially reduced performance requirements of the recording device used. Storage medium 24 preferably takes the form of a standard one track magnetic tape recorder-player of the type using standard reel-to-reel tape cassettes. However, other recording devices can be used. Power supply 28 provides electrical excitation to all of the system elements of FIG. 1 requiring the same as will be apparent to those skilled in the art.

FIG. 1 further shows the input source 12, as described above.
means for retrieving stored data from the medium 24 and demultiplexing the data for use in reproducing the musical formation represented by the data from 14 and 16; It shows. This reproduction system transmits the data forming the music generator and the auxiliary functions together with its own clock data to a receiver 30, a decoder 32,
and a conventional read head arrangement for providing a synchronizer 34, which derives the clock signal from the scan frame. This reconfigured clock is transferred to decoder 3 as shown.
2 to restore the two-phase data to NRZ form and applied to demultiplexer 36. This demultiplexer 36 performs substantially the opposite operation of multiplexer 20, ie, reorganizes the serialized data from each scan frame into parallel form and outputs it via output bus 38 to the piano or organ or other device being used. to the key drive solenoid of the instrument. At the same time, the expression data is
It is applied to current 28 via bus 40 to modulate the amplitude of the drive voltage that is supplied to the key drive solenoid to perform its expressive action. Also shown in FIG. 1, the reconstructed clock signal from decoder 32 is applied to timing device 22 which synchronizes the demultiplexing operations. The scan frame 8-bit synchronization signal of FIG. 2 is extracted during demultiplexing and applied to timing device 22 to restart or synchronize the strobe clock for each scan frame, thus
It will also be apparent that the read strobe signal should not drift outside the data cell boundaries due to signal quality degradation and possible loss of the data cell synchronization signal.

FIG. 1 also shows how the auxiliary drive signal can be transmitted to an auxiliary device such as a CRT display to display words in pictures, a color display, or some other auxiliary functions such as changing the interior light to a desired brightness. Also shown is an output bus 37 from a demultiplexer 36 for controlling levels, operating rhythm devices, and other ancillary equipment and equipment, the functions of which may be associated with musical reproduction. Or it may be unrelated.

Expressive control can be provided in a variety of ways. FIG. 3 shows one expression control system.
In this system, a transducer 50 is mounted to sense the force with which a key is struck. This state is serialized by N-channel multiplexer 52 and amplified at 54. This amplified signal is applied to a power detector 56, which is a simple threshold detector with several discrimination levels. The output of this detector 56 is an analog-to-digital converter 58.
, and the converter 58 produces a digital signal suitable for recording within the system of FIG.

Transducer 50 can take any of several forms, such as a microphone,
It may be a simple accelerometer or a magnetic pickup. A transducer in any form is a voltage generator that generates a signal that is then multiplexed at 52 to form a single analog voltage stream. Analog-to-digital converter 58, of course, operates under the control of the clock signal from timing device 22 since each transducer 1-N must be sampled at the appropriate time.

In addition to being represented by reference symbols in FIGS. 4-19, a number of the components also include industry standardized numbers representing integrated circuits;
Such circuits are commercially available and therefore will not be specifically described here. These circuits are available as pre-implemented devices from Texas Instruments, Inc., Signetics, and Fairchild.
and Harris, Inc. According to catalogs published by these companies in 1972 and 1973, the following specific classifications of integrated circuit units are available from these companies:

Signetex: NE565 (phase-locked loop); Fairchild: 741, 710, 37002,
7400, 7404, 74193, 74150, 74151, 7486,
7474, 74121, 7420, 74192 and 74164.

FIG. 4 shows another system for piano expressive control that includes four microphone sensors 60 spaced apart at the rear of the keyboard. The outputs of the microphones are multiplexed together in series at 62, which device 62 takes the form of a 4-bit analog multiplexer, preferably a Fairchild 37022 DC device. The serial output from multiplexer 62 is amplified at 64 and applied to low pass filter 66. This filtered output is then digitized by comparator 68, counter 70, and ladder network 72. This ladder network is a known device and can be easily constructed using separate components or can also be pre-packaged circuit devices from Angstrohm Precision, Inc., such as binary circuits. Available as part of the DIP series. The frequency response for the low pass filter is centered about approximately 30Hz. The output of low pass filter 66 is converted to digital form and the least significant bit of the analog-to-digital converter alternates from "1" to "0".
The three least significant bits are used as outputs to provide eight or so control levels of the strength or volume of each quarter of the piano key by varying the voltage to the solenoid that strikes the key. The three bits of data are added to the data format, stored or transmitted, and converted back to parallel information. After being converted from digital to analog form, the voltage at which the solenoid is activated is adjusted in response to this analog signal to control the force at which the key is struck.

Other forms of presentation control can of course be used, including manual presentation control.

FIG. 5 shows details of a typical implementation of multiplexer 20 of FIG. Multiplexer 20 includes a 7-bit counter providing ²⁷ combinations for 128 multiplex functions. The circuit of Figure 5 is a two-stage multiplexing scheme, the first stage assembling the data into eight parts of 16 bits each, and the second stage assembling the data into eight parts of 16 bits each.
The two parts are further assembled into a single scan frame with 128 or more data units. The first stage uses the 4 bits from timing device 22 to perform a 16 bit multiplex function. For example, in circuit 80, 4 bits of timing information and 16 bits of input data produce a serial output from the 16 input information bits, with bit 1 being retrieved first and bit 16 being retrieved last. do. Operating in parallel with this multiplexer system are seven other multiplexers of substantially identical construction producing output bits at the same rate and controlled by the same four input timing bits. However, the outputs of these eight multiplexer devices are provided to an 8-bit multiplexer 82, the timing of which is controlled by three consecutive timing bits from device 22 shown in FIG. 1, the least significant bit of the timing sequence. be done. The output of multiplexer unit 82 samples each of the other eight multiplexers once at their respective output bit times such that bit 1 of multiplexer A1 is taken out first and bit 16 of multiplexer 80g is taken out last. to generate a 128-bit serial NRZ data stream.

The synchronization word illustrated at the beginning of the scan frame in FIG. 2, for example, consists of a series of eight 1's that provides a fool-proof data format, which is unlikely to occur during random musical data formation. and can also be distributed by the synchronizer 34 and recognized as a synchronization word. This synchronization word can be fixedly wired by wiring the first eight bits to zero if all ones are required as a synchronization word. SN proposed as device 80
The 74150 produces an inversion between input and output, so all zeros are wired as an all ones sync word. A switch 12 from the piano keyboard and for the sync word is wired directly to the input of a multiplexer device 80, and when the keys are closed the switch is grounded to a common point to produce an output signal. The output data is therefore inverted to ground, or converting a binary zero to a binary one.

In the case of music reproduction, sample rate is of substantial significance in order to enable complex pieces of music and auxiliary functions to be adequately reproduced using conventional recording equipment. The sample period for each data cell is approximately 250 microseconds for both multiplexers so that the sample rate is much faster than the play rate. The sample time is therefore negligible compared to the time that a key is actually held down in normal operation of a piano or organ or other musical instrument.
The sample period for each bit is very fast, as mentioned above, about 250 microseconds, so that a key switch may
That is, if the depression starts in the middle of a sample period, it will not be detected during that sample period in that scan frame. However, since the corresponding sample period of the next scan frame arrives immediately after 250 microseconds x 128 = 0.032 seconds, the press of the key switch is detected during that sample period. This is because it takes a long time, longer than 0.032 seconds, to press down a key during normal operation of a piano or organ. On the other hand, parasitic key operations for short periods of time, such as those shorter than the scan frame time of 0.032 seconds,
It goes undetected. In this way, even if the strength of the key press (expression effect) is not detected in the first scan frame, it is always detected in the next scan frame and recorded at the expression data bit position of that scan frame. It is.

Referring now to FIG. 6, a two-phase encoder for implementing apparatus 26 of FIG. 1 is shown. This encoder 26 receives the signal from the multiplexer 20.
A certain code is generated in response to the NRZ data, which code has self-clocking characteristics and also does not exhibit a significant DC component. The basic two-phase level code is such that zero information is an inverted clock and one information is a true clock.
This code is a simple exclusive OR of the inverted clock information and the NRZ data. This is gate 9
0 and 92, implemented and connected as shown. In the timing diagram of FIG. 7, the two-phase data is a clock for binary ones and an inverted clock for binary zeros. The maximum time between data transitions is bit time. There is always a transition in the data between the bits, which is a high to low transition indicating a "1" and a low to high transition indicating a "0". When using exclusive-OR gates 90 and 92 to generate two-phase data, the spikes or transients generated in such data at high frequencies or narrow pulse widths are dependent on a sufficiently low frequency response tape recording system. It will be waved. The two-phase data encoder of FIGS. 6 and 7 is therefore particularly well suited for use in tape recorders, but requires some alternative solution for other transmission media such as wireless or wired transmission.

If correct data phasing is a requirement of the storage or transmission system and the signal-to-noise ratio of the system is good, a double density encoding scheme can be used using the implementation of FIG. 8. This results in a code format as shown in FIG. The double density code of FIG. 9 has a transition in the middle of ones and a transition at the end of zero. However, when a single zero occurs with either waveform side being 1, there is no transition at all. To generate a double-density code, the two-phase level code is an exclusive OR gate 9
6 and the NRZ data. The output of gate 96 is sent to a buffer flip-flop 98 to remove voltage spikes.
Stored in The "not" output of this flip-flop is applied to the clock input of flip-flop device 100, and the negative edge
Switch flop. The flip-flop thus generates a double density code that does not require the phase of the code to be maintained by the storage or transmission medium 24. The bandwidth may be half of that required for two-phase data. Referring to Figures 8 and 9, in a double density code, if there are 1's at both ends and all 0's in between, no transition will occur in a long code bit sequence. A DC component will be generated. This is not very desirable as it increases the bandwidth, and to avoid this, the data needs to be random to some extent. Of course, other code formats including return to zero (RZ) can be used. This has another advantage if the storage or transmission medium 24 requires clocks and data, for example, the use of telephone line transmission means requires clocks and NRZ data, whereas other media require RZ data. Good too.

Receiver 30 may take any of several forms, one form being shown in FIG. The input to receiver 30 is AC coupled from the tape read head to a zero crossing detector consisting of transistor 102. Correct input load R2
Or the resistor R1 that loads R3 is the transistor 10
Bias so that 2 crosses zero. Capacitor C
1 coupling capacitor. Capacitor C2 is a capacitor for a low-pass filter for filtering noise. Resistor R4 is simply a load on transistor 102, and the output is the data restored to its original format. Most tape recorders and other transmission systems can use the receiver of FIG.

A two-phase decoder implementation for device 32 is shown in FIGS. 11 and 12. The two-phase decoder 32 in FIG. 11 includes R1 and C as a delay circuit.
A one-shot device is used in which a transition is extracted from the two-phase data by delaying the two-phase data through the transistor Q1 having a 1. Circuit 32 then exclusive-ORs the output of Q1, which is the inverted and delayed two-phase data, with the input two-phase data. The output of exclusive-or gate 110 is a positive-going spike on the edge of the input data and triggers one-shot device 112 at the timing set by R3 and C2. The output of this one-shot device 112 is a 3/4-bit period clock, and the one-shot device encounters a one-to-zero or zero-to-one transition of two-phase data.
At the th time this one shot device synchronizes with the incoming data stream. This clock is then used to clock the inverted two-phase data into data flip-flop 114. The output of data flip-flop 114 is reconstructed NRZ data;
The output of one shot device 112 is then a clock used for data demultiplexing.

FIG. 13 shows a phase-locked loop synchronizer suitable for implementing the device 34 of FIG. If the data storage and transmission equipment has a low signal-to-noise ratio, i.e., tape speed fluctuations or other factors cause a reduction in data quality, the clock information may be transferred to a phase filter of the type shown in Figure 13. It can be regenerated by using a fixed loop. In particular, as shown in the upper left corner of FIG. 5, the sync word is hardwired such that the first eight bits are wired to a zero or ground bus. These connecting lines are first scanned in this array to generate the first eight bits in the data frame illustrated in FIG. After the entire musical score has been recorded to tape (note here that it is recorded to tape in serial form), it is decoded, then demultiplexed, and demultiplexed in Figure 1. The synchronization word (all 1:11111111) shown on the line labeled "sync" from multiplexer 36 to timing device 22 resynchronizes the system for each frame of data. During playback, the synchronization word is detected by the IC circuit 178 shown on the left side of FIG. The fixed wire is the wire connected to block 80, which is the first part of the two-level multiplexing used here, as shown in the upper left corner of FIG. The first eight bits in this first level of multiplexing are hard wired for the sync word. In either two-phase or double-density codes, the clock signal associated with twice the clock frequency is connected to delay network R1, C1, transistor 11.
6. obtained from the data by extracting the transition edges of the data using an exclusive-OR gate 118, a flip-flop 119, and a one-shot device 120. The output of the one-shot device is approximately 1/4 the bit time of the clock speed used. This pulse is fed into a phase locked loop containing transistor 121 which generates an output clock at twice the bit rate. The decode mechanism then divides the clock by two and properly phases it with the data. In the circuit of FIG. 13, the output of the one-shot device is fed into a phase-locked loop using a Signetex NE565 or its equivalent operating at a center frequency twice the bit rate. The NE565 from Signetex is a self-contained compatible filter and demodulator for the frequency range 0.001Hz to 500KHz. This circuit includes a voltage controlled oscillator of exceptional stability and linearity, a phase comparator, an amplifier and a low pass filter, which can be found in Signetex Linear Integrated Circuits Catalog 6-72 through 6-6.
It is described in more detail on page 76. The voltage controlled oscillator VCO must be able to handle large fluctuations in input frequency and flutter due to noise that may be present in the background of the recording tape. The output of the phase-locked loop is buffered if the bit rate clock is twice as high. A phase-locked loop is a simple circuit using standard integrated circuits.

Referring to FIG. 14, a two-phase decoder using a phase-locked loop is shown. The 2X clock from the phase-locked loop is used to shift the two-phase data into data flip-flops 132 and 134, and these flip-flops act as shift registers that store two half bits into the shift register. both flips
When obtaining a 1 on the flop or a zero on both flip-flops and decoding this state with the clock, the output flip-flop 13
6,138 is cleared to phase the clock with the incoming data. In the circuit shown in FIG. 14, the zero-to-one transition of the data synchronizes the clip-flop props 132, 134 to the correct phase of the data. The two-phase data is loaded into data flip-flops 136 and 138 using bit rate clock flip-flops and then decoded using the timing diagram shown in FIG.
Generate NRZ data.

A double density decoder using a phase-locked loop as the clock is shown in FIG. Double-density input data is sent to data flip-flop 150,
152, 154 and 156 into a 4-bit shift register. The outputs from these four data flip-flops are decoded to synchronize the clocks and set the output data to zero. 4 data flip-flops all 1
It is clear from the timing diagram of FIG. 17 that when the clock has a zero or all four data flip-flops have zeros, the clock and data must both be zero at this time. By decoding this state, all 1s or all zeros in all four flip-flops that clear the clock flip-flop and clear the data flip-flop are properly phased together. The output data flip-flops are toggled to reconstruct the NRZ data.

FIG. 18 shows a suitable implementation of timing device 22 of FIG. The timing device uses the same counter in both multiplex and demultiplex modes. Whether a system is operating in multiplexed or demultiplexed mode can be determined in several ways. The ideal method would be to obtain a common input from the tape recorder 24. The commands to operate the clock for use by timing circuitry 22 are either obtained from timing reference oscillator 160 or sensed from incoming data, depending on the command. gate 1
This clock, either derived from an oscillator by enabling 62 and 164, or alternatively from data via gate 166, is then implemented with two SN74 192 pulses per count cycle. synchronization counter 1
70, 172 via gate 168.
The synchronization signal that synchronizes the counter during receive mode comes from a demultiplexer that senses the synchronization word. That is, referring to the sync detection circuit shown in the upper left corner of FIG. 19, the sync word bit in the data frame is applied to an AND gate via register 178 to generate one sync pulse. This synchronization pulse is applied to synchronization counters 174 and 176, which consist of two SN7474 data flip-flops in the timing apparatus of FIG. When the data frames shown in FIG.
76, the inhibit signal from the synchronization counter 176 of FIG. , the output data from the multiplexer can be used via the demultiplexer. However, if such synchronization pulses do not occur successively, the data frames are not properly synchronized, and the synchronization counter 176 in FIG.
Generates a prohibition signal. This inhibit signal is applied to the demultiplexer of FIG. 19 to inhibit use of the output data from the multiplexer. In this way, the reproduction of sounds based on unsynchronized data frames is prohibited, and the performance is played back without the sounds. This means that it is better for the listener to skip the out-of-tune notes without playing them than to play the out-of-tune notes by playing back the out-of-sync data frames. This has the effect of not causing any harshness to the ears. The clock from the internal oscillator that oscillates the bit rate clock, or alternatively the clock from the receiver synchronizer, can be set at one time with commands to select the required clock.
78 (see Figure 19).

Referring to FIG. 19, the demultiplexer 37
It is shown. In FIG. 19, the seven timing bits from timing device 22 are
one 8-channel demultiplexer 1 that feeds the 16-channel demultiplexer 182;
The output demultiplexer of the two-stage demultiplex operation consisting of 80 is controlled. The output from this demultiplexer is only present for 25 microseconds, which is insufficient to drive the solenoid, so the pulse stretcher 184 is used to stretch this output to the required 30 milliseconds. is necessary. A suitable pulse stretcher is the one manufactured by Mr. Wheelwright.
Wright) Patent No. 3,771,406, with its reference number 290 and Section 6, Section 33 of the patent.
See the description starting with the line. Other devices such as one-shot devices can also be used. The stretched pulse is applied to driver switch 186. The multiplexer in FIG. 19 does not use a storage device. It is also possible to use a demultiplexer with a storage device for the time bits.

Figure 20 shows the equipment required in some configurations on the piano itself. Key 188 operates via a conventional mechanism 198 to move hammer 192 to strike string 194. When key 188 is manually depressed, non-conductive trip 196 pushes spring wire 198 into contact with conductor 202 and connects the electrical circuit from excitation plate 200 to conductor 202 connected to multiplexer 20. make. A similar configuration is provided for each key. To playback, solenoid 204 is energized with a voltage pulse causing plunger head 206 to rotate key 188 as if the key had been struck by hand.

The auxiliary and video signals from demultiplexer 37 can be used for a variety of operations, including those that are not musical in nature. Video word display by Gerusback Publications of New York
It may be provided by a CRT device of the type described in a Radio-Electronics paper published in 1973 by the American Society of New York and entitled "TV Typewriter."
This device is a CRT (television) set 300.
, which can be programmed via a typewriter to display words at a selected speed. In order to use such a system in conjunction with the player piano system described herein,
The first operator types words in synchronization with the simultaneous performance of a piece by the second operator, and all information is input via multiplexer 20 to encoder 26. Here, both the first operator and the second operator are humans, the second operator is a person playing the keys of an ordinary piano, and the first operator is a person who is playing the keys of an ordinary piano, and the first operator is a person who is playing the keys of an ordinary piano. This person is typing data words by hand on a TV typewriter. Fifth
The illustrated device 80g may be assigned a TV typewriter input. During playback, channel 182f of demultiplexer 36 may be exclusively assigned to control the TV set.

It should be understood that the above description is merely illustrative of the present invention and is not intended to be limiting in any way.

[Brief explanation of the drawing]

Figure 1 is a block diagram of the data recording and reproduction system, Figure 2 is a diagram of the data recording format in a certain scan frame, Figure 3 is a block diagram of the representation control system, and Figure 4 is the second automatic representation control. The circuit diagram of the system, Figure 5 is a block diagram of the multiplex system, Figure 6 is a diagram showing a two-phase encoder, Figure 7 is a waveform diagram showing the operation of the encoder in Figure 6, and Figure 8 is a diagram showing the operation of the encoder in Figure 6. A diagram showing the encoder, Figure 9 is a waveform diagram of the encoder in Figure 8, Figure 10 is a circuit diagram of the receiver, Figure 11 is a circuit diagram of a two-phase decoder, and Figure 12 is a waveform diagram of the decoder in Figure 11. Figure 13 is a circuit diagram of a phase-locked loop synchronizer, Figure 14 is a diagram showing a two-phase decoder using a phase-locked loop, and Figure 15 is a diagram showing a two-phase decoder using a phase-locked loop.
14 is a waveform diagram of the decoder of FIG. 14, FIG. 16 is a circuit diagram of a double density decoder for use in conjunction with the encoder of FIG. 8, FIG. 17 is a waveform diagram of the decoder of FIG. 18 is a circuit diagram of the timing device of FIG. 1, FIG. 19 is a diagram showing a demultiplexer, and FIG. 20 is a perspective view of a piano key data generation and actuation device. 10... Recording and reproduction system, 12... Switch, 16... Binary source, 20... Multiplexer, 22... Timing device, 24... Storage or transmission medium, 26... Encoder, 28...
...Power supply, 30...Receiver, 32...Decoder, 3
4...Synchronizer, 36...Demultiplexer, 1
88...Key, 204...Solenoid.

Claims (1)

[Claims] 1. In a music data storage and retrieval device used to operate an electrically controlled player piano having a selectively actuatable music generation key press device, a music data storage and retrieval device for operating said music generation key press device. music information comprising relatively steep transitions between a first level and a second level, said transitions providing clock data and music control data for each of said music generation key presses; magnetic tape storage means containing a serial sequence of frames of musical information as shown in the drawing; reading means for retrieving said data in serial form from said magnetic tape; means for reconverting each frame of serial music control data to parallel form controlled by said retrieved clock data; and means controlled by said retrieved clock data. means for applying reconverted music control data to the music generation device and reproducing the music formations recorded therein, wherein the serial waveform serial sequence of frames of music data is transmitted to the music generation key. comprising representation data representative of the intensity with which the depression device is to be actuated, and comprising means for applying an intensity signal reconverted to parallel form to said control means, each frame of musical information having a plurality of predetermined values. contains a periodically occurring synchronization word consisting of bits, and when a synchronization word is detected successively in response to the synchronization word, it permits the reproduction of the music formation by the current frame of music data; A music data storage and retrieval device, comprising means for inhibiting reproduction of a music formation by the current frame of music data when a synchronization word is not detected.