JPS6134196B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention allows a vending machine to reliably accept a selection signal generated by a customer's operation from a selection means such as a selection switch, and even if a plurality of selection signals are generated due to simultaneous double operations, only one selection signal is adopted. This invention provides a control circuit for a vending machine. Conventionally, a selection signal obtained by operating a selection switch is introduced into a relay circuit to excite it, and the vending drive circuit is operated via a mechanical movable contact, which has the disadvantage of being prone to contact failure or malfunction. . Furthermore, if multiple selection signals are generated at the same time, all the corresponding relay circuits will be energized, resulting in the inconvenience of selling more products than the specified amount, and therefore a mechanism is required to prevent double operation of the selection switch. was. In addition, the control circuit in the conventional device is equipped with a relay circuit depending on the product type of the vending machine to which it is installed, and this control circuit cannot be applied to other vending machines with a different number of product types, resulting in a lack of versatility. was significantly delayed. In view of the above, the present invention provides a control circuit that accepts a generated selection signal and accurately operates a product sales drive circuit in accordance with the selection signal, and furthermore, this control circuit can be used in various vending machines with different numbers of product types. It is configured so that it can be applied to. Yet another object of the invention is to use RAM (Random Access Memory) or ROM (Read Only Memory).
The objective is to provide a control circuit that is suitable for LSI implementation by making effective use of this. An embodiment of the present invention will be described in detail below based on the drawings. FIG. 1 shows a control circuit according to the present invention. The bold arrow indicates a data bus, and data is transferred in 8-bit parallel fashion, and the flow of data is controlled by opening and closing control gates G ₁ . . . G ₁₄ . Adder 11 connects An end and Bn
At the end, addition or logical operation is performed on the input data, but in this embodiment, only the AND of both data is calculated, and AND is performed for each bit.
It can be considered equivalent to a logic gate with a gate.
That is, in 8-bit parallel, A ₁ , A ₂ , A ₃ ,
..., A ₈ and B ₁ , B ₂ , B ₃ , . . . , B ₈ at the Bn end
_{When data such as _ _}
The calculation results A ₈ and B ₈ are output. Adder 11
The data necessary for the calculation are data stored in each memory of the data ROM 10 and selection information inputted via the I/0 port 9. The 8-bit input terminal of I/0 port 9 has selection switches 1 and 1, respectively.
2, 3, 4, 5, 6, 7, and 8 are connected, and each selection switch is configured to output "1" when the customer presses it after inserting a predetermined amount.
The input status at port 9 becomes selection information. Therefore, when selection switch 1 is pressed, the selection information is 8 bits "0, 0, 0, 0, 0,
0.0.1". Further, the calculation result from the adder 11 is introduced into an accumulator (ACC) 13 and further judged by a decoder 12.
2 outputs a Sta signal "1" when a status is detected in the calculation result. As shown in FIG. 2, the sequence control unit 14 includes an address counter 15,
instruction register 16, clock pulse generator 17,
Flip-flop circuit 18, control ROM 19 and
It is composed of a group of AND gates, and as an address counter 15 counts up clock pulses sequentially generated from a clock pulse generator 17, an instruction register 16 sequentially specifies a sequence. The control ROM 19 is set to appropriately output control gate signals for making the control gates conductive according to each sequence according to the sequence signals S ₁ to B ₁₀ outputted from the instruction register 16. Also, AND gates 28, 20, 21, 22, 23, 24, 25,
26 and 27 are respectively S ₁ , S ₃ , S ₄ , S ₅ , S ₆ ,
S ₇ , S ₈ , S ₉ , S ₁₀ signals are input and Sta
The signal "1" is input. Next, the present invention will be clarified by explaining the operation. Flip-flop circuit 1 in selection standby state
8 is an instruction register 16 which has been reset and a clock pulse can be introduced into the address counter 15.
continues to output the _S1 signal and control ROM1
9 outputs control gate signals G ₂ , G ₃ , and G ₁₃ . Therefore, when the control gate _G13 is turned on, the selection information can be inputted via the I/0 port 9, and further introduced into the ACC13 via the control gate _G3 , the adder 11, and the control gate _G2 . ing. In this state, select switches 1, 2, 3, 4, 5, 6, 7,
8 is operated and "1" is input to the input end of the corresponding I/0 port 9, selection information with "1" in a certain bit is introduced to the ACC 13, and the decoder 12 detects the status. Outputs Sta signal “1”. And the AND gate 28 receives the Sta signal “1”.
A logical product is obtained with the _S1 signal and the flip-flop circuit 18 is set, and the clock pulse from the clock pulse generator 17 is introduced to the address counter 15 via the AND gate 29, and the address counter 15 starts counting up and commands. The register 16 sequentially outputs S ₂ , S ₈ , S ₄ , . . . S ₁₀ signals. Upon generation of the S ₂ signal, the control ROM 19 outputs control gate signals G ₁ and G ₁₄ and inputs selection information from the ACC 13 into the register 30 and stores it therein. Subsequently, based on the S ₃ , S ₄ , S _{5 ,} . . . signals that are generated sequentially, the sequence control unit 14 determines which bit of the selection information is “1” and scans the operated selection switch. Memories 31, 32, 33, 34, 35, 36, 37, 3 of data ROM 10
8 is set with data that has information of "1" only in the bit corresponding to the selected type, and the data is set sequentially.
S ₃ , S ₄ , S ₅ ‥‥Sequence control unit 1 according to signals
4 reads this data and uses adder 11 to store it in register 3.
The selection information is compared with the selection information stored as 0, and if a match is found, the selection switch operated by the Sta signal ``1'' generated in the decoder 12 is determined. First, when the S ₈ signal is generated, the control ROM 19 outputs the control gate signals G ₂ , G ₃ , G ₄ , G ₅ , and G ₁₄ to read the data set in the memory 31 as “0, 0, 0, 0,
0.0.0.1" and the selection information are compared in an adder 11. When selection switch 1 is operated, the selection information is "0, 0, 0, 0, 0, 0, 0, 1".
The calculation is performed as shown in Table 1 below, and ACC1
3, the decoder 12 detects the status and outputs the Sta signal "1".

[Table] When the output _A1 is obtained from the AND gate 20 with the Sta signal "1" and the _S3 signal, it can be detected that the selection switch 1 has been operated. Furthermore, the output _A1 generated at the AND gate 20 resets the flip-flop circuit 18 and outputs the clock pulse or the address counter 15.
Sequence transition stops because input is prohibited. However, if a switch other than selection switch 1, for example selection switch 3, is operated, the selection information is "0, 0, 0, 0, 0, 1, 0, 0", and the Sta signal is not generated as shown in Table 2. The address counter 15 is further incremented by the subsequently input reference pulse, and the instruction register 16 is incremented by the S ₄
The adder 11 outputs the signal and compares it with the data "0.0.0.0.0.0.1.0" set in the memory 32.

[Table] In this way, the selection information is generated when the Sta signal "1" is generated and the selection information is output to any of the AND gates 20, 21, 22, 2.
Memory 31, 32, 33, 34, 3 until output A ₁ is obtained at 3, 24, ₂₅ , 26, 27.
Comparisons with data set at 5, 36, 37, and 38 are performed sequentially. And the output resulted in AND
Gate 20, 21, 22, 23, 24, 25, 2
Selection switch 1, 2, 3, corresponding to 6, 27
It is determined that 4, 5, 6, 7, and 8 have been operated. After further determining which selection switch has been operated, the address counter 15 is returned (not shown) to end the operation. According to the present invention described in detail above, selection means that generates a selection output in response to a predetermined selection operation by a customer is connected to the input terminal of the I/0 port to obtain selection information and to The selection type can be determined by detecting whether there is an output in the bit. Therefore, since no mechanical contact is required to receive the selection output, malfunctions can be prevented, and compatibility can be improved since the selection means and the control circuit can be configured separately.
Moreover, even if a plurality of selection means are operated at the same time, the comparison is stopped when the first match is detected in the process of sequential comparison, so that only a single selection type is determined, thereby preventing double operations.

[Brief explanation of the drawing]

FIG. 1 shows a control circuit according to the present invention, and FIG. 2 shows a specific example of a sequence control section. Explanation of main drawing numbers 1, 2, 3, 4, 5, 6,
7, 8...Selection switch, 9...I/0 port, 10...
Data ROM, 11...adder, 12...decoder.

Claims (1)

[Claims] 1. Selection means for outputting a selection signal in response to a predetermined operation by a customer, and means for obtaining selection information by introducing the selection signal into bits corresponding to each product type;
A means for storing in advance appropriate selection information for each product type in which data is set only in specific bits corresponding to the corresponding product type, and a means for sequentially comparing the selection information and the appropriate selection information. A control system for a vending machine comprising means for determining, when a match is found in a certain bit, that a product corresponding to the matched bit has been selected.