JPS6134316B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a still image receiving device used in a still image transmission system in which a still image such as a character is divided into many picture elements vertically and horizontally and transmitted as a binary signal. As a still image transmission system that has recently been developed and proposed in Japan, a method is known in which binary still image signals are multiplexed and transmitted during the vertical retrace period of a television broadcast signal. The methods can be broadly classified into two types, and both of them involve dividing a still image such as text into many picture elements vertically and horizontally and transmitting them sequentially. On the other hand, the difference is that the other is vertical feeding. First, the difference will be explained with reference to FIG. In Figure 1, X indicates the horizontal feed transmission method, and Y
indicates a vertical transmission method. In the horizontal transmission method, a character image of, for example, 14 characters per line to be transmitted is divided into picture elements as shown in X2 of
Extract the image signal like . The extracted image signal X2 is multiplexed line by line in one arbitrary horizontal period during the vertical retrace period of the television broadcast signal and sent out. Repeat this from the top line to the bottom line. On the other hand, on the receiving side, this image signal
2 is received, sequentially stored in its own storage device, and read out from there to display a character image on the cathode ray tube as shown in X4. The solid line part in X4 is an image of a line that has already been received, the diagonal line part is an image of a line that is currently being received, and the broken line part is an image of a line that will be received from now on.
In this way, in this horizontal feed method, the character image is transmitted and displayed one line at a time from the top. On the other hand, in the vertical transmission method, the character image to be transmitted is similarly decomposed into picture elements like Y1, and these are scanned vertically starting from the left end as indicated by the dashed-dotted line, with 16 bits per column. An image signal like B2 is extracted. The extracted image signal Y2 is multiplexed one column at a time in an arbitrary horizontal period during the vertical retrace period of the television broadcast signal and sent out. Repeat this from the leftmost column to the rightmost column. However, in this method, the image signals of five types of programs (A to H) are transmitted in one horizontal period, and for this purpose, all the character images of each program are decomposed into Y1, and the image signals of each program are The image signals extracted from the program are multiplexed by chronologically arranging them in the order of programs A to E as shown in Y2. On the receiving side, only those desired to be received are selected from among these image signals, stored in a storage device, read out from these, and displayed as a character image on a cathode ray tube as shown in Y4. The solid line portion in Y4 is an image of a column that has already been received, the diagonal line portion is an image of a column that is currently being received, and the broken line portion is an image of a line that will be received from now on. In this way, in this vertical feed method, character images are transmitted and displayed one column at a time from the left. By the way, in each of these transmission methods, character images are decomposed and transmitted one line at a time or one column at a time, and in order to transmit character images of many programs, the image signals of each program are alternately transmitted. For this purpose, the receiving side must specify the image formation time until it assembles the received image signals and forms a character image, and the program it wishes to receive, and then actually receives the program. There will inevitably be some waiting time until the process is completed. The above two methods for both times will be considered. First, in the horizontal feed system, there are nine types of programs, and the experimental standard is set so that the image signal of the same program is transmitted continuously for 30 fields (0.5 seconds) each. The forming time required for one line to receive and display an 18-line character image is 18 field periods, or 0.3 seconds. However, the longest waiting time from specifying a program to being able to receive and display the text images for that program is when you have to wait until the transmission of nine programs has completed one cycle. 0.5 seconds x 9 programs
You will have to wait 4.8 seconds, which is 4.5 seconds plus the 0.3 seconds mentioned above. On the other hand, in the vertical feed system, there are 5 types of programs.
Since the experimental standard is set so that these are multiplexed in the same horizontal period as shown in Figure 1 Y2,
Once a program is designated, text images of that program can be immediately received and displayed, and the waiting time is almost zero. However, in the case of a character image with 16 rows of characters and 2 rows of spaces, as shown in Figure 1 Y1, the formation time required to receive and display one complete character is the same as that of the previous character. The longest time is when a program is specified during transmission in the first column and the entire reception and display starts from the next character, but in this case it is 34 field periods, or 0.57 seconds. Furthermore, the formation time required to receive and display one line of 14 characters is at least 2550 field periods, or 4.17 seconds, and at the longest, 268 field periods, or 4.47 seconds, to complete the entire character image. The time required to do so becomes longer. As described above, the two conventional methods have the disadvantage that either the image forming time or the waiting time is too long, and as a result, desirable still image transmission cannot be performed. The experimental standards for these methods are shown in Tables 1 and 2.

【table】

【table】

[Table] Therefore, the present invention eliminates such conventional drawbacks and
It is an object of the present invention to provide a device that can perform desirable still image transmission by shortening the waiting time after specifying a program even in the horizontal feed method. Another object of the present invention is to provide a device that can transmit data with a short waiting time in both the horizontal and vertical methods, and can also simplify the circuit configuration for reception. A further object of the present invention is to provide a device that can clearly display a plurality of lines of still images during horizontal feed type reception. Hereinafter, prior to explaining the present invention, still image receiving devices used in vertical feed systems and horizontal feed systems will be described. First, an example of a still image signal transmission mode using the horizontal feed method and the basic configuration of a receiving device thereof will be explained with reference to FIGS. 2 and 3. Figure 2 shows how a still image signal is superimposed on a television signal.
During the 20th horizontal scanning time, an image signal X2 for one horizontal line of a still image, a 4-bit program code signal PC indicating which program this image signal belongs to, such as weather forecast news, and this An 8-bit line number code signal LN indicating which horizontal line from the top of the still image the image signal X2 belongs to is superimposed with a start signal STX indicating the reference phase of each of these signals X2, PC, and LN. and transmit it. Note that Hs is a horizontal synchronization signal and Bu is a color burst signal. Also, each signal. In addition, each number X2, PC, LN is 2, “1” or “0”.
It is transmitted as a value signal whose basic clock frequency is 8/5 times the color subcarrier frequency of 3.58MHz. FIG. 3 is a block diagram showing the basic configuration of a receiving apparatus that receives such a multiplexed television signal and displays and reproduces a still image on a cathode ray tube. In this device, a receiving circuit 1 including a tuner, a VIF circuit, a video detection circuit, etc. receives a multiplexed television signal, a synchronization separation circuit 2 extracts a composite synchronization signal, and a horizontal oscillation circuit and a horizontal AFC circuit 3 receive a multiplexed television signal.
A horizontal pulse is formed by the synchronous separation circuit 4, and a vertical pulse is formed by the vertical synchronization separation circuit 4. Furthermore, the local subcarrier oscillation circuit 5 oscillates a color subcarrier signal (3.58MHz) synchronized with the burst signal Bu, and the reception clock signal generation circuit 6 multiplies this by 8/5 to obtain a basic clock signal of 5.727272MHz. This signal is used as it is or after being counted down by the clock counter 7, it is used as a clock signal for controlling the memory and other circuits, which will be described later. On the other hand, the television signal obtained by the receiving circuit 1 is waveform-shaped into a binary signal by the waveform shaping circuit 20, and then
The signals STX, PC, LN, and X2 superimposed on the 20th H are taken out by a still image signal extraction circuit 8, and the image signal X2 is supplied to a buffer memory 9 having a storage capacity of one line, for example, 240 bits. I'll keep it. Further, the program code signal PC is extracted by the program code signal extracting circuit 10, and when the program code signal PC indicates a program desired to be received, the program code signal PC is extracted from the buffer memory 9.
is controlled and the image signal X2 is written therein. The line number code signal LN is extracted by a line number code signal extraction circuit 11, and a line counter 12 counts horizontal pulses to detect which horizontal scanning line is being stored and reproduced by the receiving device.
The count output of is compared with the comparison circuit 13, and when the two match, the input gate 14 is opened and the image signal X2 of the buffer memory 9 is added to the main memory 15, and stored in a predetermined storage location in the main memory 15. . This main memory 15 has a storage capacity capable of storing the image signal X2 for one still image screen, and for example, the image signal X2 per horizontal line is 240 bits and has 200 lines (hereinafter generally N lines). If one screen is formed by horizontal scanning lines of 48K bits (generally 240XN bits), it has a storage capacity of 48K bits (generally 240XN bits) or more. Buffer memory 9 and main memory 15 may be constructed from shift registers or the like. After storing the image signal X2 in the main memory 15 in this way, the image signal X2 is read out from the main memory 15 in synchronization with the horizontal and vertical scanning of the cathode ray tube 16, and the mixing circuit 17 outputs an image of a normal television signal. By mixing it with a signal and applying it to the cathode ray tube 16, a desired still image can be reproduced and displayed. In addition, the start signal STX is extracted by the start signal extracting circuit 18 and applied as a reset pulse to the clock counter 7, so that the phase of the output clock signal of the clock counter 7 is synchronized with the phase of the start signal STX, and accurate It attempts to establish reception, storage, and read operations. A control unit 19 receives horizontal pulses, clock signals, line counting output signals, etc., and supplies clock signals to operate each of the above-mentioned circuits in a predetermined phase relationship, and also controls reception, storage, and readout operations. This is a signal generation circuit. Next, the basic configuration and operation of a still image receiving device that receives vertically-adjusted still images will be briefly described. First, Figure 4a shows a signal for conventional still image transmission sent from the transmitting side.
Hereinafter, only the 20th H will be explained, and the 20th H will be explained below.
(283H is omitted) are still image signals of 5 types of still image programs Y a, Y b, Y ha, Y
D, Y and H are multiplexed. In this transmission method, as shown in Figure 1B1, a single character image is divided into a matrix of 16 vertically x 16 horizontal pixels, and this divided character image is scanned vertically. In the 20th H, the image signal of 16 picture elements of 1 vertical column obtained by 1 vertical column is used as a unit, and the image signal of 16 bits of 16 picture elements of 1 vertical column of each still image of 5 types of programs is generated in the 20th H. Yi...Yho are multiplexed sequentially.
The initial pulse IP is for each image signal A,...E.
This signal represents the reference phase for synchronizing the clock that extracts the 16-bit information signal. Image signals for still images of each program YI...YH are the sum of the 16-bit character image signal for one vertical column of still images, plus 1 bit each of channel separation bit CS and stop bit SP. It consists of 18 bits. The 20th H contains the still image signals YA,...YHO of five types of programs, so if we were to specify and receive the still images of group B, Figure 4B Generate a sampling gate at the position where the image signal Y-ro for the still image of the program B is sent, extract and store only the signal Y-ro, and display the still image of the program B. . Next, FIG. 5 shows the basic configuration of a receiving apparatus for this vertical feed system. Here, 1 is a receiving circuit such as a video detection circuit of a television receiver or the like, and 20 is a waveform shaping circuit which waveforms the output of the receiving circuit 1 such as a video detection circuit into a binary signal. 2 is a synchronization separation circuit, which uses both horizontal and vertical synchronization signals output from the 20H
The 20th H (and
A 20th H sampling pulse that is at a high level for the 1H period of the 283rd H (the same applies hereinafter) is generated, and the output of the waveform shaping circuit 20 is thereby gated by the 20th H sampling circuit 8, and the 20th H sampling pulse as shown in Figure 4a is generated. Extract only the signal of the part. Next, the program selection circuit 22 selects the image signals Y1, . Only the portion of the image signal Y and B of the program B is extracted from among them. On the other hand, 5 is an oscillation circuit for the color subcarrier sc,
The color carrier wave generated here is multiplied by a basic clock generation circuit 6 including a doubler circuit to generate a 2sc basic clock. Since the 2sc output of the clock generation circuit 6 always maintains a constant phase relationship with the leading edge of the horizontal period signal, the output of this basic clock is frequency-divided by the sampling clock generation circuit 23 and the phase of the output is The initial pulse detection circuit 18
The phase is controlled using the initial pulse IP detected by the sampling clock generating circuit 23, and five groups of sampling clocks of 18 bits each are obtained as the output of the sampling clock generation circuit 23, each of which is synchronized with the image signal for the still image. That is, in order to extract the image signals Yi, . . . Yho of each program shown in FIG. and gate it in the program selection circuit 22 with a sampling pulse for program selection as shown in FIG. 4b,
A sampling clock is extracted only at the position of the desired program, and this 18-bit sampling clock is applied to the clock terminal of a buffer memory 9 constituted by a 16-bit shift register, and the output from the 20th H sampling circuit 8 is added to the input terminal. 18 of any program
Even with a bit signal, the first two bits are the channel separation bit CS and stop bit SP, so after clocking the buffer memory 9 by 18 bits as described above, the buffer memory 9 contains the 16 bits of the still image signal of the desired program. It will be stored temporarily in memory. Therefore, under the control of the transfer control circuit 13, the signals stored in the buffer memory 9 are transferred to the last row of the main memory 15, that is, the rightmost memory location, in a predetermined order, one bit per line, starting from the top, and stored. The signals are stored in memory by moving them one column at a time to the left. When the image signal is moved and transferred in this manner, the display of the character image on the cathode ray tube 16 rolls from right to left. In order to move, a new image signal newly received in the next field is transferred to the main memory 15 and replaced with the old image signal after the clock for displaying one line of character images is finished. Until the operation of After that, a new 16-bit image signal is transferred from the buffer memory 9 to the main memory 15, and this is placed in the 16-bit part of the main memory 15 corresponding to the oldest column of the display. to memory. If 14 character images are to be displayed in one line as shown in Figure 1, the capacity of the main memory 15 is 250 bits per line and 16 lines as shown in Figure 5. All you have to do is display it so that the total is 250 bits x 16 lines = 4000 bits. The period for clocking the main memory 15 is, for example, the 21st to 36th H, which is the image signal transfer period.
The 16H period is the 16H period up to the 227th H period, which is the still image display period.
Only during the display period from the 242nd H to the 242nd H, successive output signals from the main memory 15 are gated and the cathode ray tube 1
6, a still image can be displayed on the cathode ray tube 16 in only one line as shown in FIG. Also, during the transfer period from the 21st H to the 36th H, one vertical column of the image signal is transferred from the buffer memory 9 to the memory location of one column at the right end of each line of the main memory 15 at a rate of 1 bit per 1H period.
Transfer bit data. The transfer pulse is
A transfer pulse is generated at the leading edge position of the 249th bit of the 250-bit display clock per 1H of main memory 1 during the transfer period from the 21st H to the 36th H, that is, at the leading edge position of the 250th bit, which is the rightmost memory position. In the circuit 24, one bit is generated per 1H, and this is added to the buffer memory 9 as a clock to advance the stored contents by 1 bit per 1H.This transfer pulse is also applied to the AND gate 14a to transfer the still image from the buffer memory 9. signal
AND gate 14a, and OR gate 14b.
It is stored here in addition to the final bit position of the main memory 15 via. At this time, the transfer pulse is inverted by the inverter 14c and used for main memory circulation.
In addition to the AND gate 14d, it is shut off at the 250th bit of every H during the transfer period, and the oldest image signal previously stored in the main memory 15 is erased bit by bit along with the new image signal. do. When this image signal is not being transferred, the ND gate 14a is shut off, the AND gate 14d is made conductive, and the readout signal from the main memory 15 is again input to the final bit, thereby circulating the memory contents of the main memory 15. In addition, the image signal data stored in the main memory 15 has just completed one round in the main memory 15 during the transfer period from the 21st H to the end of the 36th H, and then the 227th H, which is the display period. th~th
Add the main clock so that it runs one more time until the 242nd H. In order to perform the above operation, the main clock such as the display clock to the main memory 15 is used during the transfer period from the 21st H to the 36th H, and from the 227th H to the 227th H.
Every H of the 242nd H display period, 250 bits per H are sent from the main clock generation circuit 25 to the main memory 1.
5. Further, 26 is a storage and roll switching circuit, and when a newly received image signal is written to the main memory 15 and stored, the transfer control circuit 13 performs the horizontal synchronization once per field. By shaping the signal or the like to generate a roll pulse and applying it to the clock terminal of main memory 15 as described above, main memory 15 can be rotated in one field over the number of clocks whose contents are cycled exactly an integer number of times. The storage position of the still image signal is sequentially shifted to the left one bit at a time by an extra clock, and the transfer pulse generating circuit 24 generates a transfer pulse as described above to transfer the image signal.
However, when this is done, the still image to be displayed can be displayed by rolling it from the right to the left like an electric sign. On the other hand, when transferring and writing a new image signal to the main memory 15, the transfer pulse generating circuit 19
Transfer pulse generation and transfer control circuit 13 in c
Stop the roll pulse generation. Therefore, when doing this, no new image signals are written to the main memory 15, and the image signals that have been written up to that point are read out repeatedly, so it is not possible to display a still image that does not roll. can. In this way, while transferring the still image signal to the main memory 15 and storing it, or stopping the transfer and reading the still image signal from the main memory 15,
If the mixing circuit 17 mixes the video signal with the normal television image signal and supplies it to the cathode ray tube 16,
As shown in FIG. 1 Y4, a character image that rolls from right to left or a static character image can be displayed superimposed on a normal television image. The above is the basics of the still image receiving apparatus in the horizontal feed method and the vertical feed method. Next, one embodiment of the present invention will be described. First, an example of a still image transmission method used in the present invention will be explained with reference to FIGS. 7 to 9. In the illustrated method, when transmitting by the horizontal feed method, 14 characters are used to transmit 1
The character image of each line is composed of 18 lines (y line) x 16 columns, with each character being decomposed into 18 bits vertically (generally y bits) x 16 bits horizontally (generally x bits). (x column). However, one vertical bit (one column) at the left end of each character is used as a space. Therefore, one line of 14 characters consists of 224 bits. Next, such a one-line character image is divided into N arbitrary blocks in the horizontal direction. In the illustrated example, the characters are divided into 7 blocks of 2 characters each, as shown in FIG. 7, X1. Then, starting from the left block, the image signals of 32 bits per line are extracted by scanning in the horizontal direction from the upper end line in the block as shown by the dashed-dotted line. This operation is performed for each block, and after completing 16 lines of the left block, move to the next right block and repeat. On the other hand, when transmitting using the vertical feed method, as shown in FIG. It consists of 16 horizontal bits (generally x' bits). In this case, the leftmost vertical 1 of each character
Bits (one row) are used as spaces. One line of 14 characters has the same number of bits as in the vertical feed method, which is 224 bits. The method of extracting image signals in the vertical feed method is the same as that shown in FIG. Next, FIG. 8 shows a method for multiplexing the image signal extracted in this way into a television broadcast signal. In this method, as with the conventional method, multiplexing is performed in any one horizontal period during the vertical retrace period.
Here, the data is multiplexed into the 20th H and the 283rd H (hereinafter only the 20th H will be described and the 283rd H will be omitted) and transmitted. In the 20th horizontal period for multiplexing, a total of 224 bits of signals are multiplexed as binary signals in the central portion as shown in FIG. 8A. Setting the total number of bits of signals multiplexed in one horizontal period equal to the number of bits per line of a character image is advantageous in that the circuit configuration for creating various clocks in the receiving device can be simplified. It is something. However, it is not limited to this. The first and second bits of the signal are set to "1" and "0" as a start signal STX. The remaining 222 bits are divided into 6 groups of 37 bits each, and each is assigned to the 6th base program from A to F.
In both the horizontal and vertical feed systems, six programs per field are arranged and transmitted in chronological order. In the 37-bit signal group A to B for each program, code signals for various types of control are multiplexed onto the first 5 bits, and image signals are multiplexed onto the subsequent 6th to 37th bits. The first bit of the code signal is a method identification signal indicating whether the signal is a horizontal feed method or a vertical feed method, and is "1" in the case of the horizontal feed method and "0" in the case of the vertical feed method shall be. 2nd ~
The fifth bit is a control code signal for controlling the storage operation of the receiving device, and is set, for example, as shown in Table 3 below.

[Table] However, the signals in the blank areas in the table are determined according to other control items in the table. Next, the image signals created by the method described above for each program are multiplexed into the 6th to 37th bits of signal groups A to F for each program. In the case of the horizontal feed method, an image signal of 32 bits per line is extracted horizontally one line at a time from the top for each block of character images of each program A to F.
F is multiplexed as shown in FIG. The order of multiplexing is: for the first field, the first line of the block, for the next field, the second line of the block, etc., for the 16th field, the first line of the block.
In the 16th line and 17th field, the first line of the block is multiplexed sequentially from the left block and from the top line within the block. Therefore, one block is transmitted in 16 consecutive field periods, and one line of main character image is transmitted in 112 consecutive field periods. On the other hand, in the case of the vertical feed method, image signals of 16 bits per column are extracted vertically from the left column starting from the character images of the programs A to Y.
As shown in Fig. 8, bits 6 to 21 are multiplexed,
Leave the remaining 22nd to 37th bits blank. The multiplexing order is the first column for the first field, the second column for the next field, and so on, starting from the left column. Therefore, one line of character image is a continuous
224 field. In order to perform double high-speed transmission using the vertical feed method, it is sufficient to multiplex image signals for two columns following the 6th to 21st bits and the 22nd to 37th bits. In this way, by chronologically arranging and multiplexing the image signals of six programs in the same field in both the horizontal feed method and the vertical feed method, the receiving side can immediately receive the image of that program no matter when a program is specified. Signals can be received, and either method can eliminate waiting time. Furthermore, according to this method, in the horizontal feed method, one divided block of a character image consisting of 18 lines is transmitted in 18 field periods, so the receiving side can form two characters of each block in 0.3 seconds. I can do it. In the worst case, if a program is specified during the transmission of the first line of the previous block, the character image of that block will be incomplete, but the next block will be transferred 35 fields after the program specification, or approximately 0.58 seconds. It is possible to form a character image in a complete form, and it is possible to reduce the formation time required to form a readable character image, thereby providing an easy-to-understand display. Note that the entire character image of one line consisting of 7 blocks of 14 characters can be formed in about 2.1 seconds. In addition, in this horizontal feed method, if you want to be able to display a character image of two or more lines with a line spacing on the receiving side, this line spacing is required when the text image is broken down into picture elements on the sending side. should be included as part of the image to be decomposed. for example,
If the character image itself is composed of 18 lines and the space between lines is 8 lines, the total of 26 lines including the space between lines is considered to be one line of character image as shown in Figure 9, and regarding these 26 lines. The image signal may be extracted by scanning each block sequentially in the horizontal direction from above. Therefore, in this case, the image signal of the 8 field period for transmitting the interline pace remains blank. Furthermore, since the number of lines in the image is increased by the space between lines, it goes without saying that the time required for transmission and image formation increases accordingly. Next, the data rate when multiplexing such a binary signal into a television broadcast signal is as follows.
Since it is desirable that the transmission clock can be created using a color subcarrier, the width τ of one bit is 1/τ=c=m/nso, where sc is the color subcarrier frequency and m and n are natural numbers). However, in order to always synchronize the multiplexed binary signal with a fixed positional relationship with the horizontal synchronization signal, m must be an even number, and
Since the last digit of the color subcarrier frequency is "5", it is desirable that n also be "5". Furthermore, considering the frequency characteristics of the television signal transmission system and the amplification and detection circuit systems in the television receiver, it is important to be able to transmit at least the second harmonic component of the highest repetition frequency of the multiplexed signal. Necessary for the reproduction of value signals. In view of these conditions, in this method, the data rate frequency c is set to c=6/5sc=4295.454KHz. With this frequency, the multiplexed signal can be accurately reproduced because even the second harmonic component can be extracted by a broadband television receiver. Also, at this data rate, 1H=
273τ, and as shown in FIG. 8, the 224-bit signal can be multiplexed with a margin before and after it so that it does not overlap with the horizontal synchronization signal or the burst signal. An example of the standard for this method determined as described above is shown in Table 5 below as example standard (1). Note that instead of transmitting six programs in each field, three different programs may be alternately transmitted in each field, and the number of bits per program in one field may be doubled. An example of the standard in that case is shown in Table 5 as standard example (2). Also, let the data rate frequency c be c
Table 5 shows an example of the standard when the number of programs to be multiplexed is increased to 8 types by setting = 8/5sc.
Shown as (3) and (4).

[Table] Next, a receiving device according to an embodiment of the present invention that receives a still image signal transmitted by the method described above and displays a still image will be described with reference to FIGS. 10 to 14. The apparatus of this embodiment is equipped with a storage device capable of displaying two lines of character images including interline spaces as shown in FIG. 1 every time one line of character image is received as shown in
Two lines of character images are displayed while being rolled upward line by line, and when a still image signal using the vertical feed method is received, only one line of character images is displayed while being rolled from right to left as shown in Figure 11. It is something to do. In addition, the device of the second embodiment shown in FIGS. 15 and 16 is designed to display only one line of character images, and in this case, when an image signal by the horizontal feed method is received, the device shown in FIG. One line of character images is displayed each time a vertically moving still image signal is received, and only one line of character images is displayed while being rolled from right to left when a vertically moving still image signal is received. First, the apparatus of the first embodiment will be explained with reference to FIGS. 10 to 14. In this device, the storage capacity of the main memory 15 is
It is possible to display two lines of character images including the space between lines. In this way, if one page of still images covering the entire screen is composed of eight lines of character images, one page can be divided into four by displaying two lines at a time. Also, if one line consists of 14 characters, each character is 16 bits, so the number of bits per line in main memory 15 is
224 bits, and if the space between lines in the case of two-line display is 8 bits and scrolling from bottom to top is smooth, this space between lines must also be included in the memory capacity, so the number of lines is
18+8+18+8=52 lines are required, and in the end, the main memory 15 requires a memory capacity of 52×224=11648 bits. Normal IC memory is
Since it is 1024 bits or an integer multiple thereof, 12 pieces, or
There is plenty of room if you prepare 12K bits. For simplicity now,
It is convenient to select the number of clocks per H to be equal to the number of data that can be transmitted, since the two will match. For convenience of explanation below, the main memory 15 is 224.
Consider bits x 52 lines. (This is possible if it is designed in advance during mass production). First, the display section is set to the first vertical scan of the television signal.
The 52H period from the 197th H to the 248th H is allocated to characters, the next 8H period to spaces, the next 18H period to characters, and the last 8H period to spaces. In the normal operating state, the main memory 15 in FIG. 12 is clocked by 224 bits every H from the 197th H to the 248th H, and the data in the main memory 15 goes around once per field. The clock at that time is shown in FIG. 13x, gated by a gate pulse such as e. The gate pulse e is the Q output of F, F, 31a in the main clock extraction circuit 31, and the main clock f is
This is the output of the AND gate 31b. In this case, if the main memory 15 is configured with a static shift register, data will not be lost even if the clock is stopped from the 249th H to the 459th H and from the 512th H to the 196th H. The extraction and display of still image signals using the horizontal feed method will be described below. First, we will discuss the extraction of each signal, which is completely common to both the vertical and horizontal feed methods. That is, first, the phase is synchronized with fsc by the basic clock generation circuit 6 of the PLL circuit configuration.
Forms the basic clock of 6fsc. That is, 6c is
This is a 6fsc oscillation circuit whose frequency changes depending on the DC control voltage, and 6d is a 1/6 frequency divider circuit whose output is fsc. The phase difference between the outputs of the 1/6 frequency divider circuit 6d and the color subcarrier generation circuit 6 is compared by a phase comparator 6a, and the phase difference (frequency difference) between the two is integrated by 6b.
By removing the high frequency component and amplifying it to form a feedback loop, the oscillation phase of the oscillation circuit 6c is pulled into the phase of the color subcarrier. Next, the oscillation circuit 6
The frequency of the output of signal c is divided by 1/5 by a frequency dividing circuit 23d in the sampling clock generating circuit 23 to form a sampling clock pulse fc. 28a in the clock counter 28 is
As described later, at the 20th H, there is no output from the display clock generation circuit 27, and only the output from the sampling clock generation circuit 23 passes through the OR gate 28a and is added to the 225-bit counter 28b. On the other hand, in the STX detection circuit 18, the start signal
Generate a set pulse for F, F, 23b at the beginning phase of STX to set F, F, 23b,
The output is passed through the NOR gate 23c to the inverter 23d.
tell to. The other input of the NOR gate 23c is the frequency divider circuit 23
It is a 1/5 frequency divided pulse of a, and is a narrow positive pulse. Since the outputs of F, F, and 23b are at a high level at the time of reset, the output of 23c is always at a low level, and therefore the output of 23d is at a high level, clearing the frequency dividing circuit 23a. (If the frequency dividing circuit 23a is cleared at a low level, the inverter 23
d can be omitted). Therefore, after the start signal STX is detected and F, F, and 23b are set,
The output of the NOR gate 23c becomes high level, the output of the inverter 23d becomes low level, and the frequency dividing circuit 2
Frequency division at 3a begins, and a clear pulse (positive polarity) appears every 1/5 frequency division, and self-reset is performed.
Therefore, the phase difference between the start signal STX and the sampling clock pulse output from the frequency dividing circuit 23a is 1/6 _sc.
The sampling pulse near the center of each bit of data can be easily obtained as follows. The clock counter 28b counts 225 sampling pulses and uses its output to reset F, F, 23b and F, F, 27b. Therefore, the width of the 225th output pulse is narrow (approximately
10naec) pulse, which is the integrator circuit 28
c and amplified by the amplifier circuit 28d, the output becomes 224 sampled clock pulses fc. On the other hand, in the program selection clock generation circuit 22, 22a is a program sampling gate forming circuit, which in this case is formed of six F, F, and the 1st to 37th bits corresponding to the program shown in FIG. The gate pulse A is at a high level until A (width of 37 bits from the beginning of the 3rd bit to the beginning of the 40th bit when counted by fc), and the 38th to 74th bits corresponding to the B program are at a high level. A gate with a width of 37 bits is formed from a to a, which corresponds to the program. on the other hand,
The selector 22b selects one of the gate pulses a to a according to a 3- to 4-bit program code that is manually specified. For example, when program A is specified, select a.
Inform MND gate 22c. Note that the selector 22
b may be constituted by a mechanical switch so that only the switch of the designated program is made conductive. When the code signal sampling circuit 29 specifies a program, 37 sampling clock pulses as shown in FIG. 29a (serial input, parallel output type) and OR gate 30. Since the other input to the OR gate 30 is the transfer clock pulse that appears when data is transferred from the buffer memory 9 to the main memory 15, at the 20th H, only the output of the AND gate 22c is the buffer memory 9 consisting of a 32-bit shift register. added to. Since the buffer memory 9 and the shift register 29a are connected in series, they can be thought of as a 37-bit memory in total, and when clocked with the 37-bit sampling clock pulse output from the AND gate 22c, 5 bits of the code signal are transferred to the shift register. 29a and the remaining image signal 32
The bit enters the buffer memory 9. Among the 5-bit output of 29a, the first bit is the first bit shown in FIG. , First of all, this is the vertical/horizontal discrimination circuit 2
9b, the output is 1, and a horizontal feed signal is received. The 3rd, 4th, and 5th bits of the other 4 bits output from the shift register 29a
The first bit determines the position of the data on the screen, that is, the block, and the second bit being "1" indicates that it is not a code signal for controlling the operation mode. The block selector 32 in the transfer clock pulse generation circuit 32 selects the 3rd, 4th, and 5th bits (which may include the 2nd bit).
Supply to b. Block designation pulse generation circuit 32
a consists of seven F, F, forming seven pulses each having a width of 32 bits, block gate pulses C to C in FIG.
The 3rd, 4th, and 5th bits of the table are used to determine the block number from the left end, and the shift register 29a
select a gate pulse at a defined position according to the output of When the received signal is in the shape of an
The output of 2b becomes a 32-bit wide game pulse as shown in FIG. 13C. On the other hand, at times other than the 20th H, the output of the inverter 27d in the display clock generation circuit 27 is at a high level, so the F, F, and J terminals of 27b are at a high level and can be set, and are set by the output of the delay circuit 27c. . The delay circuit 27c is a pulse circuit that delays the horizontal synchronizing signal so that the oscillation start timing of the display clock oscillation circuit 27a is at an appropriate position to the left of the screen of the cathode ray tube 16, and is a monostable multivibrator. Just use it. When F, F, 27b are set at the rising position of the gate pulse in the display section e in Fig. 13, with a slight delay from the trailing edge of the horizontal synchronizing signal, the Q output is at a high level as shown in Fig. 13e. An oscillation circuit 27 consisting of a gated oscillator
a begins to oscillate. The oscillation frequency is arbitrary, but
From the aspect ratio of characters displayed on the cathode ray tube 16,
In the case of 16 bits vertically x 16 bits horizontally, around 7MHz, vertically
In the case of 18 bits x 15 bits horizontally, around 6MHz is appropriate, and here we will set it to 6MHz. The output of the oscillation circuit 27a is transmitted to the counter 28b via the OR gate 28a. On the other hand, since STX is not detected other than the 20th H, F and F23b are not set, and from the 21st H,
It remains at a high level, the output of the inverter 23d also becomes a high level, and the 1/5 frequency divider circuit 23a counter remains cleared. The counter 28b outputs the output of the oscillation circuit 27a.
Assuming a 225-bit count, F, F, 27b are reset, the Q output becomes low level, and 27a
oscillation stops. Therefore, as in the case of the 20th H, the 225th output from 28a becomes a thin pulse, and the output from amplifier circuit 28d becomes a display clock pulse of 224 bits per H. The same operation continues until the 282nd H of the next field. That is, every H224 bit pulse appears as the output of the clock counter 28. On the other hand, in the transfer clock pulse generation circuit 32,
As mentioned above, the gate pulse C in FIG. 13 is applied to the AND gate 32c, and the output is applied to the AND gate 34a in the transfer buffer memory clock generation circuit 34, and the output is applied to the AND gate 34a in the transfer buffer memory clock generation circuit 34. Output C is applied to AND gate 35a in input switching pulse generation circuit 35. Next, considering the clock of main memory 15,
When image signals are not transferred, two lines of characters are fixedly displayed at the bottom of the screen.
The clock is clocked during the 52nd H of the 248th H, and the number of clocks per H is 224 bits. Of these, space is
These are the 8H periods of the 215th to 222nd H and the 241st to 248th H.
F, F, 31d in the main clock extraction circuit 31
is line counter (horizontal pulse counter) 12
It is set and reset at the beginning of both the 197th H and 249th H pulses taken from
By forming the AND of the Q output and the output of the clock counter 28 using the AND gate 31b,
The output of the AND gate 21b is 52H for the 197th to 248th H.
During this period, a 224-bit clock pulse as shown in FIG. In this case, the capacity of the main memory 15 is
Since it is 224 bits x 53 lines, when clocked with the above clock pulse, the stored contents go around once for each field. Memory capacity is nH
For the minute, it is enough to clock 224×n times, F,
This can be easily achieved by setting F, 31a at the beginning of the (249-n)Hth and resetting it at the beginning of the 249thH. Next, regarding data rewriting, if we consider the time other than immediately after specifying a program or turning on the power switch, we can always receive the codes such as line feed, page break, beginning of line, clear two lines, etc. in Table 4. (Set in advance to send only the code to 20H of the first field without any signal). 1,5 from the left of A program between 8+18 fields after the line feed signal
A signal for one character of the block is sent. The first 8 fields have no signal. So the 10th
It is sufficient to change the state shown in FIG. A to the state B within 8 fields. In this case, since graphics are not handled, there is no need to store data in the memory between the 8 fields of space. The new line signal is 14 from the left of the previous line
It is inserted in 20H of the next field of the 18th line signal of the nth character (or the nth and final character), and this is inserted into the forward scroll gate generation circuit 36.
It is detected by the line feed code detection circuit 36a (combination of NAND gate and inverter) inside, and the 26H counter 36
Start operating b. On the other hand, F, F, 36a are output from the line counter 12 and are set at the beginning of the 249th H and reset at the beginning of the 253rd H, so their Q outputs are at a high level for 4H from the 249th to 252nd H. , which is transmitted to AND gates 36p and 31e. The AND gate 36d gates the horizontal synchronizing signal (the thin pulse of the 253rd H is integrated by the integrating circuit 36f) and every field 4H.
The minutes are transmitted to the counter 36b. Therefore, an output with a width of 4H can be obtained for each field. However, after counting 24H in a 4H width up to the 6th field, including the field where the line feed code was detected, the 7th field has a total of 26H up to 2H, so the output of the counter 36b is reset to a low level. The output of the AND gate 36e ends up being at a high level for 26H over 7 fields, and the AND gate 25b in the main clock synthesis circuit 15 performs an AND with the clock of 224 bits every H, and the data in the main memory 15 is stored. 26H
Scroll from bottom to top by (line). (7
(Carry up by 26H between fields). After scrolling, it will look like Figure 10B. After one more field of no signal, the signal shown in FIG. 8 is received. Therefore, No. 223H
New data is written during the 18H period between the 240th and the 240th hours as shown in FIG. 10C. For this purpose, the data in the buffer memory 9 is
It is necessary to determine whether it is a line or not. The purpose of the transfer line pulse generation circuit 33 is to once store a code indicating a block of characters in a latch memory 33a, and in the next field compare it with the code signal stored in the shift register 29a in a block code comparison circuit 33b. . Therefore,
The character code signal of the 1st and 2nd blocks (see Table 4) Another code is sent in the field immediately before “1001” is sent.
Let y ₁ , y ₂ , y ₃ , y ₄ be stored in the latch memory 33a, and they do not match.
The field counter 33C is reset, and the field counter 33C is reset to the first value of each field from then on.
The beginning of the 223rd H is counted based on the output from the line counter 12. Therefore, the data of the first line of the characters of the first and second blocks is received in the first field.
At the 223rd H, the output of the counter 33C is "00001", and on the other hand, the 18 line counter 33d is set to count the trailing edge of the horizontal synchronization signal from the beginning of the 223rd H of each field, and in this field, at the 223rd H Only when the output of the counter 33C and the output of the counter 33d match, the output of the line comparison circuit 33a is at a high level for only 1H, and is applied to the AND gates 34a and 35a, and the logical product with the AND gates 32b and 32c is formed. is the 223rd H
Transfer clock d only between C in Figure 13
The output of the AND gate 35a is connected to the inverter 14c of the input gate circuit 14 and the AND gate 1 through the OR gate 35c.
4a to block AND gate 14d,
AND gate 14a is made conductive, and the contents of buffer memory 9 are transmitted and transferred to main memory 15. In the next field, the 224th H (correctly 223
+263+1 = 487th H, but the 283rd H field will also be explained by replacing it with 20H), and the counter 3
The outputs of 3C and 33d match, and 32 on the second line
A bit image signal is transmitted from buffer memory 9 to main memory 15. Similarly, 18 lines x 32 bits of character data of the first and second block I are transferred to the main memory 15 between 18 fields. At the 19th field, the comparison circuit 33b detects a change in the code signal again, and the field counter 33
Clear c, and the 19th field signal is the 1st
The signal is transmitted from the buffer memory 9 to the main memory 15 by the clock d next to d in FIG. below
It is exactly the same up to the 13th and 14th block, and 18
x7 = 126 fields, 14 characters per line are written. A new line code is sent to the next field without any signal, and the process is repeated. By the way, when the code signal changes every field or is not sent, there is a chance that the output of the shift register 29a and the output of the block code memory 33a coincide with each other.
Since no output appears, AND gate 34a,
35a is shut off and there is no malfunction. Also, during horizontal feed, the output of the shift register 29b is at a high level (29b should be a re-triggerable multi-channel, and the pulse width should be 1 field or more).
Therefore, AND gates 34a, 35a, 25
is conductive, and the output of the inverter 29c is at the resistance level.
AND gates 34b and 35b are blocked.
Note that the AND gate 3 in the memory circulation control circuit 37
7a is horizontal feed, and when the scroll clock gate pulse appears as the output of AND gate 36e, the output becomes high level, and OR gate 37b,
Since the data is added to the AND gate 37d for clearing via the AND gate 37f and the NOR gate 37c, the AND gate is blocked during the 26H period when scrolling is performed, and the data between the 197H and 223H in FIG. 10A is A total of 26 hours, including 18 hours and 8 hours of subbase, are cleared. To explain this further, the first field of the scroll is clocked by 224 bits x 4 lines in addition to the normal 224 bits x 52 lines, and during this time the AND gate 37 is clocked.
Since d is blocked, the original 197H to 200H image signals (these are referred to as a ₁ to a ₄ , and hereinafter the signals up to the 222H are referred to as a _26. Also, the signals from the 223H to the 248H b ₁ , b ₂ ...b ₂₆ ) vanish, and the second
At the beginning of the th field, the order of the data in main memory is a ₅ , a ₆ ... a ₂₆ , b ₁ ... b ₂₆ followed by the 242nd ~
There is no signal for the 246th 4H period. 1 below in order
There is no signal for 4H for each field, and the memory position advances by 4H, and after 7 fields (after scrolling for 26H), the state is as shown in FIG. 10B. Next, considering the time when the power switch is turned on, the program is switched on, and the time is specified, it is assumed that the signal shown in Figure 8 is received in the first 20th hour after the program is switched on or the power switch is turned on. For example, since the 4-bit latch memory 33a is "0000", the code signals do not match, and the field counter 33c is cleared.
Despite the data on the nth line, it is stored in the memory at the position of the first line, and the next 3 and 4
Returns to normal from the data of the th block character. However, this is only two characters, and is much less serious than the conventional method of sending one line at a time, where only half of all 14 characters in one line would be displayed. Next, the auxiliary functions of this receiver will be explained. When transmitting text information from a broadcasting station, you may want to erase the previous information or display it for a long time, and the receiving side also has the same request, so these functions are
Both automatic and manual methods are required. First, when you want to stop (retain) the displayed content, enter “0011” in the 2nd to 6th bits of the fourth table from the sending side.
When the code signal is sent, this is sent to shift register 2.
9a, and detected by a decoder constituting the stop detection circuit 26a in the memory roll switching circuit 26, the output of the stop detection circuit 26a becomes low level,
Since the AND gate 25b is cut off via the AND gate 26b, the scroll clock which is the output of the OR gate 25c is no longer transmitted to the OR gate 25b, and the roll is stopped. This can be instructed independently for each program from A to F. In addition, the other inputs of the AND gate 26b can be set to a low level by manual switching, so the AND gate 25b can be set to a low level by manual switching.
It is also possible to stop the roll by blocking d.
Also, the output of the AND gate 26b is the output of the AND gate 37
f, and when the roll is stopped, even if the rewriting pulse is applied to the input gate 14,
AND gate 14a is shut off, and OR gate 35c is
Regardless of the output of , the NOR gate 14c is set to a high level and the AND gate 14d is made conductive to hold the stored image signal in the main memory 15. Next, clearing the display contents will be described. The clear signals include the page break code signal and the 2-line clear code signal shown in Table 4, which are detected by the page break clear code detection circuit 37e, and the stop code detection circuits 26a and 37e are detected by a binary decimal decoder. (If configured, a common IC can be used) When a clear signal is detected, its output becomes a high level and is transmitted to the AND gate 37f via the OR gate 37b. When the output of the AND gate 26b is at a high level, that is, the memory contents are not retained, the AND
The output of gate 35f becomes high level, and the output of NOR gate 37c becomes low level, cutting off AND gate 37d. Since the output of 37e remains at a high level for one field (no change until the next 20th H), the contents of the main memory 15 are all cleared during that time. On the other hand, manual clearing
By setting the other input of the NOR gate 37c to a high level, it can be cleared regardless of the output of the NOR gate 37e, and it can be cleared even if the output of the AND gate 26b is in a memory content retention state, that is, at a low level. In addition,
The AND gate 37a is inserted so that the roll clock gate pulse (output of the AND gate 36e) is transmitted to the OR gate 37b only during horizontal feed mode reception. Next, vertical feed type reception will be described. In the case of vertical sending method reception, the vertical/horizontal discrimination circuit 29b
The output of the inverter 29c becomes a low level, and the output of the inverter 29c becomes a high level. Operation of selecting a program to be received and writing it to buffer memory 9 and main memory 1
5 and the like are exactly the same as in the case of horizontal feed method reception. The method of extracting the image signal and transferring it to the main memory 15 written in the buffer memory 9 is as described in the explanation of FIG.
Just rewrite bit by bit. First, go to the buffer memory 9 from 6 to 37 in Y in Figure 8.
The 32nd bit of the bit is extracted and written, but
Normally, the 22nd to 37th bits, 16 bits, have no signal. Therefore, it is sufficient to transfer the 6th to 21st bits. In the previous explanation of the circuit shown in Figure 5, data transfer was explained.
This is done at the 266th bit, but since the capacity of one line of the main memory is 224 bits this time, if it is done at the end of 1H, that is, at the 224th bit as shown in the transfer pulse h in Figure 14. Typically, the transfer pulse h is a 225-bit clock counter 28 in FIG.
It is easier to obtain than b. On the other hand, since the output of the inverter 29c in FIG. 12 is at a high level, the AND gates 34b, 35b, 38
On the other hand, since the output of the vertical/horizontal discrimination circuit 29b is at a low level, the AND gate 34 becomes conductive.
a, 35a, 25a are cut off. First, at the 224th bit of the 20th H, a clock pulse as shown in FIG.
As a result, the entire image signal in the main memory 15 is shifted to the left one bit at a time. This is the same as the case in FIG. The transfer pulse appears while the output of the clock counter 28b exists, that is, over the entire one field, but it is
If formed with AND gate 35b, OR gate 35
The output of c is from 225th to 240th H as shown in Figure 4 j.
16 items appear in 16 hours. This is used for actual rewriting. F, F, 39a are set at the beginning of the 225th H by the output from the line counter 12, as shown in FIG. 12, and reset at the beginning of the 241st H, and the Q output is as shown in FIG. 14k. j is the rewriting pulse, and the AND gate 14 is activated at the 224th bit of the clock of the main memory 15 over the 225th to 240th hours.
d is cut off, AND gate 14a is made conductive, and only one bit of the image signal of the contents of buffer memory 9 is transferred to main memory 15. At the 226th H, which follows the 225th H, the rewriting pulse J shown in FIG. 14 is transmitted to the buffer memory 9 via the AND gate 34b and OR gates 34c and 30, so the contents of the buffer memory 9 are shifted by 1 bit, and the output is The 7th bit of Y in Figure 8 appears, and this is the 226th H.
The 224th bit is transferred to the main memory 15. If you repeat this, at the end of the 240th K, Figure 8 Y
The 16 bits from the 6th to 21st bits will be inserted in a vertical column at the right end of the screen, replacing the oldest data in this part. Therefore, the display advances one vertical column to the left. This is the same as the general example of the vertical feeding method described above. In the example shown in Fig. 12, there is a main memory capacity for two lines compared to the previous example, but only the 16H period from the 225th to the 240th H is used for display, and the AND gate 40 is used for the other parts. If you gate the output of the main memory 15 without displaying it on the screen, the main memory will be clocked by 224 bits for each field x 52 lines, similar to the horizontal feed method, and shifted once at the 20th H. good. If it were to be displayed, there would be no space between the two lines above and below, the number H of reading comprehension patterns would be displayed above it, and the two lines above and below would be displayed.
The lines move to the left at the same time, making the screen difficult to read. The circuit operation when manually stopping (holding) when a stop signal is detected is exactly the same as when receiving in the horizontal feed method. When switching between the horizontal feed method and the vertical feed method on the transmitting side, it is sufficient to send a clear signal to erase the displayed content. In the case of the vertical feed system, it is possible to transmit and receive 32 bits per program in 1H, so it is possible to transmit and receive at twice the speed. That is, when sending quickly, the line start code signal in Table 4 (unnecessary as it has the same meaning as line feed) is read as fast forward, and the 223rd and 224th bits are used to rewrite from the buffer memory 9 to the main memory 15. 20H No. 223, 224
If the bit is shifted by 2 bits at a time, the displayed characters will move to the left by 2 columns per field. These changes can also be easily and automatically performed. Also, when fast forwarding, it is sufficient to use the stop signal together with the transmission and adjust the reading speed to about 3 characters per second.
Fast-forwarding is convenient when used to explain screen content (dialogue in dramas, etc.). Although the first embodiment of the present invention has been described above,
There are many other ways to choose the transmission standard, but once the number of programs to be transmitted is determined under the limitations of character display speed, or reading and comprehension speed, the time required to complete one line and the number of characters that can be read are determined. This is a requirement that contradicts the waiting time until it appears, and if one character is completed in 16 to 31 fields including the waiting time, one line (14
), it takes about 4 seconds to complete, and as the number of programs increases, the waiting time will increase to (number of programs) x (time to complete one line + space) even if 16 to 18 fields can be completed to complete one line. Become. A few examples other than those mentioned above are shown in Table 4 above. Another feature of the present invention is that the total number of bits of the transmitted signal (including the code) and the number of display bits per 1H on the receiving side can be made equal, thereby simplifying the circuit. Of course, there is no difference even if they are not chosen equally. Also, since the maximum number of characters per line can be arbitrarily determined, short sentences can be broken quickly. every field
There are 2 characters per 1H and 1 program, but in the case of characters 1 to n out of 14 characters (or 16 characters) per line, if the remaining characters are not sent, the next one will be sent as quickly as {(14-n)/2} x 18/60 seconds. line. Also, if you decide in advance, one line can be made up of characters other than 14 or 16. Further, as is clear from the embodiments, the main memory, buffer memory, clock generation circuit, etc. can all be used in common by simply adding a flip-flop and some gates to the lateral feed receiving function. In addition, as main memory,
Needless to say, it is possible to display an arbitrary number of lines of character images by using a device with a larger capacity. Although the above embodiment displays a plurality of lines of character images, FIG. 15 shows an embodiment including a main memory having a capacity to display only one line of character images. In this embodiment, the main memory 15 is
It has a storage capacity for 18 lines, or 224 x 18 = 4032 bits, and the flip-flop of the display clock extraction circuit is set and reset by the 223rd and 240th line counter outputs.
From the 223rd H to the 240th H, a display clock of 224 bits per 1 H is output from the AND gate. Furthermore, since this device does not require a carrying operation, it does not include a circuit for this purpose. Other configurations and operations are similar to those of the first embodiment, and when a still image signal of the horizontal feed method is received, a still character image is displayed as shown in FIG. When a signal is received, a one-line character image that rolls from right to left is displayed as shown in FIG. 16Y. Furthermore, the above explanation has all been about the case where a character image is transmitted and displayed as a still image.
It goes without saying that the present invention can be applied to any other still images such as figures. As described above, the still image receiving device of the present invention divides still images of a plurality of programs into a plurality of blocks in the horizontal direction, and scans each block sequentially in the horizontal direction starting from the upper line starting from the left block. a receiving circuit that extracts image signals from a plurality of programs, arranges the image signals of a plurality of programs in chronological order, and receives still image signals that are multiplexed onto the vertical retrace line of the same field of a television signal and is transmitted; A buffer memory for temporarily storing only signals of programs desired to be received; a main memory for storing image signals transferred from the buffer memory in a predetermined order suitable for display; and a main memory for reading out the image signals from the main memory. and a display means for displaying a plurality of lines of still images, and a display means for discriminating a block code signal attached to the still image signal to determine which one of the plurality of blocks the image signal belongs to and the corresponding one. This method is characterized in that it identifies what line it is from the top of the block, and uses this identification output to transfer the image signal in the buffer memory to a predetermined storage location in the main memory. Still images of the forwarding method can be received and displayed without waiting time after the program is specified. In addition, the circuit configuration can be simplified by making it possible to receive both horizontal-feeding still image signals and vertical-feeding still image signals with the same clock.Furthermore, when displaying multiple lines, the clock is incremented one line at a time. Since it is displayed, it is also possible to display multiple lines that are easy to understand.

[Brief explanation of the drawing]

Figure 1 X1, X2, X3, X4, Y1, Y2,
Y3 and Y4 are principle diagrams for explaining the conventional still image transmission method, Fig. 2 is a waveform diagram of still image signals by the conventional horizontal feed method, and Fig. 3 is a conventional still image receiving device for the same method. Figures 4a and b are waveform diagrams of still image signals using the conventional vertical feed method, Figure 5 is a block diagram of a conventional still image receiving device for the same method, and Figure 6 is the same device. Detailed circuit diagram of main memory part of Figure 7, X1 and Y1
is a principle diagram for explaining the still image transmission method used in the present invention, FIG. 8 A, B, X, and Y are waveform diagrams of still image signals according to the same method, and FIG. 9 is a still image signal with line spacing according to the same method. 10A, B, C and 11 are front views showing the display mode of a still image receiving device according to an embodiment of the present invention, and FIG. 12 is a principle diagram for explaining the image transmission method. Circuit diagram showing the configuration of the device, Figure 13 A, a, a
B, a, b, b, B, C, d, e, f and Fig. 14 g, h, i, j, k, l are waveform diagrams for explaining the operation of the same device, Fig. 15 The figure is a circuit diagram of a still image receiving device in another embodiment of the present invention,
FIG. 16 is a front view showing the display mode of the device. 1... Receiving circuit, 2... Synchronization separation circuit, 3...
Horizontal oscillation circuit, 4... Vertical synchronization separation circuit, 5...
Subcarrier oscillation circuit, 6... Basic clock generation circuit, 7... Clock counter, 8... Still image signal extraction circuit, 9... Buffer memory, 10...
Program code extraction circuit, 11...Line program signal extraction circuit, 12...Line counter, 13...Transfer control circuit, 14...Input gate, 15...Main memory, 16...Cathode ray tube, 17...Mixing circuit ,
18... Start signal detection circuit, 19... Control signal generation circuit, 20... Waveform shaping circuit, 21... Sampling pulse generation circuit, 22... Program selection circuit, 23
... Reception clock generation circuit, 24 ... Transfer pulse generation circuit, 25 ... Main clock generation circuit, 2
6... Memory/roll switching circuit, 27... Display clock generation circuit, 28... Clock counter, 29
...Code signal extraction circuit, 30...OR gate,
31...Main clock extraction circuit, 32...Block pulse generation circuit for transfer, 33...Line pulse generation circuit for transfer, 34...Buffer memory clock generation circuit for transfer, 35...Input switching pulse generation circuit, 36 ...Advancing scroll gate pulse generation circuit, 37...Memory circulation control circuit, 38...
... Roll pulse generation circuit, 39 ... Gate pulse generation circuit for one-line display, 40 ... AND gate.

Claims (1)

[Scope of Claims] 1. A still image of a plurality of programs is divided into a plurality of blocks in the horizontal direction, and image signals are extracted by sequentially scanning each block in the horizontal direction from the upper line starting from the left block. A receiving circuit that receives still image signals that arrange the image signals of a plurality of programs in chronological order and multiplex them on the vertical retrace line of the same field of the television signal and transmits the same, and A buffer memory that temporarily stores only the program data, a main memory that stores the image signals transferred from the buffer memory in a predetermined order suitable for display, and a still image of multiple lines by reading out the image signals from the main memory. and display means, and determines the block code signal attached to the still image signal to determine which of the plurality of blocks the image signal belongs to and which line from the top of the block. A still image receiving device characterized in that the image signal in the buffer memory is transferred to a predetermined storage location in the main memory based on the identification output. 2. In the circuit that controls the transfer of the image signal, the block code signal attached to the image signal of the program desired to be received is compared with the block code signal received one time before for the program, and it is determined whether the two signals are different. 2. The still image receiving device according to claim 1, wherein the still image receiving device identifies the top line of the still image when the line reaches the top line of the still image. 3. In the horizontal feed method, still images of multiple programs are divided horizontally into multiple blocks, and each block is sequentially scanned horizontally from the upper line starting from the left block to extract image signals. The image signals of these multiple programs are arranged in chronological order and multiplexed in the vertical retrace interval of the same field of the television signal. a receiving circuit that receives a still image signal transmitted by scanning to extract an image signal, arranging the image signals of a plurality of programs in chronological order and multiplexing them in the vertical retrace period of the same field of a television signal; , a buffer memory for temporarily storing only those of the desired program among the received still image signals; a main memory for displaying and storing the image signals transferred from the buffer memory in a suitable predetermined order; display means for reading out the image signal and displaying a still image, and storing image signals from the horizontal feeding method and the vertical feeding method in the buffer memory using a common clock circuit; The discrimination code signal attached to the still image signal is discriminated to identify which method the signal is, and when it is determined that it is the horizontal feed method, the block code attached to the still image signal is The image signal is discriminated to identify which of the plurality of blocks the image signal belongs to and which line of the block it belongs to, and based on this identification output, the image number in the buffer memory is stored in the main memory. When the image signals are transferred to a predetermined storage position in the main memory and it is identified that the vertical feeding method is used, the storage positions of the image signals in the main memory are sequentially shifted according to the identification output, and the image signals are transferred from the buffer memory to the storage position at the end. A still image receiving device characterized by transferring an image signal. 4. Receive a still image signal in which image signals from a horizontal feed method and a vertical feed method are mixed and multiplexed in the same field of the television signal, and the discrimination signal is added to all the image signals; Still image according to claim 3, characterized in that the transfer operation for both the horizontal feed and the vertical feed is switched by determining a discrimination signal attached to the image signal of the program desired to be received. Signing device. 5. Both the horizontal feed method and the vertical feed method receive the still image signal transmitted using the same data sheet, and the image signals of both methods are stored in the buffer memory using the same reception clock. A still image receiving device according to claim 3 or 4. 6. In the above-mentioned vertical feed method, receiving a still image signal for high-speed transmission in which image signals for two or more vertical columns of still images of the same program and their code signals are multiplexed in the same field, and transmitting the above-mentioned code signal. Claims 3, 4 or 4, characterized in that the transfer speed of the image signal from the buffer memory to the moin memory is increased by the identification signal that identifies the still image, and the display speed of the still image is increased. The still image receiving device according to item 5. 7 In the circuit that controls the transfer of the image signal using the horizontal feed method, the block code signal attached to the image signal of the program desired to be received is
compared with the previously received block code signal,
7. The still image receiving device according to claim 3, 4, 5, or 6, wherein the still image is identified as the top line of the still image when the two are different. 8 In the horizontal feed method, still images of multiple programs are divided into multiple blocks in the horizontal direction, and the image signals are extracted by sequentially scanning each block in the horizontal direction starting from the upper line, starting from the left block. The image signals of these multiple programs are arranged in chronological order and multiplexed in the vertical retrace interval of the same field of the television signal. a receiving circuit that receives a still image signal transmitted by scanning to extract an image signal, arranging the image signals of a plurality of programs in chronological order and multiplexing them in the vertical retrace period of the same field of a television signal; , a buffer memory that temporarily stores only those of the desired program among the received still image signals, and a buffer memory that stores the image signals transferred from the buffer memory in a predetermined order suitable for display, and a plurality of lines of the still image. a main memory having a storage capacity of 1,000 yen, and a display means for reading out the image signal from the main memory and displaying a plurality of lines of still images,
The image signals from the horizontal feed method and the vertical feed method are stored in the buffer memory using a common clock circuit, and the discrimination code signals attached to the still image signals of the horizontal feed method and vertical feed method are discriminated. When it is determined that the still image signal is a horizontal feed method, the block code signal attached to the still image signal is determined to determine whether the image signal is one of the plurality of blocks mentioned above. and what line from the top of the block it is on is identified. Based on this identification output, the image signal in the buffer memory is transferred to a predetermined storage location in the main memory, and the still image is transferred to a predetermined storage location in the main memory. When a line feed code signal is detected, the image signal in the main memory is advanced by the number of bits corresponding to the total line of one still image line and the interline space until the next line of still image is received, and after this advancement, The above image signal is transferred to the bottom row of the screen to display multiple lines of still images on the cathode ray tube via the space between the lines, and when it is identified that the vertical feed method is used, the above The image signal from the buffer memory is stored in the storage position at the end while sequentially shifting the storage position of the image signal in the main memory, and only one line of the image signal is read out from the main memory and stored in one line on the cathode ray tube. A still image receiving device characterized by displaying only a still image. 9. A display clock added to the main memory in order to read the image signal from the main memory and an advance clock added to the main memory in order to advance the storage position of the image signal in the main memory are connected to the same clock. 9. The still image receiving device according to claim 8, wherein the still image is generated by a generating circuit. 10. The still image receiving device according to claim 9, wherein a gated oscillator that oscillates during the readout period and the advance period is used as a generating circuit for the display clock and the advance clock. . 11 Receive a still image signal in which image signals of the horizontal feed method and the vertical feed method are mixed and multiplexed in the same field of the television signal, and the above discrimination code signal is added to all the image signals. Claims 8 and 8 are characterized in that the transfer operation for the horizontal feed method and the vertical feed method is switched by determining a discrimination code signal attached to the image signal of the program desired to be received. Section 9 or 1st
Still image receiving device according to item 0. 12. Still image signals of the horizontal feed method and the vertical feed method are both transmitted at the same data rate, and the image signals of either method are stored in the buffer memory using the same reception clock. Claims 8 and 9
The still image receiving device according to item 10, item 10, or item 11. 13 In the above vertical feed method, receive a still image signal for high-speed transmission in which image signals for two or more columns of still images of the same program in the vertical direction and their code signals are multiplexed in the same field, and transmit the above code signal. Claims 8 and 9 are characterized in that the transfer speed of the image signal from the buffer memory to the main memory is increased by the identification signal that identifies the still image, and the display speed of the still image is increased. 10th
12. The still image receiving device according to item 11, item 11, or item 12. 14 In the circuit that controls the transfer of the image signal in the horizontal feed method, the block code signal attached to the image signal of the program desired to be received is compared with the block code signal received one time previously in the program; Claims 8, 9, 10, and 11 are characterized in that when both signals are different, it is identified as the top line of the still image.
The still image receiving device according to item 1 or 12.