JPS6134623B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a speed detection device for a moving object such as a high-speed vehicle, and in particular detects the input time interval of position pulses generated every time the moving object moves a certain distance to determine the passing time. The present invention relates to a speed detection device for determining and detecting the speed of a moving object.

A conventional device of this kind is shown in FIG. The input position pulse signal is a three-phase signal with an electrical phase shift of 120 degrees, and this is converted into a single-phase signal with noise removed by a rationality check that includes the phase. Count the signals and convert them into distance traveled. At the same time, the moving time corresponding to the moving distance is determined from the difference between the input absolute times of the position pulses, and the speed is calculated from this moving time and the converted moving distance. These calculations and the detection of the position pulse input absolute time are performed by a calculation control device, which has the drawback of causing errors in speed detection due to operational delays that occur as the control load of the calculation control device increases.
This will be explained in detail below.

The input absolute time of the position pulse signal taken out from the position pulse input section 1 of the control circuit A through the rationality check section 2 of the calculation control device B is determined by the speed calculation time reading section 3 operating when the position pulse signal is input. As a result, the absolute time of the time counter 12, which will be described later, is read out and sequentially set in the speed calculation time register 4. The absolute time that is sequentially updated and set in the speed calculation time register 4 for each position pulse is:
The data is read into the time width detection section 5. Time width detection section 5
is the speed calculation reference time set in the speed calculation reference time storage section 6, the past absolute time set in the speed calculation time storage section 8 through the speed calculation time storage control section 7, and the current time read from the register 4. The difference from the absolute time (referred to as time width) is compared. In this comparison, on the condition that the above-mentioned time width is larger than the speed calculation reference time, the time width detection section 5 gives the above-mentioned time width to the speed calculation section 9, and at the same time operates the speed calculation time storage control section 7 to store it. Register 4 in part 8
The position pulse input absolute time is given to update the contents of the storage unit 8. Further, the time width detection section 5 outputs the distance data set in the position pulse counter 10 to the speed calculation section 9, and resets the counter 10. The speed calculation unit 9 divides the distance data by the time width to calculate the speed.

Now, the absolute time setting in the register 4 using the position pulse of the rationality check section 2 is performed by controlling the time reading section 3 using the position pulse to set the contents of the time counter 12 that counts the clock of the clock pulse generation section 11 provided in the calculation control device B. Let's do it.

Therefore, if the response of the speed calculation time reading section 3 corresponding to the input of the position pulse signal is delayed, the output of the clock pulse generating section 11 causes the clock counter 1 to
There was a drawback that the contents of 2 did not change and the correct absolute position pulse input time could not be obtained.

Figure 2 shows this situation.

In FIG. 2, clock pulses are generated at regular intervals, and the absolute time of the time counter is the sum of the number of generated clock pulses. Assuming that the input absolute time of position pulse P ₁ is T ₁ as shown in Fig. 2, if the speed calculation time readout R ₁ corresponding to position pulse P ₁ is delayed, the value detected as the speed calculation time will be T ₁ The result is something like +2. Assuming the speed V ₁₁ and moving distance D obtained from this result, V ₁₁ = D/T ₁ − T ₀ +2 ………(1) Also, assuming the correct speed V ₁ , V ₁ = D/T ₁ − T ₀ ……………(2) Therefore, the detected speed deviation ΔV ₁ is ΔV ₁ =V ₁₁ −V ₁ =−V ₁ 2/T ₁ −T ₀ +2……(3) .

Further, after this happens, assuming that the delay in the speed calculation time readout _R4 with respect to the position pulse input _P4 in FIG. 2 is sufficiently small, the speed calculation time becomes _T4 .

The speed V ₄₁ obtained from this result is, if the moving distance is set as D for convenience, V ₄₁ = D/T ₄ − T ₁ −2 …(4) The correct speed V ₄ at this time is V ₄ = D/T ₄ −T ₁ …………………(5) Therefore, the detection speed deviation ΔV ₄ is ΔV ₄ =V ₄₁ −V ₄ =V ₄ 2/T ₄ −T ₁ −2 …… ...(6) As mentioned above, if there is a delay in reading the speed calculation time only once, the deviation of the detected speed will occur twice (Δ
V ₁ and ΔV ₄ ), which becomes a speed detection error.

The delay in speed calculation time readout increases in frequency in proportion to the control load of the calculation control device, and becomes significant in a high speed range where the number of position pulse inputs increases.

An object of the present invention is to provide a speed detection device that does not cause a speed detection error even if a delay occurs in speed calculation time reading.

The present invention detects the position pulse input absolute time at the same time as the position pulse input and holds this until the next position pulse input, so that even if there is a delay in reading the speed calculation time, the speed calculation time detection result This is done so that it does not change.

FIG. 3 shows the configuration of an embodiment of the present invention.

In this embodiment, the position pulse input clock section is configured by the control circuit A, the clock pulse generator 11 and the clock counter 12 are realized by the control circuit or taken out from the calculation control device B, and the clock buffer control section 13
The data is temporarily stored in a time buffer 15 via a time counter readout unit 14 controlled by a time counter readout unit 14 controlled by a time counter readout unit 14 controlled by a time counter readout section 14 controlled by a time counter readout section 14 controlled by a time counter readout section 14 controlled by a time counter readout section 14 controlled by a time counter readout section 14 controlled by a time counter readout section 14 controlled by a time counter readout section 14 . That is, the position pulse input absolute time taken in by the calculation control device is the data set in the clock buffer 15.

Timing buffer control unit 1 simultaneously with position pulse input
3 operates the time counter reading section 14, and the absolute time of the time counter 12 is set in the time buffer 15. Since the timing buffer control section 13 and the timing counter reading section 14 operate only when a position pulse is input, the position pulse input absolute time set in the timing buffer 15 is held until the next position pulse input.

When a position pulse is input, the calculation control device operates the rationalization check section 2 and the speed calculation time reading section 3, reads out the position pulse input absolute time of the timing buffer 15 set above, and sets it in the speed calculation time register 4. .

FIG. 4 shows how the clock buffer and speed calculation time are read out when position pulses are input.

In FIG. 4, clock pulses are generated at regular intervals, and the absolute time of the time counter is the sum of the number of generated clock pulses. When the position pulse input P ₁ in Fig. 4 occurs, the position pulse input absolute time T ₁ is set in the timing buffer, and even if the speed calculation time readout R ₁ corresponding to the position pulse input P ₁ is delayed, the speed The value detected as the calculation time becomes T ₁ , and a correct result is obtained.

If the speed calculation time readout _R1 ends before the next position pulse input _P2 , accurate speed calculation time can be obtained at all times, so no speed detection error occurs.

According to this embodiment, the absolute time of the position pulse is taken in by the time buffer control section 13, the time counter readout section 14, and the time buffer 15 provided in the control circuit A, and the contents are temporarily stored in the buffer 15. Since the position pulse is set in the register 4 by the position pulse of Noise removal of position pulse input can be realized as a function tailored to the position pulse input without changing the control device.

In addition, if the clock pulse generator is implemented in the control circuit instead of using the clock pulse with a fixed period that is standardly equipped in calculation control device B, a clock with an appropriate period corresponding to the position pulse input time interval can be used. can do.

According to the present invention, the speed calculation time can be accurately detected regardless of the control load of the calculation control device, so that speed detection errors do not occur even in high speed ranges where the control load of the calculation control device increases. Detection is possible.

[Brief explanation of the drawing]

FIG. 1 is a conventional speed detection device, FIG. 2 is an explanatory diagram of the speed calculation time detection contents in FIG. 1, FIG. 3 is a configuration diagram showing an embodiment of the present invention, and FIG.
It is an explanatory view of speed calculation time detection contents in a figure. A...Control circuit, B...Calculation control device, 1...
Position pulse input section, 2... Rationality check section, 3
...Speed calculation time reading unit, 4...Register, 5
...Time width detection section, 6...Reference time storage section, 7...
...Time storage control unit, 8...Time storage unit, 9...Speed calculation unit, 10...Position pulse counter, 11...
...Clock pulse generation section, 12...Time counter, 13...Time buffer control section, 14...Time counter reading section, 15...Time buffer.

Claims (1)

[Claims] 1. A means for generating a position pulse train according to the travel distance of a moving object, and a calculation control device that inputs this position pulse train and calculates the speed of the mobile object by program processing. means for reading the input times of the first and second pulses, and means for calculating the time width between the two pulses from the difference between these two input times;
A device including a means for counting the number of position pulses inputted between the two pulses, and a speed calculation means for dividing the counted contents by the time width, which is provided outside the calculation control device, and includes a timing buffer; A control circuit is provided with means for reading out the time measurement contents of the absolute time counter to the time measurement buffer every time an output pulse is generated from the pulse train generation means, and the pulse input time reading means is configured to read out the time measurement contents of the absolute time counter to the time measurement buffer every time an output pulse is generated by the pulse train generation means, and the pulse input time reading means A speed detection device characterized in that it is configured to read the time stored in the time measurement buffer.