JPS6135577B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a microprogram control method for computer hardware, and is intended to improve the reliability of the operation of the hardware.

Control of computer hardware tends to be performed by microprograms. As a result, the capacity of memory for storing microprograms has increased, so as shown in Figure 1, multiple ROMs (read only memory) M ₁ ,
M ₂ , M ₃ . It's on. Since a plurality of ROMs are connected in the form of a bus in this way, if an error occurs on the control bus 2 of the ROM, microinstructions become unexecutable, resulting in a system failure. Additionally, if the system goes down, it becomes impossible to diagnose errors.

On the other hand, as described in Japanese Patent Application Laid-Open No. 50-82950, there is an instruction register into which a macro instruction is introduced, a microprogram counter that specifies the address of a microprogram based on the macro instruction, and a microprogram counter that specifies the address of the microprogram based on the macro instruction. A switching circuit can select between an internal processing device consisting of a microprogram memory that stores microprograms accessed by the contents of the microprogram, and an external processing device with exactly the same configuration to execute different instructions. It is proposed that In this means, it is conceivable to store the basic instructions of the CPU in the microprogram memory of the internal processing device, and use the microprogram memory of the external processing device as an extended instruction memory or optional memory. However, it is necessary to equip each microprogram memory with an instruction register, microprogram counter, etc.
including extended instruction memory and option memory,
If a large amount of memory is required, the hardware will be large-scale. Furthermore, an operation instruction circuit, an error determination circuit, etc. are also required, making the control complex and the reliability of the operation poor.

The technical problem of the present invention is to solve these problems in the conventional microprogram control method,
The purpose is to enable only the basic instruction memory to be independent from other extended instruction memories, option memories, etc. by using a method that is easy to configure and control.
In order to achieve this objective, the present invention utilizes the CPU (Central Processing Unit) to
Microprograms important for the control of the CPU are stored in a ROM separate from other extended instructions, etc., and are separated from the control bus for other extended instructions, etc., and a multiplexer is used to switch between the CPU basic instruction ROM and other ROM. A method is adopted in which instructions are read out. in this way
Since the CPU basic instruction ROM is separated from other ROMs, even if an error occurs on the control bus of other extended instruction ROMs, the CPU basic instruction ROM can still be read and the system will go down. There is no error analysis or ROM related to the error.
It is also possible to disconnect the control bus from the control bus. Furthermore, the extended instruction memory, option memory, etc. are connected to a common control bus, and the basic instruction memory, extended instruction memory, option memory, and the judgment circuit that controls the multiplexer are each connected to a common address bus. There is no need to provide an instruction register or microprogram counter for each microprogram memory as in the past, and there is also no need for operation instruction circuits or error judgment circuits, simplifying the hardware and making control easy and reliable. Improves sex.

Next, an embodiment of the method of the present invention will be described based on FIG. Mc, M ₁ ′, M ₂ ′...... are memories that store microprograms, such as ROM, and the memory Mc stores CPU operations such as execution of basic CPU instructions, interrupt control, console control, etc. contains important microprograms. Other memories M ₁ ′, M ₂ ′...... are extended instructions
ROM or option ROM, such as the above
Contains microprograms other than instructions important for CPU operation. For example, special instructions such as floating instructions, function control, high-speed multiplication and division, etc. are stored. These extended instruction memories and option memories M ₁ ′, M ₂ ′...
... are connected on the same control bus 2, but the basic instruction memory Mc is separated from this control bus 2 and is connected to the instruction register 3 via a multiplexer 4. A control bus 2 is also connected to the multiplexer 4, and when reading instructions, the multiplexer 4 switches between the basic instruction memory Mc and other memories M ₁ ', M ₂ ', . . . . That is, by determining the address by the determining circuit 5 connected to the address bus 1, the multiplexer 4 selects the basic instruction memory Mc and other memories M ₁ ', M ₂ ', . . . . In each memory Mc, M ₁ ', M ₂ ', . . ., when its own address is selected, the gate is opened and the microprogram is read into the microinstruction execution register 3.

In this way, the basic instruction memory Mc is connected to the control bus 2 to which other memories M ₁ ′, M ₂ ′, etc. are connected.
Since _{the control} bus 2 is separated from Since it is possible to read from the instruction memory Mc, the system does not go down like in the past. In addition, since the CPU is operational, it is also possible to analyze errors that occur on control bus 2.
As a result, it is possible to isolate only the memory involved in the error and control the microprogram using other memories. In particular, the extended instruction memory, option memory, etc. are connected to a common control bus, and the basic instruction memory, extended instruction memory, option memory, and judgment circuits that control the multiplexer are each connected to a common address bus. There is no need to provide an instruction register or a microprogram counter for each microprogram memory, and there is also no need for an operation instruction circuit or an error determination circuit, which simplifies the hardware. Furthermore, control of access to the target system down memory becomes easier, improving reliability.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional microprogram control circuit, and FIG. 2 is a block diagram showing a conventional microprogram control circuit.
FIG. 2 is a block diagram of a microprogram control circuit showing an example of a program control method. In the figure, Mc is the basic instruction memory, M ₁ ′,
M ₂ '...... is extended instruction memory and option memory, 1 is address bus, 2 is control bus, 3
is a microinstruction execution register, 4 is a multiplexer, and 5 is a determination circuit. 〓〓〓〓

Claims (1)

[Scope of Claims] 1. Microprograms important for controlling the CPU, such as the basic instructions of the CPU, are stored in a basic instruction memory that is separate from other extended instruction memories and option memories. The option memories are each connected to a common control bus, the basic instruction memory is separated from the control bus, the control bus and the basic instruction memory are connected to the microinstruction execution register via a multiplexer, and the basic instruction memory is connected to the microinstruction execution register via a multiplexer. A microprogram control system characterized in that an instruction memory, an extended instruction memory, an option memory, and a determination circuit for controlling the multiplexer are each connected to a common address bus.