JPS6135739B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a bus control device in a data transmission device that selectively connects a plurality of digital devices via a common bus.

As this type of data transmission equipment becomes larger and more complex, the number of signal wires increases and the processing of signal lines becomes difficult using individual wiring as in the past. Bus route (bus line)
A single bus system, in which signals are sent and received from multiple points on the bus, has come into use.

FIG. 1 shows the general configuration of such a data transmission device using a single bus method. Data transmission and reception on a common bus 1 is managed by a bus control device 2, and input/output devices are connected from the data common bus 1. Control part 3
The information is sent to and received from the input/output device 4 via the input/output device 4.

Figure 2 shows the conventional configuration of such a data transmission device using a single bus method.Generally, the common bus 1 has a plurality of signal lines, one of which
Only books are shown.

In the figure, each input/output device 4 sends a signal onto the common bus 1 by a transmission gate 5 in the input/output device control unit 3, and the signal is received by a reception gate 6 in the bus control device 2. It's summery. The output state of the transmission gate 5 is low impedance when the signal is on, and high impedance when the signal is off. In addition, 7 is resistance,
8 is a power supply terminal.

By the way, in a single bus type data transmission device, the input/output device side, for example, the input/output device control section 3
If the output of the transmitting gate 5 remains at low impedance due to a malfunction or failure of the transmitting gate 5, data transfer using the common bus 1 is impossible until the impedance is restored. If the signal on the line is a control signal that manages input/output, an abnormality in one signal line causes bus 1
All input/output processing using .

Therefore, it is necessary to detect an abnormality in the signal line and take prompt action, but in the conventional device, an abnormality is detected as a result of data transmission and reception via the common bus 1. For example, if there is a failure in a data signal line, the abnormality is detected after erroneous data is sent and received.

Therefore, data is sent and received in vain until an abnormality is discovered, reducing the reliability of the system and causing a large loss of time until an abnormality is discovered.

The present invention detects an abnormality in one of the signal lines of the common bus at a timing when data is not being transferred on the common bus, and when an abnormality is detected, returns all digital devices to the initial state. , the bus control system checks the signal line for failure again, and if the failure is not recovered, prohibits data transfer on the common bus, improving system reliability and reducing time loss until abnormality detection. It provides equipment.

FIG. 3 shows an embodiment of a common control device according to the present invention.

In the figure, a common bus 1 consists of a signal line 9 indicating that the input/output device is transferring data, a signal line 10 indicating a data transfer request from the input/output device, a reset line 11, and other signal lines 12. There is.

The bus control device 2 also controls the or gates 13 to 1.
5, clock generator 16, flip-flop 1
7, 18 and a reset signal sending circuit 19.

In such a configuration, when the power of the bus control device 2 is turned on and the common bus 1 becomes available for use, the clock generator 16 operates continuously from then on, and the signal line abnormality occurs when the bus is not used. A detection timing pulse is sent to flip-flop 17 via trigger line 20.

The flip-flop 17 also has a signal line 12.
The signal is the OR gate 13, the signal line status display line 21
is entered via.

If the signal lines 9 and 10 are currently off and no data is being transferred on the common bus, the flip-flop 17 uses a signal from the clock generator 16 to turn the signal line 12 on at a constant cycle. Check to see if the transmitting gate is malfunctioning. At this time, if even one of the signal lines 12 is turned on due to a failure in the input/output device or the common bus itself, the output of the OR gate 13 is turned on, and the trigger signal 20 causes the flip-flop 17 to turn on. is set. In other words, a failure has been detected by this flip-flop 17. If this happens, normal data transfer is no longer guaranteed.

Therefore, before the next data transfer begins, the reset signal sending circuit 19 resets the input/output devices to the initial state. After sending out the reset signal, it is checked again whether all the bus signal lines, including signal lines 9 and 10, other than the reset line 11 are turned off.

Specifically, the output of gate 13, which is the OR output of signal line 12, and the output of gate 15, which is the OR output of gate 14, which is the OR output of signal lines 9 and 10, are input to flip-flop 18. Check at the timing shown in Figure 4d.

If an abnormality is detected again here, flip-flop 18 is set and flip-flop 1
8 is set, the reset signal continues to be output to the reset line 11, as shown by the broken line in FIG. 4c.

In other words, if no abnormality is detected again in the recheck after sending the reset signal, the abnormality previously detected by the flip-flop 17 is an abnormality that can be recovered by resetting the input/output device, so the input/output After resetting the device, resume data transfer on the common bus.

However, if the flip-flop 18 detects the error again, it determines that it is an abnormality that requires maintenance, sends a reset signal, locks the input/output devices connected to the common bus, and disconnects the common bus. Make one or more processing devices used unresponsive. That is, after all input/output devices are set to their initial state, the presence or absence of an abnormality is checked again, and if the failure is not recovered, all data transfer on the common bus is prohibited from now on.

While the signal indicating that data transfer is in progress or the data transfer request signal on the signal line 9 or 10 is on, the flip-flop 17 is reset through the OR gate 14 and the clear line 22, and at the same time the trigger signal output 10 of the clock generation circuit 16 is reset. prevent. Therefore, the signal line abnormality check has no effect on normal data transfer, and therefore abnormality detection is possible without impairing the data processing ability of the common bus itself.

Figure 4 shows a time chart of the above-mentioned signal line abnormality detection timing.
Only when there is no data transfer as shown in a, a signal line check pulse shown in b is generated to start checking. As a result, if an abnormality is detected, a reset signal shown in c is sent to all input/output devices, and when the reset of each input/output device is completed,
The signal line is checked again using the signal line check pulse shown in d. If no abnormality is detected, the reset signal continues to be sent as shown by the dotted line c, and the use of any input/output device is prohibited from now on.

As described above, according to the present invention, a failure in the common bus can be detected before data transfer, and the failure can be confined within the common bus and prevented from spreading to the processing devices that use the common bus. Reliability can be improved and time loss until abnormality detection can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a single bus type data transfer device, FIG. 2 is an explanatory diagram illustrating a conventional bus control device, and FIG. 3 is a configuration diagram of an embodiment of a bus control device according to the present invention. FIG. 4 is a timing chart explaining the operation of FIG. 3. DESCRIPTION OF SYMBOLS 1... Common bus, 2... Bus control device, 3... Input/output device control section, 4... Input/output device, 9-12... Signal line, 13-15... OR gate, 16... Clock generator, 17, 18... Flip-flop, 19...Reset signal sending circuit.

Claims (1)

[Claims] 1. A data transmission device comprising a plurality of digital devices and a common bus, wherein the digital devices are selectively connected to the common bus, and the selected digital devices exclusively use the common bus to transfer data, detection means for detecting an abnormality in one of the signal lines of the common bus at a timing when none of the digital devices is transferring data via the common bus; , state setting means for setting all of the digital devices to an initial state; and after the initial state setting by the means, detecting an abnormality in the signal line of the common bus again, and when an abnormality is detected, setting the digital device to an initial state; 1. A bus control device for a data transmission device, comprising means for retaining all initial states.