JPS6135795B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention improves speed stability by using a stable frequency such as the output of a crystal oscillator as a speed reference,
Furthermore, by inserting a low-frequency compensation circuit into the speed control loop to improve load stability, even though it is essentially a single-loop control circuit consisting only of the speed control loop, when phase control is applied. This invention relates to a motor speed control device that can obtain almost the same characteristics as the above. Conventional motors used in audio equipment such as record players use speed control motors that use voltage as the speed standard, but this method is sufficiently resistant to changes in ambient temperature and aging of components. It is difficult to create a stable reference voltage; for example, if the reference voltage changes due to a change in temperature, it may cause a change in motor speed and cause a speed deviation; Contains problems. To solve this problem, high-end machines add a phase control loop to the speed control loop to reduce speed deviations in response to changes in steady load or changes in ambient temperature. However, this method requires two control loops, a speed control loop and a phase control loop, and the operations of these two control loops affect each other, making adjustment difficult, the configuration complex, and the surrounding environment Various problems exist, such as the operating point shifting due to changes in temperature or aging of components, resulting in a decrease in the synchronization range. The present invention provides a motor speed control device that can solve the above-mentioned conventional problems. Hereinafter, the present invention will be explained based on illustrated embodiments. FIG. 1 is a block diagram of one embodiment of the present invention. This will be explained with reference to the waveform diagram for explaining the operation in FIG. Note that the signals I to I appearing on the signal lines in FIG. 1 and I to I in FIG. 2 correspond to each other. The speed of a speed-controlled motor 1 such as a brushless DC motor is measured by two detectors 1, a first and a second.
3A and 13B, and AC signals A and B corresponding to the rotational speed of the motor 1 and having different phases are obtained from the respective detectors 13A and 13B. The AC signals A and B are waveform-shaped by first and second shaping circuits 14A and 14B, respectively, to become rectangular-wave shaped signals C and D. A reference frequency generating circuit 2, which generates a stable frequency signal like a crystal oscillator, supplies a clock pulse to a reference time width generating circuit 3. The reference time width generation circuit 3 uses the rising edge of the output signal C of the first shaping circuit 14A as a trigger signal, and uses the clock pulse of the reference frequency generation circuit 2 as a trigger signal.
It is constituted by an N-ary counter that maintains the "1" level while counting N numbers (N is an integer) and returns to the "0" level after counting N numbers.
Therefore, the output signal of the reference time width generation circuit 3 is as follows.
The pulse signal remains at the "1" level for the reference time width T _c =N·τ from the time of triggering by the output signal C of the first shaping circuit 14A. Here, τ is the period of the clock pulse supplied by the reference frequency generating circuit 2. Further, in FIG. 2, the "1" level is shown as a high level. Time difference width T _d between the output signal D of the second shaping circuit 14B and the output signal C of the first shaping circuit 14A
(In this example, the time from the rising edge of the output signal C to the rising edge of the output signal D) is detected by the time difference pulse generator 4, and a pulse signal H which remains at the "o" level during the time difference width T _d is obtained. . This output signal E and the output signal of the reference time width generation circuit 3 are synthesized in the pulse synthesis circuit 5, and the time difference width T _d and the reference time width T _c
An output pulse is generated according to the difference (T _d −T _c ) between the two. In this example, the output state of the pulse synthesis circuit 5 has three states: a "current outflow" state, a "current intake" state, and a "high impedance" state, and always when T _d −T _c =o. Between the “ _high impedance _” state and the “high impedance” state when T _{d −T c} ≠ _o , a pulse-like “ There is a current outflow state or a current inflow state. The time difference pulse generation circuit 4 and the pulse synthesis circuit 5 constitute a time width comparison circuit 9, which compares the time difference width _Td and the reference time width _Tc , and generates an output pulse according to _Td - _Tc . I have to. Further, the reference time width generation circuit 3 and the time width comparison circuit 9 constitute a speed error detection circuit 10. The output signal T of the time width comparison circuit 9 is smoothed by the filter circuit 6 and converted into a DC voltage, and the low frequency component including the DC voltage is amplified by the low frequency compensation circuit 7. The output signal of the low frequency compensation circuit 7 is power amplified by the motor drive circuit 8 and supplied to the motor 1. As a result, the speed of the motor 1 is controlled so that the time difference width T _d is equal to or approximately equal to the reference time width T _d . FIG. 3 shows an example of the relationship between the motor 1 and the detectors 13A, 13B. In the same figure, the rotation shaft 1 of the motor 1
The disc-shaped detection rotor 12 attached to the rotor 1 has a plurality of fixed magnetic pole pairs (N, S poles) that are permanently magnetized over the entire circumference on a circle centered on the rotation axis or almost on a circle. It has a changing part. A composite head 13 that integrally includes two magnetic heads constituting the detectors 13A and 13B is disposed opposite the changing portion (magnetic pole pair) of the detection rotor 12. The detectors 13A and 13B are arranged separated by a predetermined distance, and the detection rotor 1
2, AC signals with different phases are generated. FIG. 4 shows an explanatory diagram of the principle of speed detection in this example.
The figure shows the detection rotor 12 and the detectors 13A, 1.
3B is a view seen from above the axis, E indicates the rotation axis, and F indicates one point of the changing part. Further, the outer circumference of the detection loader 12 is indicated by a circle, and the circle on the circle indicates the switching point of the magnetic pole pair, which is a changing part.
Detector 13 for output AC signal of detector 13A
The time difference T _d of the output AC signal of B is the detection rotor 1
The rotational angular velocity of 2 is ω, and the detectors 13A and 13B
If the angle seen from the center of rotation E is θ, then T _d =θ/ω. Therefore, if the time difference T _d is controlled to be a constant value T _c , the rotational speed of the motor 1 will be constant. In particular, if the detector 13A is placed upstream of the detector 13B with respect to the rotational direction of the detection rotor 12 as shown in the figure, it can be made less susceptible to the eccentricity of the detection rotor 12 and variations in the changing portion. It will be advantageous. FIG. 5 shows a specific example of the configuration of the speed error detection circuit 10. In the same figure, the clock input terminal
N with CK, clear terminal CL and output terminal
A forward counter 21, a differentiation circuit 22 which differentiates the rising edge of the input signal and outputs an "O" level signal, and an "O" level signal.
A reset/set flip-flop (hereinafter abbreviated as R-S/FF) circuit 23 that performs reset and set operations using a level trigger signal, and an AND
The reference time width generating circuit 3 is constituted by the circuit 24, and includes a set priority reset/set flip-flop (hereinafter abbreviated as S priority RS/FF) which performs reset and set operations using a signal at the "1" level. ) The circuit 25 constitutes the time difference pulse generation circuit 4, and the OR circuit 26, the AND circuit 27, and the PNP
type transistor 32 and NPN type transistor 3
3 and resistors 28, 29, 30, and 31 constitute a pulse synthesis circuit 5. Next, its operation will be explained with reference to the waveform diagram in FIG. First, the output signal C of the first shaping circuit 14A is at "0" level, and the second shaping circuit 14B
Output signal 2 is at "1" level, output to Q output of R-S/FF circuit 23 is "0" level, S priority R-S/
It is assumed that the output H of the FF circuit 25 is at the "1" level (the leftmost state in FIG. 2). Next, if the signal C changes to the "1" level, a trigger signal of the "0" level is generated in the differentiating circuit 22 at the rising edge of the signal C, and the R-S FF
The Q output of the circuit 23 is changed to the "1" level. The output of the differentiating circuit 22 is at the "1" level except at the rising edge of the signal C, and the R-S.
Since the Q output of the FF circuit 23 changes to "1" level, the CL terminal of the N-ary counter 21 becomes "1".
level, and the clearing (resetting) of the N-ary counter 21 is canceled. As a result, the N-ary counter 21 starts counting the clock pulses input to the CK terminal from the time of triggering by the signal C, and while counting N clock pulses, the terminal is at the "1" level, The moment the count ends, the terminal changes from "1" level to "0" level. The R-S/FF circuit 23 is reset by the change in the "0" level of the terminal, and the Q output of the R-S/FF circuit 23 becomes "0".
level. To the Q output, the CL terminal is set to "0" level via the AND circuit 24, and the N-ary counter 2 is connected to the Q output.
The internal state of 1 is set to "0" and the terminal is set to "1" level, and R-S.
The Q output of the FF circuit 23 is kept at "0" level. Therefore, the reference time width generating circuit 3 uses the rising edge of the output signal C of the first shaping circuit 14A as a trigger signal to generate a reference time width T _c =Nτ determined by the product Nτ of the period τ of the clock pulse and the number of counts N. while,
A reference time width pulse signal having a "1" level is generated. Usually, the count number N is set between 10 and ¹⁰⁵ . On the other hand, the output signal C of the first shaping circuit 14A is applied to the set trigger input terminal S of the time difference pulse generation circuit 4 constituted by the S-priority R-S/FF circuit 25, and the output signal C of the first shaping circuit 14A is applied to the reset trigger input terminal S. The output signal D of the second shaping circuit 14B is added to R. Considering the temporal changes in the inputs S, R and the output from the leftmost state in FIG. 2, the results are as shown in Table 1 below. Here, H corresponds to the "1" level and L corresponds to the "0" level.

[Table] Therefore, the output H of the S-priority R-S/FF circuit 25 is set with the rising edge of the input signal H at the set trigger input terminal S as the trigger point (in this example, =
It is reset (=H in this example) with the rising edge of the input signal 2 at the reset trigger input terminal R as the trigger point. As a result, the output signal H of the time difference pulse generation circuit 4 is transmitted to the first shaping circuit 14A.
The rising edge of the output signal C is used as a trigger signal, and a time difference pulse signal having a pulse width equal to the time difference width T _d of the output signal D of the second shaping circuit 14B with respect to the output signal C is generated. The output signal H of the reference time width generation circuit 3 and the output signal H of the time difference pulse generation circuit 4 are input to the OR circuit 26 and the AND circuit 27 of the pulse synthesis circuit 5, and the output of the OR circuit 26 causes the transistor 3
2, and the transistor 33 is driven by the output of the AND circuit 27. The relationship between the input signals H and E of the pulse synthesis circuit 5 and the output state G is as shown in Table 2 below.

[Table] Therefore, as shown in FIG. 2, the output state of the pulse synthesis circuit 5 is normally in a "high impedance" state (both transistors 32 and 33 are OFF), and T _d −T _c ≠0. Sometimes during the “high impedance” state, depending on the sign of T _d −T _c |T _d
−T _c | width pulse-like “current outflow” state or “current inflow” state is sandwiched. In this example, “current outflow” occurs when T _d −T _c >0.
state, and when T _d −T _c <0, the state is defined as “current suction”. This is a problem in circuit configuration, and it goes without saying that the reverse case can also be configured. Next, the time difference width T _d , the reference time width T _c and the motor 1
The operation will be explained with reference to FIG. In FIG. 6, a shows the case where the speed of the motor 1 is too slow, b shows the case where the speed is too fast, and c shows the case when the motor 1 is at a steady speed. If the speed of the motor 1 in FIG. 6a is too slow, the time difference width T of the output signal E of the time difference pulse generation circuit 4
_d becomes wider than the reference time width T _c to the output signal of the reference time width generation circuit 3 (T _d > T _c ), and the output state of the pulse synthesis circuit 5 becomes |T _d - _{T c} | width. It has a "current outflow" state. The output pulse of the pulse synthesis circuit 5 is supplied to the filter circuit 6 shown in FIG. , control is applied to make the time difference width T _d equal to the reference time width T _c . Also, if the speed in Fig. 6b is too fast, T _d
<T _c , and the output state of the pulse synthesis circuit 5 has a "current suction" state with a width of |T _d −T _c |. At this time, the output voltage of the filter circuit 6 decreases, and the low frequency compensation circuit 7 and the motor drive circuit 8
Control is applied to slow down the speed of the motor 1 via , so that T _d is equal to T _c . Furthermore, when the motor 1 in FIG. 6c is at a steady speed, T _d =T _c , and there is no period in which the signals E and E are at the same level, and the output state G of the pulse synthesis circuit 5 is in a "high impedance" state. Therefore, no current flows into or out of the filter circuit 6, and its output voltage remains constant. As a result, the speed of the motor 1 can be kept constant. As is clear from the above description, in the steady control state, the relationship T _d =T _c =Nτ (constant) always holds true. Note that the time difference pulse generation circuit 4 in FIG.
Not limited to the priority R-S/FF circuit 25, for example, 2
It may also be configured by a differentiating circuit and an R-S/FF circuit whose differential output is used as a trigger input. FIG. 7 is a diagram showing another configuration example of the reference time width generation circuit 3, in which the reference time width T _c is set by changing the count number N from the outside using the programmable counter 41. Motor 1
It is designed to adjust the speed of In the same figure, the differentiating circuit 22 and the R-S/FF circuit 23
The AND circuit 24 has the same configuration as that shown in FIG. 5 described above, and its operation is also the same. In Figure 7,
The difference from the reference time width generation circuit 3 in FIG. 5 is that N
This is where the advance counter 21 is replaced with a programmable counter 41. Programmable counter 4
1 has a preset input terminal, and the terminal becomes “1” level from the start of counting, and furthermore,
When the preset input terminal has finished counting the value set in binary, a "0" level output is output from the terminal. Presetting of the programmable counter 41 is performed by a setting circuit 42, which is composed of a plurality of switches 43 and a plurality of resistors 44 that provide a "1" level. The preset input terminals of the programmable counter 41 correspond to digits 2 ⁰ , 2 ^{1 ,} _. ) can be obtained. According to this configuration, as _explained with the time chart in _FIG . When the count number N of 41 is changed externally, the reference time width _Tc changes, and as a result, the speed of the motor 1 changes so that the time difference width _Td becomes equal to _Tc . Therefore, the count number N of the programmable counter 41
By adjusting , the speed of the motor 1 can be adjusted. Note that τ above is the period length of the clock pulse pulse. FIG. 8 shows a specific example of the configuration of the low frequency compensation circuit 7. In the figure, an operational amplifier 51, a resistor 5
2 and 53, a capacitor 54, and a reference power supply 55, the active filter constitutes the low frequency compensation circuit 7. As shown in FIG. 9, the frequency characteristics of the low frequency compensation circuit 7 operate such that the gain increases as the frequency range including DC increases, and by incorporating it into the speed control loop, the amount of feedback increases as the frequency decreases. It's becoming like that. FIG. 10 shows the control characteristics of the motor. Figure a is a Bode diagram showing the torque disturbance frequency-speed fluctuation characteristics, and the broken line J is the low-frequency compensation circuit 7.
The solid line K shows the case where there is no low-frequency compensation circuit 7. In addition, FIG. 1B is a graph showing steady load torque-speed change characteristics, where the broken line J is the case where the low-frequency compensation circuit 7 is not provided, and the solid line K is the case where the low-frequency compensation circuit 7 is present. By incorporating such a low frequency compensation circuit 7 into the control loop, the amount of feedback of the control system increases as the frequency range decreases.
In the DC range, it is practically infinite (determined by the bare gain of the operational amplifier 51 in Fig. 8), so any load torque within the control range is as shown by the solid line K in Fig. 10b. However, the speed change is almost zero, and the characteristics are almost the same as when phase control is applied. Note that the detectors 14A and 14B used in the present invention
is not limited to the structure illustrated in FIG. 3; for example, two full-circumference integral type frequency generators may be used. Further, the motor 1 is not limited to a rotary type, but may be a so-called linear motor that moves in a straight line. Furthermore, the motor 1 and the motor drive circuit 8 are not limited to direct current type. As is clear from the above description, the motor speed control device of the present invention has a number of features as described below. (1) Although it is a single-loop control circuit with only a simple speed control loop, it can have almost the same load characteristics as when phase control is applied. Additionally, as a result, the operating points of the speed control loop and the phase control loop do not interfere with each other, as would be the case when phase control is applied, and the operating points of the circuit will not fluctuate due to changes in ambient temperature or aging of components. It also disappears. (2) Since speed error detection is performed digitally, no detection errors other than bit errors occur, and extremely accurate detection is possible. In particular, by using a stable frequency signal such as the output of a crystal oscillator as a clock pulse, the reference time width T _c =Nτ becomes stable, and as a result, the stability of the steady speed of the motor is equivalent to that of the crystal oscillator. can do. (3) The output state of the speed error detection circuit (output state of the pulse synthesis circuit 5) is "current outflow" mode, "current intake" mold, and "high impedance".
It has three modes, and when the speed is constant, it becomes stable in the "high impedance" mode, so there is no current flowing in or out, and no ripples occur. Or even if it occurs, it is extremely small. Therefore, even if the time constant of the filter circuit 6 is made small, smooth control can be achieved. (4) Even if the count number of the counter that constitutes the reference time width generation circuit of the speed error detection circuit is changed in order to adjust the steady speed, the output state of the speed error detection circuit will automatically become "high impedance" mode. Since the speed is constant, there is no need to adjust the operating point. Therefore, speed adjustment and variable speed control are facilitated. (5) Since the speed error detection circuit can be constructed entirely of digital circuits, it is suitable for IC implementation such as IIL or C-MOS. Further, external capacitors and the like required in conventional sampling-type speed error detection circuits are not required, and costs can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention;
Figure 2 A, B, C, D, H, H, and G are waveform diagrams for explaining the operation, Figure 3 is a main part configuration diagram showing an example of the relationship between the motor and the detector in the same embodiment, and Figure 4 is Third
5 is a diagram showing a specific configuration example of the speed error detection circuit; FIGS. 6 a, b, and c are time charts for explaining the speed control operation; FIG. 7 is a diagram showing an example of the configuration of the reference time width generation circuit, FIG. 8 is a diagram showing an example of the configuration of the low-frequency compensation circuit, FIG. 9 is its frequency characteristic diagram, and FIGS. 10a and b are according to the present invention. FIG. 4 is a characteristic diagram for explaining an example of a characteristic improvement effect. 1...Motor, 2...Reference frequency generation circuit, 3...Reference time width generation circuit, 4...Time difference pulse generation circuit,
5...Pulse synthesis circuit, 6...Filter circuit, 7...Low frequency compensation circuit, 8...Motor drive circuit, 9...Time width comparison circuit, 10...Speed error detection circuit, 13A, 13
B...detector, 14A, 14B...shaping circuit, 21...
N-ary counter, 22...differentiation circuit, 23...reset/set flip-flop circuit, 24...
AND circuit, 25...Set priority reset/set flip-flop circuit, 41...Programmable counter, 42...Setting circuit.

Claims (1)

[Scope of Claims] 1. A speed-controlled motor, first and second detectors for obtaining first and second AC signals corresponding to the rotational speed of the motor and having different phases, and the first detection a first shaping circuit that shapes the output AC signal waveform of the detector, a second shaping circuit that shapes the output AC signal waveform of the second detector, a reference frequency generation circuit that generates a clock pulse, and a clock pulse. It has an input terminal and a trigger pulse input terminal, uses the output signal of the first shaping circuit as a trigger signal, starts counting the clock pulses from the trigger point, and counts N clock pulses (N is an integer). Maintain the first level while
It includes an N-ary counter that becomes the second level after completing N counts, and has a reference time width T ₀ [=
a reference time width generating circuit that generates a pulse of N·τ (τ is the period of the clock pulse)], a time difference width T _d between the output signal of the second shaping circuit with respect to the output signal of the first shaping circuit, and the reference time. A time width comparison circuit that compares the reference time width _Tc of the width generation circuit and generates an output pulse according to the difference between them, a filter circuit that smoothes the output of the time width comparison circuit, and a DC output of the output of the filter circuit. and a motor drive circuit that power amplifies the output of the low frequency compensation circuit, and supplies the output of the motor drive circuit to the motor to increase the time difference width T. A speed control device for a motor, characterized in that a speed control system is configured such that _d is equal to or approximately equal to the reference time width _Tc . 2. The motor according to claim 1, wherein the time width comparison circuit has three output states: a current outflow state, a current intake state, and a high impedance state. Speed control device. 3. In the description of claim 1 or 2, the N-ary counter constituting the reference time width generation circuit is a program counter whose count number is programmable, and the program counter is controlled by external settings. A motor speed control device characterized in that the speed of the motor can be adjusted by adjusting the speed of the motor. 4. In the description of claim 1 or 2, the time width comparison circuit has a set trigger input terminal and a reset trigger input terminal, and uses the output signal of the first shaping circuit as the set trigger. The output as a signal is set to the first level, and the second
By using the output signal of the shaping circuit as a reset trigger signal and resetting the output to the second level, the time difference width T _d between the output signal of the second shaping circuit and the output signal of the first shaping circuit can be adjusted. 1. A motor speed control device comprising: a time difference pulse generation circuit for generating pulses; and a pulse synthesis circuit for synthesizing output pulses from both the reference time width generation circuit and the time difference pulse generation circuit.