JPS6136695B2 - - Google Patents
Info
- Publication number
- JPS6136695B2 JPS6136695B2 JP54129750A JP12975079A JPS6136695B2 JP S6136695 B2 JPS6136695 B2 JP S6136695B2 JP 54129750 A JP54129750 A JP 54129750A JP 12975079 A JP12975079 A JP 12975079A JP S6136695 B2 JPS6136695 B2 JP S6136695B2
- Authority
- JP
- Japan
- Prior art keywords
- secondary winding
- impedance
- winding
- compensating
- core side
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000004804 winding Methods 0.000 claims description 49
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical group [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 claims description 11
- 238000010586 diagram Methods 0.000 description 4
- 230000005284 excitation Effects 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F27/00—Details of transformers or inductances, in general
- H01F27/42—Circuits specially adapted for the purpose of modifying, or compensating for, electric characteristics of transformers, reactors, or choke coils
- H01F27/422—Circuits specially adapted for the purpose of modifying, or compensating for, electric characteristics of transformers, reactors, or choke coils for instrument transformers
- H01F27/427—Circuits specially adapted for the purpose of modifying, or compensating for, electric characteristics of transformers, reactors, or choke coils for instrument transformers for current transformers
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Transformers For Measuring Instruments (AREA)
Description
【発明の詳細な説明】
本発明は誤差補償を目的とした変流器に係り、
特に能動素子を用いて高精度に誤差補償を行なう
誤差補償形変流器の改良に関する。[Detailed Description of the Invention] The present invention relates to a current transformer for the purpose of error compensation,
In particular, the present invention relates to improvements in error-compensating current transformers that use active elements to perform error compensation with high precision.
第1図は従来の能動素子を用いた誤差補償形変
流器である。同図においてlは鉄心であつて、こ
の鉄心lは1次側に巻数N1を巻装してなる1次
巻線2,2次側に巻数N2を巻装してなる2次巻
線3を備えている。4は演算増幅器であり、これ
の反転入力部は2次巻線3の一方出力端子5に、
非反転入力部は2次巻線3の他方出力端子6に接
続されている。さらに、演算増幅器4の反転入力
部と出力部との間に帰還抵抗7を接続している。
8,9は変流器の出力端子であつて出力電圧vp
を発生する。なお、演算増幅器4の非反転入力部
は端子6,9に共通接続して接地状態としてい
る。 FIG. 1 shows a conventional error compensation type current transformer using active elements. In the figure, l is an iron core, and this iron core l has a primary winding 2 with N 1 turns on the primary side and a secondary winding with N 2 turns on the secondary side. It has 3. 4 is an operational amplifier, the inverting input part of which is connected to one output terminal 5 of the secondary winding 3;
The non-inverting input section is connected to the other output terminal 6 of the secondary winding 3. Further, a feedback resistor 7 is connected between the inverting input section and the output section of the operational amplifier 4.
8 and 9 are the output terminals of the current transformer, and the output voltage v p
occurs. Note that the non-inverting input portion of the operational amplifier 4 is commonly connected to the terminals 6 and 9 to be grounded.
而して、第1図のような誤差補償形変流器は
I1/I2=N2/N1=K ……(1)
vp=I2・RF=−I1/K・RF ……(2)
の関係が成立する。但し、I1は1次巻線2の1
次電流、I2は2次巻線3の2次電流、RFは帰還
抵抗7の抵抗値である。ところで、第1図の回路
構成によつて誤差の改善される理由は次の通りで
ある。2次巻線3の出力端子5,6が演算増幅器
4の入力部に接続されているので、増幅器4の利
得が充分大きければ端子5−6間の電位e5-6は
ほぼ零となる。つまり、鉄心1の2次巻線3の2
次負担が零となつて誤差が改善される。 Therefore, the error compensation type current transformer as shown in Fig. 1 has the following equation: I 1 /I 2 =N 2 /N 1 =K (1) v p =I 2・R F =−I 1 /K・R F ……(2) holds true. However, I 1 is 1 of primary winding 2
The secondary current, I 2 is the secondary current of the secondary winding 3, and R F is the resistance value of the feedback resistor 7. By the way, the reason why the error is improved by the circuit configuration shown in FIG. 1 is as follows. Since the output terminals 5 and 6 of the secondary winding 3 are connected to the input section of the operational amplifier 4, if the gain of the amplifier 4 is sufficiently large, the potential e 5-6 between the terminals 5-6 becomes approximately zero. In other words, 2 of the secondary winding 3 of the iron core 1
The next load becomes zero and the error is improved.
しかし、実験結果によると、誤差は完全に零と
ならず、高精度を必要とする変流器にあつては特
に励磁電流に伴う位相角誤差に問題があつた。 However, according to experimental results, the error was not completely zero, and in current transformers that required high precision, there was a problem particularly with the phase angle error associated with the excitation current.
このような誤差が完全に補償されない原因につ
いて検討してみると、2次巻線3の2次漏れイン
ピーダンスおよび励磁インピーダンスの存在によ
るものと考えられ、以下そのことについて説明す
る。今、第1図を等価回路で表わせば第2図のよ
うになる。第2図において3は第1図の2次巻線
3に相当し、Z2はその巻線3の2次漏れインピー
ダンス、E2は励磁インピーダンスによる2次誘
起電圧を示している。2次巻線3の出力端子5,
6を短絡している短絡線10は演算増幅器4の働
きによつて端子5が仮想接地されるためである。
従つて、端子5−6間を仮想接地と考えれば、e
5-6=0となり、次式が成立する。 Examining the reason why such an error is not completely compensated, it is believed that it is due to the presence of secondary leakage impedance and excitation impedance of the secondary winding 3, and this will be explained below. Now, if Figure 1 is expressed as an equivalent circuit, it will be as shown in Figure 2. In FIG. 2, 3 corresponds to the secondary winding 3 of FIG. 1, Z 2 represents the secondary leakage impedance of the winding 3, and E 2 represents the secondary induced voltage due to the excitation impedance. Output terminal 5 of secondary winding 3,
This is because the terminal 5 is virtually grounded by the operation of the operational amplifier 4 due to the shorting line 10 that short-circuits the terminal 6.
Therefore, if we consider the space between terminals 5 and 6 as virtual ground, e
5-6 = 0, and the following formula holds true.
E2+I2・Z2=0
∴E2=−I2Z2 ……(3)
しかし、(3)式に示すように、端子5−6間を短
絡しても誤差の要因である2次誘起電圧E2は完
全に零とならず、2次巻線3の2次漏れインピー
ダンスZ2のために、その電圧降下分の値を持つて
しまうことを示している。従つて、この電圧E2
によつてわずかの励磁電流が発生し、これが位相
角誤差の生ずる原因となつている。すなわ、2次
電圧e5-6を零としても、2次誘起電圧E2は零と
はならずこれが誤差の原因となつている。 E 2 +I 2・Z 2 =0 ∴E 2 =−I 2 Z 2 ...(3) However, as shown in equation (3), even if terminals 5 and 6 are shorted, 2 is a cause of error. This shows that the secondary induced voltage E 2 does not become completely zero, but has a value corresponding to the voltage drop due to the secondary leakage impedance Z 2 of the secondary winding 3. Therefore, this voltage E 2
This generates a small excitation current, which causes phase angle errors. In other words, even if the secondary voltage e 5-6 is made zero, the secondary induced voltage E 2 does not become zero, which causes an error.
本発明は上記実情にかんがみてなされたもの
で、その目的とするところは、主鉄心側2次巻線
に該2次巻線から負荷側をみた電圧がほぼ零とな
る能動負荷を接続して機器が負荷の影響を受けな
いようにするとともに、主鉄心側2次巻線の2次
誘起電圧及び2次漏れインピーダンスによつて生
ずる誤差を負荷とは無関係に補償インピーダンス
を入れて補償することにより、高精度に電流変換
でき、任意の負荷を接続してもその度に補償イン
ピーダンスを可変する必要がなく、また小容量の
補償インピーダンスで補償し得る誤差補償形変流
器を提供することにある。 The present invention has been made in view of the above circumstances, and its purpose is to connect an active load to the main core side secondary winding so that the voltage seen from the secondary winding to the load side is almost zero. In addition to ensuring that the equipment is not affected by the load, the error caused by the secondary induced voltage of the secondary winding on the main core side and the secondary leakage impedance is compensated for by inserting a compensation impedance regardless of the load. The object of the present invention is to provide an error compensation type current transformer that can convert current with high accuracy, eliminates the need to vary the compensation impedance each time an arbitrary load is connected, and can compensate with a small capacity compensation impedance. .
以下、本発明の一実施例について第3図を参照
して説明する。同図において21は主鉄心、22
は補助鉄心、23は鉄心21,22に共通の1次
巻線であつて巻数N11で巻装されている。24は
主鉄心21に巻数N21で巻装してなる主鉄心側2
次巻線、25は補助鉄心22の2次巻線であつて
主鉄心側2次巻線24と同極性でかつ巻数N31で
巻装されている。そして、主鉄心側2次巻線24
の一端は、同巻線24の2次誘起電圧及び2次漏
れインピーダンスを補償する補償インピーダンス
Zcを介して演算増幅器26の反転入力部に、ま
た2次巻線24の他端は演算増幅器26の非反転
入力部に接続するとともに接地状態としている。
この演算増幅器24としては、利得の充分大きな
ものを使用し、端子28,29間の電圧がほぼ零
となるようにし、変流器が負荷側の影響を受けな
いようにする。さらに、補助鉄心側2次巻線25
の両端は補償インピーダンスZcと並列に接続
し、主鉄心側2次巻線24の補償インピーダンス
Zcに所定の電流を与えることにより、専ら主鉄
心側2次巻線24の2次誘起電圧及び2次漏れイ
ンピーダンスによつて生ずる誤差を補償するよう
にしている。27は帰還抵抗、30,31は変流
器の出力端子である。 Hereinafter, one embodiment of the present invention will be described with reference to FIG. In the figure, 21 is the main core, 22
is an auxiliary core, and 23 is a primary winding common to cores 21 and 22, which is wound with a number of turns N11 . 24 is the main core side 2 which is wound around the main core 21 with a number of turns N 21 .
The next winding 25 is a secondary winding of the auxiliary core 22, which has the same polarity as the main core side secondary winding 24 and is wound with a number of turns N31 . Then, the main iron core side secondary winding 24
One end of the secondary winding 24 is connected to the inverting input of the operational amplifier 26 via a compensating impedance Z c that compensates for the secondary induced voltage and secondary leakage impedance of the secondary winding 24, and the other end of the secondary winding 24 is connected to the operational amplifier 26. It is connected to the non-inverting input part of the circuit and is grounded.
As the operational amplifier 24, one with a sufficiently large gain is used so that the voltage between the terminals 28 and 29 is approximately zero, so that the current transformer is not affected by the load side. Furthermore, the secondary winding 25 on the auxiliary core side
Both ends of are connected in parallel with the compensation impedance Zc, and the compensation impedance of the secondary winding 24 on the main iron core side
By applying a predetermined current to Zc, errors caused exclusively by the secondary induced voltage and secondary leakage impedance of the main core side secondary winding 24 are compensated for. 27 is a feedback resistor, and 30 and 31 are output terminals of the current transformer.
而して、第3図を等価回路で表わすと第4図の
ようになる。この第4図においてZ3,E3は主鉄
心側2次巻線24の2次漏れインピーダンスおよ
び2次誘起電圧を示し、またZ4,E4は補助鉄心
側2次巻線25の2次漏れインピーダンスおよび
2次誘起電圧である。なお、2次漏れインピーダ
ンスと2次漏洩インピーダンスとは同一の概念で
ある。32は演算増幅器26の働きによつて仮想
接地される仮想短絡線である。従つて、第4図の
等価回路から第3図の関係が、成立する。 Therefore, when FIG. 3 is expressed as an equivalent circuit, it becomes as shown in FIG. 4. In FIG. 4, Z 3 and E 3 indicate the secondary leakage impedance and secondary induced voltage of the secondary winding 24 on the main core side, and Z 4 and E 4 indicate the secondary leakage impedance and secondary induced voltage of the secondary winding 25 on the auxiliary core side. leakage impedance and secondary induced voltage. Note that the secondary leakage impedance and the secondary leakage impedance are the same concept. 32 is a virtual short-circuit line that is virtually grounded by the operation of the operational amplifier 26. Therefore, the relationship shown in FIG. 3 is established from the equivalent circuit shown in FIG. 4.
I21=N11/N21・I11 ……(4)
I31=N11/N31・I11 ……(5)
N11/N21=1/k ……(6)
N21/N31=a ……(7)
I31=aI21 ……(8)
とすると、
E3=I21(Z3+Zc)−I31・Zc ……(9)
∴E3=I21・Z3+(1−a)I21・Zc ……(10)
となる。ここで、誤差を零にするためには、そ
の要因となるE3を零になる必要がある。(10)式に
おいてE3=0の条件を求めると、
Zc=Z3/a−1 ……(11)
となる。但し、a>1である。即ち、第3図に
示す構成にあつて本質的に誤差を補償する場合、
補償インピーダンスZcの値は、(11)式で示したよ
うにZ3/(a−1)であればよいことになる。従
つて、以上のような構成とすれば、主鉄心側2次
巻線24と負荷側との間に高利得の演算増幅器を
介挿することにより、2次巻線24側から負荷側
をみた電圧をほぼ零とすることが可能となり、よ
つて2次巻線24と負荷側とを電気的に分離した
構成とすることができる。よつて、補償インピー
ダンスZcは主鉄心側2次巻線24の2次誘起電
圧及び2次漏れインピーダンスによつて生ずる誤
差のみを補償すればよいので、特に可変形のもの
を使用する必要がないばかりか、負荷が変るたび
に補償インピーダンスを可変する必要がなく、ま
た補償インピーダンス及び補助鉄心の容量を小さ
くすることができる。また、主鉄心側2次巻線よ
り得られた電流を高利得の演算増幅器で電圧に変
換して出力するようにしたので、演算増幅器の出
力をそのまま負荷に供給して使用できるものであ
る。 I 21 =N 11 /N 21・I 11 ...(4) I 31 =N 11 /N 31・I 11 ...(5) N 11 /N 21 =1/k ...(6) N 21 /N 31 = a ... (7) I 31 = aI 21 ... (8) Then, E 3 = I 21 (Z 3 + Z c ) - I 31・Z c ... (9) ∴E 3 = I 21・Z 3 + (1-a) I 21・Z c ...(10). Here, in order to make the error zero, it is necessary to make E 3 , which is a factor thereof, zero. If we find the condition for E 3 =0 in equation (10), we get Z c =Z 3 /a-1 (11). However, a>1. That is, when essentially compensating for errors in the configuration shown in FIG.
The value of the compensation impedance Z c may be Z 3 /(a-1) as shown in equation (11). Therefore, with the above configuration, by inserting a high gain operational amplifier between the main core side secondary winding 24 and the load side, the load side is It becomes possible to reduce the voltage to almost zero, and thus it is possible to have a configuration in which the secondary winding 24 and the load side are electrically separated. Therefore, since the compensating impedance Zc only needs to compensate for the error caused by the secondary induced voltage of the secondary winding 24 on the main core side and the secondary leakage impedance, there is no need to use a variable type compensating impedance Zc. Moreover, it is not necessary to change the compensation impedance every time the load changes, and the compensation impedance and the capacity of the auxiliary core can be reduced. Furthermore, since the current obtained from the secondary winding on the main iron core side is converted into voltage by a high gain operational amplifier and output, the output of the operational amplifier can be directly supplied to the load for use.
なお、本発明は上記実施例に限定されるもので
はないことは言うまでもない。即ち、第3図で
は、Zcは(11)式で表わしたが、Z3は2次巻線24
の直流抵抗r3とみなして、|Z3|≒r3とすれば、
Zc=r3/a−1 ……(12)
となり、第5図のように補償インピーダンスZ
cは単なる抵抗Rcであつてもよいものである。 It goes without saying that the present invention is not limited to the above embodiments. That is, in FIG. 3, Z c is expressed by equation (11), but Z 3 is expressed by the secondary winding 24
If |Z 3 |≒r 3 , then Z c = r 3 /a-1 ... (12), and the compensation impedance Z is
c may be a simple resistance R c .
また、第3図では、N21/N31=aとしたが、a
>1の関係であればaは任意の値でよいものであ
る。 In addition, in Figure 3, N 21 /N 31 = a, but a
If the relationship is >1, a can be any value.
さらに、第3図では、1導電流I11に比例した
電圧vpを出力しているが、V/I変換を行なう
回路を用いてI11に比例する電圧又は電流の何れ
の信号を出力してもよいものである。 Furthermore, in Fig. 3, a voltage v p proportional to one conduction current I 11 is output, but it is possible to output either a voltage or current signal proportional to I 11 using a circuit that performs V/I conversion. It is a good thing.
以上詳記したように本発明によれば、鉄心の2
次巻線の2次漏れインピーダンスと等しい補償イ
ンピーダンス又は純抵抗からなる補償素子を2次
巻線に挿入するとともに、該2次巻線に補償イン
ピーダンス又は純抵抗からなる補償素子を介して
高利得の演算増幅器を接続したことにより、負荷
側と無関係に高精度に補償できるばかりでなく、
小容量の補償素子で比較的簡単に補償できる。ま
た、種々の負荷を接続することが可能であるとと
もに、負荷が変る度に補償素子を可変する必要が
ないなどの種々の効果を有するものである。 As detailed above, according to the present invention, two iron cores
A compensation element made of a compensation impedance or pure resistance equal to the secondary leakage impedance of the secondary winding is inserted into the secondary winding, and a high gain By connecting an operational amplifier, not only can compensation be performed with high accuracy regardless of the load side, but also
Compensation can be achieved relatively easily with a small capacitance compensation element. Further, it has various effects such as being able to connect various loads and eliminating the need to change the compensation element every time the load changes.
また、補助鉄心側2次巻線は主鉄心側2次巻線
の2次漏れインピーダンス分のみ(a=2の時)
又はその1/aだけをその負荷とする((11)式のZ
c))だけでよいので、小形の鉄心を用いて誤差補
償を行うことができる。 In addition, the secondary winding on the auxiliary core side only corresponds to the secondary leakage impedance of the secondary winding on the main core side (when a = 2)
Or, let only 1/a be the load (Z in equation (11)
Since only c )) is required, error compensation can be performed using a small iron core.
第1図は能動素子を用いた従来の誤差補償形変
流器の構成図、第2図は第1図の等価回路図、第
3図は本発明に係る誤差補償形変流器の一実施例
を示す構成図、第4図は第3図の等価回路図、第
5図は本発明の他の例を示す構成図である。
21……主鉄心、22……補助鉄心、23……
1次巻線、24……主鉄心側2次巻線、25……
補助鉄心側2次巻線、26……演算増幅器、27
……帰還抵抗、Zc……補償インピーダンス、Rc
……補償抵抗。
Fig. 1 is a block diagram of a conventional error-compensating current transformer using active elements, Fig. 2 is an equivalent circuit diagram of Fig. 1, and Fig. 3 is an implementation of an error-compensating current transformer according to the present invention. FIG. 4 is an equivalent circuit diagram of FIG. 3, and FIG. 5 is a configuration diagram showing another example of the present invention. 21... Main iron core, 22... Auxiliary iron core, 23...
Primary winding, 24...Main core side secondary winding, 25...
Auxiliary core side secondary winding, 26... operational amplifier, 27
...Feedback resistance, Z c ... Compensation impedance, R c
...Compensation resistance.
Claims (1)
心と、前記主鉄心側2次巻線に接続され、この2
次巻線側から負荷側をみた電圧がほぼ零となるよ
うに制御する能動負荷と、この能動負荷と主鉄心
側2次巻線との間に介挿された該2次巻線の2次
漏れインピーダンスに比例する補償インピーダン
ス又は補償用純抵抗からなる補償素子と、この補
償素子の両端に前記補助鉄心側2次巻線を並列に
接続して該補償素子に所定の電流を流して前記主
鉄心側2次巻線の2次漏れインピーダンスによつ
て生ずる電圧と等しい相殺電圧を生じさせる補償
手段とを備えたことを特徴とする誤差補償形変流
器。1 A main core and an auxiliary core that have a common primary winding, and are connected to the main core side secondary winding, and these two
An active load that is controlled so that the voltage seen from the next winding side to the load side is almost zero, and a secondary winding of the secondary winding that is inserted between this active load and the main core side secondary winding. A compensating element consisting of a compensating impedance proportional to the leakage impedance or a compensating pure resistance is connected in parallel with the secondary winding on the auxiliary core side to both ends of this compensating element, and a predetermined current is passed through the compensating element. An error compensating current transformer comprising compensation means for generating an offset voltage equal to the voltage generated by the secondary leakage impedance of the secondary winding on the iron core side.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12975079A JPS5654020A (en) | 1979-10-08 | 1979-10-08 | Error compensation type current transformer |
| GB8007357A GB2045952B (en) | 1979-03-15 | 1980-03-04 | Current transforming circuits |
| US06/128,300 US4309652A (en) | 1979-03-15 | 1980-03-07 | Current transforming circuits |
| FR8005744A FR2451621B1 (en) | 1979-03-15 | 1980-03-14 | IMPROVEMENTS TO CURRENT TRANSFORMATION CIRCUITS |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12975079A JPS5654020A (en) | 1979-10-08 | 1979-10-08 | Error compensation type current transformer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5654020A JPS5654020A (en) | 1981-05-13 |
| JPS6136695B2 true JPS6136695B2 (en) | 1986-08-20 |
Family
ID=15017268
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12975079A Granted JPS5654020A (en) | 1979-03-15 | 1979-10-08 | Error compensation type current transformer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5654020A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4749940A (en) * | 1986-12-22 | 1988-06-07 | General Electric Company | Folded bar current sensor |
| RU2647875C2 (en) * | 2016-07-05 | 2018-03-21 | Общество с ограниченной ответственностью научно-производственная фирма "Квазар" | Method of compensation of current transformer errors in transient modes |
-
1979
- 1979-10-08 JP JP12975079A patent/JPS5654020A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5654020A (en) | 1981-05-13 |
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