JPS6137655B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a high-speed address translation device in an information processing system using multiple virtual memory.

As shown in FIG. 1, a conventional high-speed address translation device includes an address comparator 103a that stores at least a part of a segment number 100a that is a part of a virtual address 100, and a real address section 103b that stores a segment start address 101a. and a size section 103c storing information 101b indicating the segment length.
In order to avoid referencing other areas by mistake, if an address translation pair corresponding to the virtual address 100 exists in the address translation buffer 103, the intra-segment address 100b in the virtual address and the contents of the size field 103c are compared. , in the address translation buffer 103, the segment size 101b in the segment table 101 existing on the main memory is compared with the intra-segment address 100b.

Since there are various sizes of segments, placing them within the intra-segment address 100b with a fixed number of bits results in a reduction in the usage rate of virtual addresses or complexity in management due to segment division. To prevent this, for example, the number of bits in the segment address 100b is set to two types, and when the number of bits in the segment address 100b is 16 bits, it is called a small segment, and when it is 22 bits, it is called a large segment. There is a method of allocating to either large or small segments. In this method, the segment size is 10
1b also requires 16 bits for a small segment and 22 bits for a large segment. Note that the number of bits of the virtual address 100 is constant for both large and small segments. If you try to mix these large segments and small segments in the address translation buffer 103, the address comparison unit 103a
must match the bit configuration of the small segment even in the case of the large segment. That is, the large segment is also divided according to the maximum size of the small segment, and each divided segment is registered separately in the address translation buffer 103.

However, even if the large segment is divided and registered separately in the address translation buffer 103, the number of bits in the size part 103c still requires 22 bits, and the total number of bits in the address translation buffer 103 remains the same as before. The disadvantage is that there is no advantage of dividing it into segments. SUMMARY OF THE INVENTION An object of the present invention is to provide a high-speed address translation device that achieves a reduction in the capacity of an address translation buffer.

The device of the present invention includes a virtual address supply means for supplying a virtual address consisting of a segment address and an intra-segment address, and the virtual address information, the real address information corresponding to the virtual address information, and the intra-segment address of the virtual address. address conversion information storage means for storing a plurality of sets of information each including intra-segment address boundary information defining an upper limit, and outputting a detection signal when a segment address given from the virtual address supply means is stored; address boundary supply means for supplying address boundary information; and when a detection signal is given from the address translation information storage means, selects intra-segment address boundary information stored in the address translation information storage means and receives the detection signal. address boundary selection means for selecting address boundary information from the intra-segment address boundary supply means when there is no address boundary information; and intra-segment address boundary information provided from the intra-segment address boundary supply means in response to the selection operation of the address boundary selection means; an address comparison means for comparing the upper bits with the upper bits of the intra-segment address given from the virtual address supply means; and when the comparison results of the address comparison means match, the address comparison means compares the intra-segment address boundary information from the address boundary supply means; The present invention is characterized in that it includes means for setting lower bits to a specific value to use as intra-segment address boundary information of the address translation information storage means.

Next, the present invention will be explained in detail with reference to the drawings. In FIG. 2, when virtual address 100 is set in virtual address device 200, address translation buffer 103 is referenced by all or part of segment number 100a.

If the desired address translation pair does not exist in the address translation buffer 103, the address translation pair detection signal 3 from the address translation buffer 103 is
00, the address boundary selection means 202 selects the address translation pair from the address boundary device 201.

The address boundary device 201 includes a segment size 101b read from main memory (not shown).
is set, and the segment size 101b and the intra-segment address 100b in the virtual address device 200 are compared in the address boundary comparison means 203.

Here, the number of bits between the intra-segment address 100b and the segment size 101b is 16 bits for a small segment, and 16 bits for a large segment.
It is assumed that there are 22 bits, and large and small segments can be distinguished by the upper 1 bit of the segment number 100a.

For small segments, segment size 1
16 bits of 01b are segment address 100
b is compared with 16 bits, segment size 10
If 1b is equal to or smaller than the intra-segment address 100b, the normal address translation operation is stopped as a memory protection error and control is transferred to the operating system.

Conversely, if the segment size 101b is larger than the intra-segment address 100b, the address conversion operation ends normally and the address boundary comparison means 203 does not output the address boundary change signal 301, so the address boundary change means 204 The device 201 is selected and the 16 bits of the segment size 101b are registered as they are in the size section 103c of the address translation buffer 103 to prepare for the next address translation operation.

Next, in the case of a large segment, the 22 bits of the segment size 101b are compared with the 22 bits of the intra-segment address 100b by the address boundary comparison means 20.
It is compared with 3. Segment size 101
If b is less than or equal to intra-segment address 100b, the operating system intervenes as a storage protection error, as in the case of small segments.

When the segment size 101b is larger than the intra-segment address 100b, the address boundary comparison means 203 compares the upper 6 bits of the 22 bits of the segment size 101b and the upper 6 bits of the 22 bits of the intra-segment address 100b.

As a result of the comparison, if the upper 6 bits of the segment size 101b are larger than the upper 6 bits of the intra-segment address 100b, the address boundary change signal 301 from the address boundary comparison means 203 causes the address boundary change means 204 to change the address boundary device. Segment size 10 from 201
All 16 bits of 1b are registered in the size section 103c of the address translation buffer 103 as logic "1".

Conversely, if the upper 6 bits of the segment size 101b are equal to the upper 6 bits of the intra-segment address 100b, the address boundary comparison means 20
3, the address boundary change signal 301 is not output, and the address boundary change means 204 selects the segment size 101b from the address boundary device 201 as in the case of the small segment. As a result, the lower 16 bits of the segment size 101b are transferred directly to the size section 103 of the address translation buffer 103.
Register to c.

In other words, in the case of a large segment, if the address specified by the segment size 101b and the address specified by the intra-segment address 100b are within the same 64 kilobyte (2 ¹⁶ ) byte boundary area,
Size section 103c of address conversion buffer 103
Register the lower 16 bits of segment size 101b. As a result, the next time an address translation request is given within the same 64 kilobyte boundary area,
Normal memory protection checks can be performed.

Furthermore, if the address specified by the segment size 101b is in a 64-kilobyte boundary area above the address specified by the intra-segment address 100b, all logic "1" information is registered in the size section 103c of the address translation buffer 103. .
Therefore, even if an address translation request is given within the same 64 kilobyte boundary area next time, a memory protection error will never occur.

As described above, by registering in the size section 103c of the address translation buffer 103, if the desired address translation pair exists in the address translation buffer 103, the address translation buffer 10
The size section 103c of the address translation buffer 103 is selected by the address boundary selection means 202 based on the address translation pair detection signal 300 from 3. For both large and small segments,
The output of the address boundary selection means 202 and the 16 bits of the intra-segment address 100b are compared by the address boundary comparison means 203. If the output of the address boundary selection means 202 is smaller than 16 bits of the intra-segment address, a pre-storage protection error occurs.

In the present invention, the conventional size portion 103c of the address translation buffer 103, which required 22 bits, is reduced to 16 bits.
decreases to bits.

Further, in the present invention, by adopting a method in which a paging function is added to segmentation, it is possible to further increase the reduction in the number of bits in the size section 103c of the address translation buffer 103.
Now, assuming that the page size is 2 kilobytes, the size section 10 of the address translation buffer 103
The number of bits of 3c should be 11 bits. For small segments, segment size 101b is 16
The upper 5 bits are address 1 within the segment.
Size part 1 of the address translation buffer 103 is larger than the upper 5 bits of the 16 bits of 00b.
The segment size of all logic "1" is stored in 03c. In addition, in the case of a large segment, the upper 11 bits of the 22 bits of the segment size 101b are the upper 11 bits of the 22 bits of the intra-segment address 100b.
When the segment size is larger than the bit, the segment size of all logic "1" is stored in the size section 103c of the address translation buffer 103.

Except for the above cases, segment size 101b
Address conversion buffer 1 uses the lower 11 bits of
It is sufficient to store it in the size section 103 of 03.

The present invention has the advantage that by changing and registering the segment size 101b in the address translation buffer 103, the number of bits in the address translation buffer can be reduced compared to the conventional method.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional address conversion device, and FIG. 2 is a block diagram showing an embodiment of the present invention. In FIGS. 1 and 2, 100...virtual address, 100a...segment number, 100
b...Segment address, 101...Segment table, 101a...Segment start address, 101b...Segment size, 102...
...Segment, 103...Address conversion buffer, 103a...Address comparison section, 103b...
Real address part, 103c...Size part, 200...
...virtual address device, 201...address boundary device, 202...address boundary selection means, 203...
. . . address boundary comparison means, 204 . . . address boundary change means, 300 . . . address translation pair detection signal, 301 .

Claims (1)

[Scope of Claims] 1. Virtual address supply means for supplying a virtual address consisting of a segment address and an intra-segment address; the virtual address information, real address information corresponding to the virtual address information, and the intra-segment address of the virtual address; address translation information storage means for storing a plurality of sets of information, one set of intra-segment address boundary information defining an upper limit of the address conversion information, and outputting a detection signal when a segment address given from the virtual address supply means is stored; address boundary supply means for supplying the address boundary information; and when a detection signal is given from the address translation information storage means, selects intra-segment address boundary information stored in the address translation information storage means; address boundary selection means for selecting address boundary information from the intra-segment address boundary supply means when the intra-segment address boundary supply means is not available; and intra-segment address boundary information provided from the intra-segment address boundary supply means in response to the selection operation of the address boundary selection means. address comparing means for comparing the upper bits of the intra-segment address supplied from the virtual address supply means with the upper bits of the intra-segment address given from the virtual address supply means; and when the comparison results of this address comparison means match, the intra-segment address boundary from the address boundary supply means; 1. A high-speed address translation device comprising: means for setting lower bits of information to a specific value to use as intra-segment address boundary information of the address translation information storage means.