JPS6137773B2 - - Google Patents
Info
- Publication number
- JPS6137773B2 JPS6137773B2 JP55041644A JP4164480A JPS6137773B2 JP S6137773 B2 JPS6137773 B2 JP S6137773B2 JP 55041644 A JP55041644 A JP 55041644A JP 4164480 A JP4164480 A JP 4164480A JP S6137773 B2 JPS6137773 B2 JP S6137773B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor layer
- type
- metal film
- melting point
- point metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/01—Manufacture or treatment
- H10W10/031—Manufacture or treatment of isolation regions comprising PN junctions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/30—Isolation regions comprising PN junctions
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- Recrystallisation Techniques (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置の製造方法に関し、詳しく
はアイソレーシヨン領域で素子分離されたエピタ
キシヤル基体の形成手段を改良した半導体装置の
製造方法に係る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device in which a means for forming an epitaxial substrate whose elements are separated in an isolation region is improved.
従来、バイポーラデイバイスの基体として用い
られるエピタキシヤル基体は半導体基板に所望の
エピタキシヤル層を気相成長することにより造ら
れる。こうして得られたエピタキシヤル基体のエ
ピタキシヤル層にトランジスタ等の素子を形成す
るには例えば第1図に示すようにn+埋込層2が
形成されたp-シリコン基板1上のn型エピタキ
シヤル層3に拡散マスク4を介してボロン等のp
型不純物を拡散して予め素子分離のためのp+型
アイソレーシヨン領域5を設ける必要がある。し
かしながら、かかる従来法にあつては、エピタキ
シヤル層を成長するに際し、高価な気相成長装置
を用いる必要があり、しかも所望のエピタキシヤ
ル層を得るためには成長温度等を厳密に制御しな
ければならず生産性の低下要因になる欠点があ
る。また、p+型アイソレーシヨン領域の形成に
あたつては、第1図に示すように水平方向への拡
散が伴なうため、デイバイスの高集積化が損なわ
れる欠点がある。 Conventionally, epitaxial substrates used as substrates for bipolar devices are fabricated by vapor phase growth of a desired epitaxial layer on a semiconductor substrate. To form elements such as transistors on the epitaxial layer of the epitaxial substrate thus obtained, for example, as shown in FIG. P such as boron is applied to the layer 3 through the diffusion mask 4.
It is necessary to provide in advance a p + -type isolation region 5 for element isolation by diffusing type impurities. However, in such conventional methods, it is necessary to use an expensive vapor phase growth apparatus when growing the epitaxial layer, and the growth temperature etc. must be strictly controlled in order to obtain the desired epitaxial layer. There are drawbacks that inevitably lead to a decrease in productivity. Furthermore, in forming the p + -type isolation region, diffusion in the horizontal direction is involved, as shown in FIG. 1, which has the disadvantage of impairing high integration of devices.
これに対し、本発明は上記欠点を克服すべく
種々検討した結果、単結晶の半導体基板上に第一
導電型の不純物を含む非結晶性半導体層わ被覆
し、更に該半導体層の所望部分を高融点金属膜で
覆い、これをマスクとして第二導電型の不純物を
半導体層に選択的にイオン注入した後、レーザ光
を照射した場合、非結晶性半導体層は単結晶半導
体基板よりはるかにレーザ光のエネルギーを吸収
し易く、かつ前記高融点金属膜の反射性により該
金属膜で覆われた領域以外の非結晶性半導体層が
単結晶半導体基板を結晶核としてそれと接する部
分から単結晶化すると共に、前記第二導電型のイ
オン注入部が拡散されて第二導電型の単結晶半導
体層を選択的に形成できることを究明した。しか
も、前記高融点金属膜を除去した後、再度レーザ
光を照射した場合、前述の如くレーザ光のエネル
ギー吸収は単結晶半導体に比べて非結晶性半導体
層の方が大きいために、高融点金属膜が除去され
た非結晶性半導体層部分は選択的に溶融し、同様
に単結晶化され、一方既に形成された第二導電型
の単結晶半導体層はレーザ光のエネルギーをほと
んど吸収せず熱効果を受けることがないために該
単結晶半導体層中の第二導電型の不純物が横方向
等に再拡散することはないことを究明した。 On the other hand, as a result of various studies to overcome the above drawbacks, the present invention has been developed by coating a single-crystal semiconductor substrate with an amorphous semiconductor layer containing impurities of the first conductivity type, and further covering desired portions of the semiconductor layer. When a semiconductor layer is covered with a high melting point metal film and used as a mask to selectively ion-implant impurities of the second conductivity type into the semiconductor layer and then irradiated with laser light, the amorphous semiconductor layer is much more sensitive to the laser than the single crystal semiconductor substrate. The non-crystalline semiconductor layer, which easily absorbs light energy and is reflective of the high-melting point metal film, forms a single crystal from the portion in contact with the single-crystal semiconductor substrate, using the single-crystal semiconductor substrate as a crystal nucleus due to the reflective property of the high-melting-point metal film. In addition, it has been found that the second conductivity type ion implantation portion can be diffused to selectively form a second conductivity type single crystal semiconductor layer. Moreover, when the laser beam is irradiated again after the high melting point metal film is removed, the energy absorption of the laser beam is greater in the amorphous semiconductor layer than in the single crystal semiconductor, as described above. The portion of the amorphous semiconductor layer from which the film has been removed is selectively melted and similarly becomes single crystallized, while the already formed single crystal semiconductor layer of the second conductivity type absorbs almost no energy from the laser beam and is heated. It has been found that the second conductivity type impurity in the single crystal semiconductor layer does not re-diffuse in the lateral direction because it is not affected by this effect.
しかして、本発明者は上記知見に基づき更に鋭
意研究した結果、半導体基板上に第一導電型の不
純物を含む非結晶性半導体層を被覆し、この半導
体層の所望部分を高融点金属膜で覆い、これをマ
スクとして第二導電型の不純物を前記半導体層部
分にイオン注入した後、レーザ光の照射を施すこ
とによつて、高融点金属膜以外の露出した半導体
層部分を第二導電型の単結晶半導体層に変換でき
る。しかるに、高融点金属膜を除去した後、再度
レーザ光の照射を施すことによつて、前記工程で
形成された単結晶半導体層中の第二導電型の不純
物の再拡散を招くことなく、高融点金属膜が除去
された第一導電型の不純物を含む非結晶性半導体
層部分を第一導電型の単結晶半導体層に変換でき
る。その結果、マスクとなる高融点金属膜に対す
るパターン変換差がほとんどなく、所定幅の単結
晶半導体層からなるアイソレーシヨン領域で分離
されたこれと反対導電型の単結晶半導体層を半導
体基板上に極めて簡単かつ再現性よく形成でき、
この基体のアイソレーシヨン領域で分離された単
結晶半導体層にバイポーラトランジスタ等を形成
することによつて高集積度化、高信頼性の半導体
装置を製造し得る方法を見い出した。 As a result of further intensive research based on the above findings, the inventors of the present invention coated a semiconductor substrate with an amorphous semiconductor layer containing impurities of the first conductivity type, and covered desired portions of this semiconductor layer with a refractory metal film. After ion-implanting impurities of the second conductivity type into the semiconductor layer portion using this as a mask, the exposed semiconductor layer portion other than the high melting point metal film is converted to the second conductivity type by irradiating with laser light. can be converted into a single crystal semiconductor layer. However, by irradiating the high melting point metal film again with laser light, the high melting point metal film can be removed without causing re-diffusion of the second conductivity type impurity in the single crystal semiconductor layer formed in the above step. The portion of the amorphous semiconductor layer containing first conductivity type impurities from which the melting point metal film has been removed can be converted into a first conductivity type single crystal semiconductor layer. As a result, there is almost no pattern conversion difference with respect to the high-melting point metal film that serves as a mask, and a single crystal semiconductor layer of the opposite conductivity type separated by an isolation region consisting of a single crystal semiconductor layer of a predetermined width is placed on the semiconductor substrate. It can be formed extremely easily and with good reproducibility.
We have discovered a method for manufacturing highly integrated and highly reliable semiconductor devices by forming bipolar transistors and the like in single-crystal semiconductor layers separated by isolation regions of this substrate.
以下、本発明を詳細に説明する。 The present invention will be explained in detail below.
まず、半導体基板上にCVD法等により第一導
電型の不純物を含む非結晶性半導体層を被覆す
る。この半導体層中の不純物はn型(例えば砒
素、リン等)またはp型(例えばボロン等)であ
る。また、前記非結晶性半導体層の被覆にあたつ
ては、従来のエピタキシヤル層を形成するような
高価な気相成長装置は必要とせず、しかも厳格か
つ煩雑な気相成長制御を要せず、極めて簡単に行
なえる。つづいて、前記非結晶性半導体層の所望
部分を例えば写真蝕刻法等により高融点金属膜で
覆う。この高融点金属膜はこの後に示す第二導電
型の不純物のイオン注入に際しての注入マスクと
して作用すると共に、レーザ光の照射に際しても
該レーザ光を反射してレーザ光のマスクとして作
用する。かかる高融点金属としては、例えばモリ
ブデン、タンタル、タングステン等を挙げること
ができる。高融点金属膜で覆う非結晶性半導体部
分を具体的に例示すると、素子領域形成予定部又
はアイソレーシヨン領域形成予定部である。こう
した二つの形成予定部の被覆選択的にあたつて
は、非結晶性半導体層の導電型(又はイオン注入
する不純物の導電型)によつて行なえばよい。 First, an amorphous semiconductor layer containing impurities of a first conductivity type is coated on a semiconductor substrate by a CVD method or the like. The impurities in this semiconductor layer are n-type (eg, arsenic, phosphorus, etc.) or p-type (eg, boron, etc.). Furthermore, in coating the amorphous semiconductor layer, there is no need for expensive vapor phase growth equipment that is required for forming conventional epitaxial layers, and there is no need for strict and complicated vapor phase growth control. , is extremely easy to do. Subsequently, a desired portion of the amorphous semiconductor layer is covered with a high melting point metal film by, for example, photolithography. This high melting point metal film acts as an implantation mask during ion implantation of a second conductivity type impurity, which will be described later, and also functions as a mask for laser light by reflecting the laser light during irradiation with laser light. Examples of such high melting point metals include molybdenum, tantalum, and tungsten. A specific example of the amorphous semiconductor portion covered with the high melting point metal film is a portion where an element region is to be formed or a portion where an isolation region is to be formed. The selective coating of these two formation regions may be done depending on the conductivity type of the amorphous semiconductor layer (or the conductivity type of the impurity to be ion-implanted).
次いで、前記高融点金属膜をマスクとして該金
属膜以外の露出した非結晶性半導体層部分に第二
導電型の不純物をイオン注入した後、レーザ光の
照射を施す。このイオン注入条件はその目的から
高融点金属膜下の半導体層まで通過せず、露出し
た半導体層部分に十分不純物を注入し得るエネル
ギー条件で行なう必要がある。かかる第二導電型
の不純物とは、前記半導体層中の不純物がn型の
場合、p型であり、同半導体層中の不純物がp型
の場合、n型である。レーザ光の照射は露出する
イオン注入された非結晶性半導体層を選択的に溶
融し、第二導電型の単結晶半導体層に変換させる
観点から、非結晶性半導体層のみにエネルギーが
吸収される波長のレーザ光を選定する必要があ
る。かかるレーザ光としては、例えば波長1.06μ
mのNd−YAGレーザ光等を用いることができ
る。つづいて、前記高融点金属膜を除去した後、
再度レーザ光の照射を施す。このレーザ光は前記
レーザ光を同様な波長を有するものを用いること
が必要である。こうしたレーザ照射により金属膜
が除去された第一導電型の不純物を含む非結晶性
半導体層部分、つまり第二導電型の不純物がイオ
ン注入されなかつた半導体層部分が第一導電型の
単結晶半導体層に変換され、半導体基板上に互に
導電型の異なる単結晶半導体層が形成される。そ
の後、これら半導体層の一方をアイソレーシヨン
領域、他方を素子領域とし、この素子領域にバイ
ポーラトランジスタ、MOSトランジスタ等を形
成することにより半導体装置を製造する。なお、
前記素子領域にバイポーラトランジスタ(特に
npnバイポーラトランジスタ)を形成する場合、
通常コレクタのシリーズ抵抗を低減するためにn
+型埋込層を基板と素子領域間に形成していた
が、近年の浅い接合形成技術の進歩により、単結
晶半導体層の厚さを薄くすれば前記埋込層の形成
は不要となる。 Next, using the high melting point metal film as a mask, a second conductivity type impurity is ion-implanted into the exposed amorphous semiconductor layer portion other than the metal film, and then laser light is irradiated. For the purpose of this ion implantation, it is necessary to perform the ion implantation under energy conditions that do not allow the ion to pass through to the semiconductor layer under the high-melting point metal film, but to sufficiently implant the impurity into the exposed portion of the semiconductor layer. The impurity of the second conductivity type is p-type when the impurity in the semiconductor layer is n-type, and is n-type when the impurity in the semiconductor layer is p-type. Laser light irradiation selectively melts the exposed ion-implanted amorphous semiconductor layer and converts it into a second conductivity type single crystal semiconductor layer, meaning that energy is absorbed only in the amorphous semiconductor layer. It is necessary to select the wavelength of the laser beam. Such a laser beam may have a wavelength of 1.06μ, for example.
A Nd-YAG laser beam or the like can be used. Subsequently, after removing the high melting point metal film,
Apply laser light irradiation again. It is necessary to use a laser beam having a wavelength similar to that of the laser beam. The portion of the amorphous semiconductor layer containing impurities of the first conductivity type from which the metal film has been removed by such laser irradiation, that is, the portion of the semiconductor layer in which the impurities of the second conductivity type have not been ion-implanted, is a single crystal semiconductor of the first conductivity type. single crystal semiconductor layers having mutually different conductivity types are formed on the semiconductor substrate. Thereafter, one of these semiconductor layers is used as an isolation region and the other as an element region, and a bipolar transistor, a MOS transistor, etc. are formed in this element region to manufacture a semiconductor device. In addition,
A bipolar transistor (especially
When forming an npn bipolar transistor),
Normally, n is used to reduce the series resistance of the collector.
A + type buried layer was formed between the substrate and the element region, but with recent advances in shallow junction formation technology, the formation of the buried layer becomes unnecessary if the thickness of the single crystal semiconductor layer is reduced.
次に、本発明をバイポーラ集積回路の製造に適
した例について図面を参照して説明する。 Next, an example of the present invention suitable for manufacturing a bipolar integrated circuit will be described with reference to the drawings.
実施例 1
〔〕 まず、第2図aに示すように比抵抗30〜
50Ω−cmのp-型シリコン基板11上にn型不
純物であるリンを5×1016/cm3ドープした非結
晶性シリコン層12を厚さ0.8μm堆積した
後、全面に厚さ1.0μmのモリブデン膜を真空
蒸着し、写真蝕刻法によりパターニングして素
子形成領域となるべき非結晶性シリコン基層1
2上をモリブデン膜13で覆つた。Example 1 [] First, as shown in Figure 2 a, the specific resistance is 30~
After depositing a 0.8 μm thick amorphous silicon layer 12 doped with 5×10 16 /cm 3 of phosphorus, which is an n-type impurity, on a 50 Ω-cm p - type silicon substrate 11, a 1.0 μm thick layer was deposited on the entire surface. An amorphous silicon base layer 1 to be formed into an element formation region by vacuum-depositing a molybdenum film and patterning it by photolithography.
2 was covered with a molybdenum film 13.
〔〕 次いで、p型不純物であるボロンを出力
50Kev、ドーズ量1×1014/cm2の条件で全面に
イオン注入してモリブデン膜13以外の露出す
る非結晶性シリコン層12部分にドープした後、
波長1.06μm、パルス巾200nsec、エネルギー
密度5J/cm2のNd−YAGレーザ光を全面に照射
した。この時、モリブデン膜13の存在しない
イオン注入非結晶性シリコン層12部分が溶融
し、液相エピタキシイによつて単結晶化すると
共に表面近傍にドープされたボロンは急速に拡
散し、p-型シリコン基板11に達し、第2図
bに示すように不純物濃度1×1018/cm3のp型
アイソレーシヨン領域14が形成された。な
お、モリブデン膜13下の非結晶性シリコン層
12部分はレーザ光を影響を受けず非結晶性の
状態のまま残つた。[] Next, boron, which is a p-type impurity, is output
After doping the exposed portion of the amorphous silicon layer 12 other than the molybdenum film 13 by implanting ions into the entire surface under the conditions of 50Kev and a dose of 1×10 14 /cm 2 ,
The entire surface was irradiated with Nd-YAG laser light having a wavelength of 1.06 μm, a pulse width of 200 nsec, and an energy density of 5 J/cm 2 . At this time, the portion of the ion-implanted amorphous silicon layer 12 where the molybdenum film 13 does not exist melts and becomes single crystallized by liquid phase epitaxy, and the boron doped near the surface rapidly diffuses to form p - type silicon. The p-type isolation region 14 having an impurity concentration of 1×10 18 /cm 3 was formed as shown in FIG. 2b. Note that the portion of the amorphous silicon layer 12 under the molybdenum film 13 was not affected by the laser light and remained in an amorphous state.
〔〕 次いで、モリブデン膜13をリン酸系の
エツチヤントで除去し、再度波長1.06μm、パ
ルス巾200nsec、エネルギー密度5J/cm2のNd−
YAGレーザ光を全面照射した。この時モリブ
デン膜13が除去されることにより露出したリ
ンドープ非結晶性シリコン層12部分が液相エ
ピタキシイによつて単結晶化し、第2図cに示
すように比抵抗0.2Ω−cm、接合深さ0.8μm
で、不純物濃度がシリコン堆積時と同等のn型
エピタキシヤル領域15(素子形成領域)が形
成された。その後、n型エピタキシヤル領域1
5に常法に従つてρs=800Ω/□、接合深さ
0.5μmのp型内部ベース領域16、p+型外部
ベース領域17を形成し、更に内部ベース領域
16内にρs=20Ω/□、接合深さ0.6μmの
n+型エミツタ領域18、及びコレクタ領域と
してのn型エピタキシヤル領域15にn+コレ
クタ電極接触領域19を形成した後、シリコン
酸化膜20の成長、コンタクトホール21…2
1の開孔及びAl膜を男蒸着、パターニングに
よりベース、エミツタ、コレクタと接続する
Al配線22,23,24を形成してバイポー
ラ集積回路を製造した(第2図d図示)。[] Next, the molybdenum film 13 was removed with a phosphoric acid-based etchant, and again Nd- with a wavelength of 1.06 μm, a pulse width of 200 nsec, and an energy density of 5 J/cm 2
The entire surface was irradiated with YAG laser light. At this time, the portion of the phosphorus-doped amorphous silicon layer 12 exposed by removing the molybdenum film 13 is made into a single crystal by liquid phase epitaxy, and as shown in FIG. 0.8μm
Thus, an n-type epitaxial region 15 (element formation region) was formed with an impurity concentration equivalent to that during silicon deposition. After that, the n-type epitaxial region 1
5, according to the usual method, ρs = 800Ω/□, junction depth
A p type internal base region 16 of 0.5 μm and a p + type external base region 17 are formed, and furthermore, an n + type emitter region 18 with ρs = 20Ω/□ and a junction depth of 0.6 μm and a collector region are formed in the internal base region 16. After forming an n + collector electrode contact region 19 in the n-type epitaxial region 15 as a base, a silicon oxide film 20 is grown and contact holes 21...2 are formed.
Connect the openings in No. 1 and the Al film to the base, emitter, and collector by vapor deposition and patterning.
A bipolar integrated circuit was manufactured by forming Al wirings 22, 23, and 24 (as shown in FIG. 2d).
上記実施例1において、モリブデン膜13を
マスクとして利用し、レーザ光の照射を併用す
ることによつて、p型アイソレーシヨン領域1
4と素子形成領域としてのn型エピタキシヤル
領域15とを簡便に形成でき、かつ両領域1
4,15の寸法をモリブデン膜13の形状によ
つて精度よく規定でき、極めて簡易な製造プロ
セスで高集積化、高信頼性のバイポーラ集積回
路を製造できた。 In the first embodiment, the molybdenum film 13 is used as a mask and the p-type isolation region 1 is
4 and an n-type epitaxial region 15 as an element formation region can be easily formed, and both regions 1 and 15 can be easily formed.
The dimensions of 4 and 15 can be defined with high accuracy depending on the shape of the molybdenum film 13, and a highly integrated and highly reliable bipolar integrated circuit can be manufactured using an extremely simple manufacturing process.
実施例 2
〔〕 まず、第3図aに示すように前記実施例
1と同様なp-型シリコン基板11上にp型不
純物であるボロンを1×1016/cm3ドープした非
結晶性シリコン層12′を厚さ0.8μm堆積した
後、全面に厚さ1.0μmのモリブデン膜を真空
蒸着し、写真蝕刻法によりパターニングしてア
イソレーシヨン領域となるべき非晶質シリコン
層12′上をモリブデン膜13′で覆つた。Example 2 [] First, as shown in FIG. 3a, amorphous silicon doped with boron, which is a p-type impurity, at 1×10 16 /cm 3 is placed on a p - type silicon substrate 11 similar to that in Example 1. After depositing the layer 12' with a thickness of 0.8 μm, a molybdenum film with a thickness of 1.0 μm is vacuum-deposited on the entire surface, and patterned by photolithography to coat the amorphous silicon layer 12', which is to become an isolation region, with molybdenum. It was covered with a membrane 13'.
〔〕 次いで、n型不純物であるリンを出力
50kev、ドーズ量4×1012/cm2の条件で全面に
イオン注入してモリブデン膜13′のマスク作
用によりこの膜13′以外の露出する非結晶性
シリコン層12′部分にドープした後、波長
1.06μm、パルス巾200nsec、エネルギー密度
5J/cm2のNd−YAGレーザ光を全面照射した。
この時、モリブデン膜13′の存在しないイオ
ン注入非結晶性シリコン層12′部分が溶融
し、液相エピタキシイによつて単結晶化すると
共に、表面近傍にドープされたリンは急速に拡
散し、p-型シリコン基板11との界面まで達
し、第3図bに示すように不純物濃度3×
1016/cm3、比抵抗0.2Ω−cm、接合深さ0.8μm
のn型エピタキシヤル領域15′(素子形成領
域)が形成された。[] Next, outputs phosphorus, which is an n-type impurity.
After ion implantation into the entire surface under the conditions of 50keV and a dose of 4×10 12 /cm 2 to dope the exposed amorphous silicon layer 12' except for this film 13' using the masking effect of the molybdenum film 13', the wavelength
1.06μm, pulse width 200nsec, energy density
The entire surface was irradiated with 5J/cm 2 Nd-YAG laser light.
At this time, the portion of the ion-implanted amorphous silicon layer 12' where the molybdenum film 13' does not exist melts and becomes single crystallized by liquid phase epitaxy, and the phosphorus doped near the surface rapidly diffuses and p - type silicon substrate 11, and the impurity concentration is 3× as shown in FIG. 3b.
10 16 /cm 3 , specific resistance 0.2Ω-cm, junction depth 0.8μm
An n-type epitaxial region 15' (element formation region) was formed.
〔〕 次いで、モリブデン膜13′をリン酸系の
エツチヤントで除去し、再度前述したのと同様
な条件のNd−YAGレーザ光を全面照射した。
この時、モリブデン膜13′が除去されること
により露出したボロンドープ非結晶性半シリコ
ン層12′部分が液相エピタキシイによつて単
結晶化し、第3図cに示すように不純物濃度が
非結晶性シリコン層の堆積時と同時のP型アイ
ソレーシヨン領域14′が形成された。その
後、前記実施例1と同様、n型エピタキシヤル
領域15′にnpnバイポーラトランジスタを形
成し、Al配線を設けてバイポーラ集積回路を
製造した。[] Next, the molybdenum film 13' was removed using a phosphoric acid-based etchant, and the entire surface was again irradiated with Nd-YAG laser light under the same conditions as described above.
At this time, the boron-doped amorphous semi-silicon layer 12' exposed by removing the molybdenum film 13' becomes single crystallized by liquid phase epitaxy, and as shown in FIG. 3c, the impurity concentration becomes amorphous. A P-type isolation region 14' was formed at the same time as the silicon layer was deposited. Thereafter, in the same manner as in Example 1, an npn bipolar transistor was formed in the n-type epitaxial region 15', and Al wiring was provided to manufacture a bipolar integrated circuit.
上記実施例2においても極めて簡易な製造プ
ロセスにより高集積度で高信頼性のバイポーラ
集積回路を製造できた。 In Example 2, a highly integrated and highly reliable bipolar integrated circuit was also manufactured using an extremely simple manufacturing process.
以上詳述した如く、本発明によれば半導体基板
上への第一導電型不純物を含む非結晶性半導体層
の被覆、この半導体層上への選択的な高融点金属
膜の被覆、該金属膜をマスクとした第二導電型の
不純物のイオン注入、レーザ光の照射、更には高
融点金属膜の除去後の再度のレーザ光照射の工程
を行なうことによつて、単結晶のアイソレーシヨ
ン領域、素子形成領域を容易に形成できると共
に、両領域の寸法を前記高融点金属膜の形状によ
り精度よく制御でき、もつてこの素子形成領域に
トランジスタ等を形成することにより高集積度で
高信頼性の半導体装置を極めて簡単かつ再現性よ
く製造できる等顕著な効果を有する。 As detailed above, according to the present invention, a semiconductor substrate is coated with an amorphous semiconductor layer containing a first conductivity type impurity, a high melting point metal film is selectively coated on the semiconductor layer, and the metal film is coated with a high melting point metal film. The isolation region of the single crystal is , the element formation region can be easily formed, and the dimensions of both regions can be precisely controlled by the shape of the high melting point metal film, and by forming transistors etc. in this element formation region, high integration and high reliability can be achieved. This method has remarkable effects such as the ability to manufacture semiconductor devices extremely easily and with good reproducibility.
第1図は従来法により製造されたp+アイソレ
ーシヨン領域で分離されたn型エピタキシヤル層
を有する基体の断面図、第2図a〜dは本発明の
実施例1におけるバイポーラ集積回路の製造工程
を示す断面図、第3図a〜cは本発明の実施例2
におけるバイポーラ集積回路の一部の工程を示す
断面図である。
11……p-シリコン基板、12,12′……不
純物ドープ非結晶性シリコン層、13,13′…
…モリブデン膜、14,14′……p型アイソレ
ーシヨン領域、15,15′……n型エピタキシ
ヤル領域(素子形成領域)、16……p型内部ベ
ース領域、17……p+型外部ベース領域、18
……n+型エミツタ領域、19……n+型コレクタ
電極接触領域、20……シリコン酸化膜、22,
23,24……Al電極。
FIG. 1 is a cross-sectional view of a substrate having an n-type epitaxial layer separated by a p + isolation region manufactured by a conventional method, and FIGS. Cross-sectional views showing the manufacturing process, FIGS. 3 a to 3 c are Embodiment 2 of the present invention
FIG. 3 is a cross-sectional view showing some steps of the bipolar integrated circuit in FIG. 11...p - silicon substrate, 12, 12'... impurity-doped amorphous silicon layer, 13, 13'...
...Molybdenum film, 14, 14'...p type isolation region, 15, 15'...n type epitaxial region (element formation region), 16...p type internal base region, 17...p + type external base area, 18
... n + type emitter region, 19 ... n + type collector electrode contact region, 20 ... silicon oxide film, 22,
23, 24...Al electrode.
Claims (1)
結晶性半導体層を被覆する工程と、この非結晶性
半導体層上の所望部分を高融点金属膜で覆う工程
と、この高融点金属膜をマスクとして露出する非
結晶性半導体部分に第二導電型の不純物を選択的
にイオン注入した後、レーザ光の照射を施す工程
と、前記高融点金属膜を除去した後、再度レーザ
光の照射を施す工程とを具備したことを特徴とす
る半導体装置の製造方法。1. A step of coating a semiconductor substrate with an amorphous semiconductor layer containing impurities of a first conductivity type, a step of covering a desired portion of the amorphous semiconductor layer with a high melting point metal film, and a step of covering the high melting point metal film with a high melting point metal film. After selectively ion-implanting a second conductivity type impurity into the amorphous semiconductor portion exposed as a mask, irradiation with laser light is performed, and after removing the high melting point metal film, irradiation with laser light is performed again. 1. A method for manufacturing a semiconductor device, comprising the steps of:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4164480A JPS56146231A (en) | 1980-03-31 | 1980-03-31 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4164480A JPS56146231A (en) | 1980-03-31 | 1980-03-31 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS56146231A JPS56146231A (en) | 1981-11-13 |
| JPS6137773B2 true JPS6137773B2 (en) | 1986-08-26 |
Family
ID=12614039
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4164480A Granted JPS56146231A (en) | 1980-03-31 | 1980-03-31 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS56146231A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW299897U (en) | 1993-11-05 | 1997-03-01 | Semiconductor Energy Lab | A semiconductor integrated circuit |
| JP4967205B2 (en) * | 2001-08-09 | 2012-07-04 | 富士電機株式会社 | Manufacturing method of semiconductor device |
-
1980
- 1980-03-31 JP JP4164480A patent/JPS56146231A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS56146231A (en) | 1981-11-13 |
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