JPS6137781B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a method for manufacturing a semiconductor device having a multilayer wiring structure.

In semiconductor devices, due to the demand for higher integration, techniques for miniaturizing elements and multilayering are being developed. Due to these demands for miniaturization and multilayering, for example, when upper and lower wiring intersect with each other via a thin insulating film, reactive ion etching is used to pattern fine wiring in highly undulating steps with good controllability. Anisotropic etching methods such as (RIE method) are becoming widely used. Such anisotropic etching progresses only in the direction perpendicular to the surface of the semiconductor substrate and does not proceed at all in the parallel direction, so it is advantageous for forming fine wiring as described above. When forming the second layer wiring on the wiring, if the insulating film on the first layer wiring has an overhang structure, the material of the second layer wiring remains near the overhang, and the material between the second layer wiring Invite Shyoto. This will be explained below with reference to FIG. 1, taking as an example the case of a two-layer wiring made of polycrystalline silicon.

First, a polycrystalline silicon layer is deposited on an oxide film on a semiconductor substrate 1, and this is patterned to form a first layer of polycrystalline silicon wiring 2. Then, using the wiring as a mask, a gate oxide film in the source/drain region is formed. etching. Subsequently, a thermal oxidation process is performed to grow an oxide film 4 around the exposed substrate 1 and first layer polycrystalline silicon wiring 2. Subsequently, polycrystalline silicon is deposited on the entire surface and patterned by the RIE method to form second layer polycrystalline silicon interconnections 5, 5 that cross over the first layer polycrystalline silicon interconnection 2 with an oxide film 4 interposed therebetween. .

However, in the above method, the side walls of the first layer wiring 2 are etched due to the difference in oxidation rate between the polycrystalline silicon and the substrate during thermal oxidation after forming the first layer wiring 2 and etching the oxide film using this as a mask. An overhang portion 6 is formed at the bottom. In this state, a second polycrystalline silicon layer is deposited,
When patterning is performed by the RIE method, etching progresses only in the direction perpendicular to the substrate 1, and polycrystalline silicon 7 remains in the shadow portion of the overhang portion 6. As a result, the remaining polycrystalline silicon 7 causes a shortcoming between the second layer polycrystalline silicon wirings 5 and 5.

On the other hand, as a result of extensive research in order to overcome the above-mentioned drawbacks, the inventor of the present invention found that when patterning the wiring material layer on a semiconductor substrate, the wiring material layer is applied to the non-wiring area and the sidewall of the wiring to a certain thickness. By patterning and forming interconnects so as to leave a We have discovered a method for manufacturing a semiconductor device that achieves good multilayer wiring without shorts between wirings in patterning by etching.

That is, the present invention involves a process of depositing a wiring material layer made of polycrystalline silicon or metal silicide on a semiconductor substrate, and a process of depositing a wiring material layer made of polycrystalline silicon or metal silicide on a semiconductor substrate in manufacturing a semiconductor device having multilayer wiring that intersects with each other on a semiconductor substrate. forming a wiring by patterning the wiring so that a thin layer of wiring material remains at least on the side wall of the wiring to be formed and in a non-wiring area, and forming an oxide film around the wiring by performing thermal oxidation treatment. The present invention is characterized in that it comprises a step of forming a second layer of wiring across the wiring on this oxide film by patterning using anisotropic etching.

Examples of the wiring material used in the present invention include polycrystalline silicon containing a high concentration of arsenic, phosphorus, or boron, or metal silicides such as molybdenum silicide, tungsten silicide, and tantalum silicide.

Next, embodiments of the present invention will be described with reference to the drawings.

Embodiment [1] First, a field oxide film 12 is grown on a semiconductor substrate 11, and a phosphorus-doped polycrystalline silicon layer 13 with a thickness of 4000 A° is deposited thereon.
4 and 14 were formed by photolithography (FIG. 2a). Subsequently, photoresist films 14, 14
Using this as a mask, etching was performed using the RIE method so that a polycrystalline silicon thin film 13' with a thickness of about 500 A° remained to form the first layer wiring 15 (second layer).
Figure b).

[] Next, after removing the photoresist films 14, 14, thermal oxidation was performed in an oxygen atmosphere at 1000°C. At this time, a polycrystalline silicon thin film 13' is formed near the boundary between the wiring 15...side wall and the field oxide film 12.
remains, so an overhang portion due to the difference in oxidation rate between the polycrystalline silicon wiring and the field oxide film does not occur at the lower part of the sidewall of the wiring 15, unlike when the thin layer 13' does not exist. Wiring 15... Oxide film 16 with uniform thickness around the periphery
(thickness: 1500A°) was grown (as shown in Figure 2c).

[] Next, as shown in FIG. 2d, a phosphorus-doped polycrystalline silicon layer 17 is deposited on the entire surface, and then patterned by an etching process using the RIE method to form an oxide film 16 on the first layer wiring 15. A semiconductor device was manufactured by forming second-layer interconnections 18 crossing through the semiconductor device (FIGS. 2e and 3). Note that FIG. 3 is a perspective view of FIG. 2e.

Therefore, in this embodiment, the first layer wiring 1
Since thermal oxidation is performed with the polycrystalline silicon thin layer 13' remaining near the boundary between the sidewalls of the first layer interconnects 15 and the field oxide film 12, an oxide film 16 without overhang can be formed around the first layer wirings 15. As a result, when the second layer of phosphorus-doped polycrystalline silicon layer 17 was deposited on the entire surface and patterned by the RIE etching process, the first layer wiring 15 due to the presence of overhang...the surrounding oxide film 16 There is no residual polycrystalline silicon,
As shown in FIG. 3, fine second layer wiring 18 without any shorts between wirings can be formed.

Note that in the above embodiment, the first layer wiring 15...
By leaving a polycrystalline silicon thin layer 13' near the boundary between the sidewall and a gate oxide film (not shown) when forming the field portion, the wiring 15...
When the gate oxide film in the device region is etched using the mask as a mask, the field oxide film is not etched, and as a result, the formation of overhangs due to overetching during thermal oxidation can be prevented.

As described in detail above, the present invention has remarkable effects such as being able to manufacture, at a high yield, a semiconductor device that realizes fine multilayer interconnections without shorts between interconnections due to overhangs.

[Brief explanation of the drawing]

FIG. 1 is a perspective view of a semiconductor device having a two-layer wiring structure manufactured by a conventional method, and FIGS. 2 a to e are cross-sectional views showing the manufacturing process of a semiconductor device having a two-layer wiring structure in an embodiment of the present invention. , FIG. 3 is a perspective view of the semiconductor device of FIG. 2e. DESCRIPTION OF SYMBOLS 11... Semiconductor substrate, 12... Field oxide film, 13, 17... Linden-doped polycrystalline silicon layer, 13'... Polycrystalline silicon thin layer, 15... First layer wiring, 16... Oxide film, 18... ...Second layer wiring.

Claims (1)

[Claims] 1. In manufacturing a semiconductor device equipped with multilayer wiring that intersects with each other on a semiconductor substrate, a step of depositing a wiring material layer made of polycrystalline silicon or metal silicide on the semiconductor substrate, and at least forming this wiring material layer A process of patterning and forming a wiring so that a thin layer of wiring material remains on the sidewalls of the wiring and non-wiring areas, a process of applying thermal oxidation treatment to form an oxide film around the wiring, and a process of oxidizing the wiring. 1. A method of manufacturing a semiconductor device, comprising the step of forming a second layer of wiring on the film by patterning using anisotropic etching to cross the wiring.