JPS6137835B2 - - Google Patents

Description

[Detailed description of the invention]

[Technical Field of the Invention] The present invention relates to a color signal processing device used in a color television receiver or the like, which is capable of receiving television signals of different formats with a single device. [Technical Background of the Invention] There are three color television signal systems currently used in the world: NTSC, PAL, and SECAM. Each of these systems was uniquely adopted by each country or region, but with the advancement of color television broadcasting using space satellites and the spread of video tape recorders, the signals of these different systems were There is an increasing demand for so-called multi-system color television receivers that can receive images with a single color television receiver. Conventional multi-system color television receivers are
In order to reproduce and process the signals of each system, each television signal processing circuit suitable for each system is provided independently. For this reason, conventional multi-system color television receivers have problems such as an increase in price, an increase in power consumption, and a decrease in reliability in proportion to the increase in the number of component parts. In order to solve the above-mentioned problems, multi-system color television receivers have been developed that reduce the number of parts by increasing the number of circuits that can be used in common with each system when the signal systems are similar. . This multi-system color television receiver is
It can receive images in NTSC and PAL formats. Here, the unique parts of NTSC and PAL color television receivers are
The explanation will be given with reference to FIGS. FIG. 1 shows a color signal processing circuit of an NTSC color television receiver. 11 is a chroma signal input terminal, and 12 is a band amplification circuit. The band amplification circuit 12 includes an automatic gain control circuit (ACC) and a burst gate circuit.
This is a circuit that detects level fluctuations in the input signal and automatically controls the output so that it is always at a constant level.
The burst gate circuit is a circuit for separating a color signal component and a burst signal from an input signal. The chroma signal separated by the band amplification circuit 12 is
The signal is inputted to the color control circuit 14 via the transmission line 13, and is amplified according to the user's adjustment. The output chroma signal from the color control circuit 14 is sent to a (B-Y) demodulator 15 and a (R-Y) demodulator 17.
is input. On the other hand, the burst signal separated by the band amplification circuit 12 is input to the hue control circuit 19 via the transmission line 18. Hue control circuit 19
The receiver has a function of correcting hue errors caused by influence of the television signal on the transmission path on the receiver side, and adjustments for the correction are made by the user. The burst signal whose phase has been adjusted in the hue control circuit 19 is input to a color synchronization circuit 21 via a transmission line 20. The color synchronization circuit 21 includes a demodulation reference width carrier generator for generating subcarriers necessary for demodulating color signals, and a killer detector for identifying whether the broadcast is in color or black and white. The output of the killer detector is supplied to the color control circuit 14 or the demodulator, and the circuit function can be stopped so as not to generate color noise during monochrome broadcasting. The reference width carrier generator has an automatic phase control function that accurately follows the phase of the input burst signal, generates subcarriers for demodulation based on the phase of the burst signal, and transmits each subcarrier through transmission lines 22 and 23. (B-Y) demodulator 15,
(RY) is supplied to the demodulator 17. Figure 2 shows the color signal processing circuit of a PAL color television receiver. Components having the same functions as those of the circuit shown in FIG. 1 will be described with the same reference numerals. The chroma signal output from the color control circuit 14 is input to a 1H (one horizontal period) delay device 31, and is also inputted via an attenuator 32.
The signal is input to the PAL matrix circuit 33. The output of the 1H delay device 31 is also added to this PAL matrix circuit 33. In the PAL matrix circuit 33, matrix processing is performed on the 1H delayed signal and the undelayed signal of the chroma signal, and the chroma signal is separated into a (B-Y) component and a (R-Y) component. (B-Y) demodulator 15 and (R-Y) demodulator 17. By the way, in the PAL system, the demodulation axis of the (RY) component is inverted by 180 degrees every horizontal period and transmitted. This is a feature of the PAL system, and when the PAL matrix circuit 33 performs vector synthesis of the signal from one horizontal period before and the direct signal, the influence of subcarrier phase distortion on the demodulated signal is reduced.
Since the PAL method is not easily affected by phase distortion in the transmission path, a hue control circuit is not required, and the burst signal separated by the band amplifier circuit 12 is directly input to the color synchronization circuit 21 to generate a reference subcarrier. used for purposes. Color synchronization circuit 2
The subcarrier for (B-Y) demodulation obtained in step 1 is
(B-Y) Input to demodulator 15. Also, (R-
Y) The subcarrier for demodulation is input to the pulse switch circuit 34 which is driven by a horizontal retrace pulse and obtains an inversion operation every horizontal period, and the phase is adjusted. (R
-Y) Input to demodulator 17. Further, the inversion operation of the pulse switch circuit 34 is performed with respect to the transmission signal (R-Y) based on the ident detection output information (obtained from the ident detector of the color synchronization circuit).
The demodulation subcarrier is controlled to have the correct phase. In the pulse switch circuit 34, an internal flip-flop circuit output is inverted or non-inverted by a horizontal retrace pulse. In the above-mentioned color signal processing circuit dedicated to the NTSC system and the PAL system, a shared circuit that allows common functions to be shared by both systems is configured as shown in FIG. In FIG. 3, parts having the same functions as the circuits shown in FIGS. 1 and 2 will be described with the same reference numerals. In the case of this shared circuit, a switching circuit 35 and method selection means 36 are further provided, and the output of the switching circuit 35 selects the PAL matrix circuit 3.
3. The operation of the pulse switch circuit 34 and hue control circuit 19 can be switched. During PAL reception, the control operation of the hue control circuit 19 is stopped, and the burst signal separated by the band amplification circuit 12 is introduced into the color synchronization circuit 21 as it is. During NTSC reception, the chroma signal derived from the color control circuit 14 passes through a part of the PAL matrix circuit 33 without undergoing matrix processing (B
-Y) demodulator 15 and (RY) demodulator 17. Also, (R
-Y) The subcarrier for demodulation is also a pulse switch circuit 34.
(R-
Y) Input to demodulator 17. As mentioned above, according to the color signal processing circuit that can be used for both PAL and NTSC systems, depending on the received signal system,
The signal processing mode is switched. In the above explanation, regarding the chroma signal, the PAL matrix circuit 33
A switching circuit 35 determines whether or not to perform matrix processing.
Regarding the subcarrier, the pulse switch circuit 34 determines whether or not the (RY) demodulation axis is to be inverted by 180 degrees every horizontal period. That is, in the above system, PAL
The phase processing function in the color signal processing circuit is switched depending on the reception method and NTSC method. If we further focus on the signal differences between the PAL and NTSC systems, for example, they are shown in Table 1 below.

[Problems with background technology]

As described above, in a multi-system color television receiver, it is necessary to perform unique color signal processing depending on the transmitted color signal to be processed. For PAL color signals, a so-called identification operation is performed to detect whether the swing phase of the burst signal matches the reproduced color subcarrier. This identification operation is color signal processing specific to PAL color signals that is not present in NTSC color signals. Therefore, when considering the case of processing PAL color signals and NTSC color signals, it becomes difficult to share the above-mentioned ident circuit and color killer circuit. [Object of the Invention] The present invention has been made in view of the problems of the background art described above, and provides a color signal that can stably perform color killer operation, identification operation, etc. according to a plurality of transmitted color signals to be processed. The purpose is to provide processing equipment. [Summary of the Invention] In order to achieve the above object, the present invention applies a burst signal of a transmission color signal and a color killer detection axis signal to the color killer detection circuit shown at 83 in FIG. The resulting color killer detection signal is used as a color killer control signal, and is also used as a state control signal for a flip-flop circuit 86 that matches the phase of the reproduced color subcarrier with the phase of the burst swing. The ident and killer circuit 85 is
When processing a color signal without burst swing such as an NTSC signal, the oscillation operation of the flip-flop circuit 86 is stopped and the output potential of the flip-flop circuit 86 is set to a predetermined constant potential. With this configuration, the flip-flop circuit 86 has a phase inversion control function that inverts the color killer detection axis every horizontal period when receiving a PAL color signal, and a function that stops the inversion control when receiving an NTSC color signal. to hold. [Embodiments of the Invention] Examples of the invention will be described below with reference to the drawings. FIG. 5 shows the overall configuration of the color signal processing circuit section in the color television receiver of the present invention. 61 is an input terminal for a chroma signal including a burst signal, and the chroma signal input here is input to a variable gain amplifier 62. The chroma signal subjected to gain control in the variable gain amplifier 62 is input to a burst chroma signal separation circuit 63. The burst signal separated by the burst/chroma signal separation circuit 63 is input to a hue control circuit 81, and the chroma signal is input to a color control circuit 64. Further, the burst signal separated by the burst/chroma signal separation circuit 63 is input to an automatic color control (ACC) detection circuit 71, where the amplitude is detected.
A DC voltage obtained by amplitude detecting the burst signal is applied to the gain control terminal of the variable gain amplifier 62. Therefore, the variable gain amplifier 6
Burst chroma signal separation circuit 6 in which the chroma signal output from 2 is always controlled to a stable level.
At 3, the gate pulse from the gate pulse shaping circuit 72 is used to separate the burst signals. This gate pulse is phase-synchronized with the burst signal period, and is output after, for example, a horizontal synchronizing signal is delayed and adjusted to a constant pulse width. The chroma signal separated by the burst chroma signal separation circuit 63 is amplified by the color control circuit 64. The color control circuit 64 is
The gain is varied by adjusting the adjustment volume 65 by the user. The output chroma signal from the color control circuit 64 is sent to the pulse matrix circuit 75 via a 1H delay device 66 having a delay time of one horizontal period and a coupling capacitor 67.
The signal is applied to the delay input line 75a of the pulse matrix circuit 75, and is also applied to the direct input line 75b of the pulse matrix circuit 75 via an attenuator 68 and a coupling capacitor 69. The specific operation of the pulse matrix circuit 75 will be explained in detail in FIG. In this pulse matrix circuit 75, the system is PAL
When processing television signals of
Matrix processing is performed on a 1H delayed chroma signal delayed by 1H (one horizontal period) of the chroma signal and a direct chroma signal that is not delayed. Through this matrix processing, the (B-Y) component and the (R-Y) component are separated.
7 is input. On the other hand, when the system is processing an NTSC television signal, the operation switch 74 is turned on and the delay input line 7
The 1H daytime chroma signal on 5a is connected to ground. Therefore, only the direct chroma signal is input to the pulse matrix circuit 75. When the operation switch 74 is turned on, the pulse matrix circuit 75 switches its internal signal path, and as a result, the system switch circuit 7
The output state of 9 can also be switched. (The specific configuration of the system switch circuit 79 is also explained in detail in FIG. 6.) When the system is processing an NTSC television signal, the pulse matrix circuit 75 sends the direct chroma signal to two transmission paths. The signals are separated and input to a (B-Y) demodulator 76 and a (R-Y) demodulator 77, respectively. A gate pulse from a waveform shaping circuit 80 that outputs a pulse synchronized with the horizontal synchronizing signal period is also applied to the pulse matrix circuit 75. When this gate pulse is applied, the pulse matrix circuit 75 cuts off the chroma signal. The waveform shaping circuit 80 generates the gate pulse using, for example, a flyback pulse synchronized with a horizontal synchronizing signal. This gate pulse is applied to a flip-flop circuit 8 which will be described later.
6 is also used as a timing pulse to obtain phase inversion operation. The signal output from the pulse matrix circuit 75 is sent to a (B-Y) demodulator 76 and a (R-Y) demodulator 77.
Furthermore, demodulation processing is performed in a (GY) demodulator 78. This (B-Y) demodulator 76, (R-
The specific configuration and operation of the Y) demodulator 77 and the (G-Y) demodulator 78 will be described in detail in FIG. On the other hand, the burst signal whose phase has been adjusted in the hue control circuit 81 is input to a color killer detection circuit 83 (hereinafter referred to as a killer detection circuit) and an automatic phase control detection circuit 84 (hereinafter referred to as an APC detection circuit). Hue control circuit 81
To adjust the adjustment volume 82, the adjustment volume 82 is operated by the user. In the killer detection circuit 83, phase detection is performed between the burst signal and the subcarrier for killer detection, and a voltage corresponding to the phase difference is output as a killer detection voltage. In the APC detection circuit 84, phase detection is performed between the burst signal and the automatic phase control subcarrier, and a voltage corresponding to the phase difference is obtained as an oscillation frequency control voltage. The killer detection circuit 83 and the APC detection circuit 84 are
The detection operation is performed in synchronization with the burst signal, and its timing is determined by the gate pulse from the gate pulse shaping circuit 72. The color voltage from the killer detection circuit 83 is input to the ident and killer circuit 85. This ident and killer circuit 85 is shown in FIGS. 9 and 10.
It is detailed in the figure. The ident and killer circuit 85 controls on/off of chroma signal transmission of the color control circuit 64 and inversion/non-inversion of the flip-flop circuit 86 according to the level of the killer voltage. Furthermore, the ident and killer circuit 85 can also turn on and off the chroma signal transmission path of the pulse matrix circuit 75 by its output. Ident and killer circuit 85
It is possible to determine the color broadcast reception state and the black and white broadcast reception state according to the level of the killer voltage.Furthermore, when receiving a PAL television signal, the flip-flop circuit 86 is inverted,
It can be determined whether the non-inverting operation is in correct phase or out of phase. The inversion/non-inversion timing of the flip-flop circuit 86 is as follows:
It is determined by the gate pulse output from the waveform shaping circuit 80, and can be inverted or non-inverted every horizontal period. Furthermore, the flip-flop circuit 86 is set to an inactive state or an active state by a switching signal from the system switch circuit 79. When an NTSC television signal is being processed, the flip-flop circuit 8
The operation of the flip-flop circuit 86 is stopped, and when a PAL television signal is being processed, the operation of the flip-flop circuit 86 is started. The reference oscillation output from the voltage controlled oscillator 87 is introduced into the phase synthesizer 88, and the phase synthesizer 88 outputs, for example, four subcarriers depending on the purpose of use. This phase synthesizer 88
is (B-Y) for adding to the (B-Y) demodulator 76.
Y) subcarrier for demodulation, (RY) subcarrier for demodulation to be added to the demodulator 77, (G-
Y) a correction subcarrier to be added to the demodulator 78;
A killer detection subcarrier to be added to the killer detection circuit 83 is generated. The correction subcarrier is
It is utilized in the (GY) demodulator 78 when an NTSC television signal is being processed. The operation mode of the phase synthesizer 88 is switched by the output of the system switch circuit 79, and the phase state of the (R-Y) demodulation subcarrier is switched between PAL system reception and NTSC system reception. When receiving a PAL signal, the phase of the (R-Y) demodulating carrier wave is inverted every horizontal period by the output of the flip-flop circuit 86. The specific configuration and operation of the phase synthesizer 88 will be described in detail in FIG.
Two reference oscillation outputs with different vector phases are input, and are used to generate various subcarriers. The voltage controlled oscillator 87 has an oscillation frequency controlled by the detection output from the APC detection circuit 84, and is controlled so as to always obtain an oscillation output phase-synchronized with the burst signal. Next, details of each circuit will be explained. (1) [Description of the pulse matrix circuit 75] FIG. 6 specifically shows an example of the configuration of the pulse matrix circuit 75, the system switch circuit 79, and the operation switch 74. The pulse matrix circuit 75 functions as a matrix circuit that performs vector addition and subtraction of the direct chroma signal and the delay chroma signal when receiving the PAL system, and functions as a separate transmission path for the direct chroma signal when receiving the NTSC system. It is assumed that the operation switch 74 is turned off when receiving the PAL system, and turned on when receiving the NTSC system. A negative horizontal blanking pulse (gate pulse) is applied from the waveform shaping circuit 80 to the base of the transistor Q839. This horizontal blanking pulse causes transistor Q8 to
39 is turned off, but its collector potential increases and the transistor Q8 involved in chroma signal transmission
10, Q813, Q814, and Q817 are turned off and have the function of blocking input signals during the horizontal blanking period (meaning removing burst signals). Furthermore, even if the transistor Q839 is on during the chroma signal period, if the transistor Q840 is turned on by the color killer signal, the pulse matrix circuit 75 immediately cuts off the transmission path of the chroma signal. The matrix circuit 75 functions as a pulse matrix when receiving PAL, and functions as a color amplifier when receiving NTSC. (1)-1 [Operation when receiving PAL method] When receiving PAL method, the operation switch 74
is turned off, thereby causing transistor Q
817 and Q818 are turned on. As a result, the collector potential of transistor Q818 of the operational amplifier formed by Q817 and Q814 drops at this time. A voltage further lower than the collector potential of transistor Q818 by V _F (transistor base-emitter forward potential drop) appears at the emitter of transistor Q842, and this voltage
Added to the base of 89, Q882, and Q821. By this, transistor Q88
9, Q822, and Q821 are turned off. (Transistors Q822 and Q821 are transistors that function to transmit the (RY) and (B-Y) chroma signals when receiving the NTSC method, but are turned off when receiving the PAL method.) (1)-2 [Vector addition in pulse matrix] The direct chroma signal added to the base of transistor Q810 is
It passes through the collector of Q810 → resistor R875 → transistor Q820 and is led to resistor R823. In this case, the phase of the direct chroma signal is inverted by transistor Q820. Also, the direct chroma signal applied to the base of transistor Q810 is transferred from the emitter of transistor Q810 to resistor R816 to R817.
→ Transistor Q813 → Resistor 876 → Transistor Q823 → Resistor R882 → Also led to R826. The direct chroma signal in this path is not phase inverted. The delay chroma signal applied to the base of transistor Q817
It is led to the collector of this transistor Q824 via the emitter → resistor R819 → R818 → transistor Q814 → R877 → transistor Q824, and the emitter of transistor Q817 → resistor R819 → R818 → transistor
Q814 → Resistor R878 → Transistor Q825 → Resistor
Directed via route R823. This connects the collector of transistor Q824 to the resistor.
At the connection point R823, the direct chroma signal and the inverted delay chroma signal are added. That is, vector subtraction is performed between the direct chroma signal and the delayed chroma signal. Also, with resistor R826,
Vector addition of the direct chroma signal and the delayed chroma signal is performed at the connection point with the resistor R883 connected to the collector of the transistor Q825. The result of vector addition (B-
Y) component is added to the base of transistor Q827 and the result of vector subtraction (R-Y)
The component is applied to the base of transistor Q826. (1)-3 [Operation when receiving the NTSC method] When receiving the NTSC method, the pulse matrix circuit 75 performs amplification and distribution processing of the direct chroma signal. Operation switch 74
is turned on at this time. Therefore, the transistors constituting the system switch circuit 79
The base potential of Q818 and Q817 becomes low, and transistors Q818, Q883, and Q817 are turned off.
Therefore, transistors Q818, Q883, Q884, which constitute the system switch circuit 79,
Of the transistors in Q819, the transistor
The collector potential of Q818 becomes high, while the collector potential of transistor Q819 becomes low. As the collector potential of transistor Q818 becomes higher, the emitter potential of transistor Q842 also becomes higher, and this emitter potential is applied to the bases of transistors Q889, Q822, and Q821. This allows the transistor
Q889, Q822, and Q821 transition from the off state to the on state. On the other hand, since the collector potential of transistor 819 has become low, the emitter potential of transistor Q841 has also become low, and this emitter potential has become the same as that of transistors Q823 and
Base of Q824, Q825 and transistor Q820
is applied to the bases of the transistors, turning them off. As a result, during NTSC reception, transistors Q825 and Q824 forming the transmission path for the day chroma signal are turned off, and the day chroma signal is immediately cut off.
Therefore, during NTSC reception, the signal is applied to the base of transistor Q826 via the path from the base and collector of transistor Q810 → resistor R875 → transistor Q821 → resistor R880, and also from the base to emitter of transistor Q810 →
Resistor R816 → Resistor R817 → Transistor Q813 →
It is applied to the base of transistor Q827 via the path of resistor R876 → transistor Q822 → resistor R881. The signal applied to the base of transistor Q827 is transferred from the emitter of transistor Q827 → capacitor C802 for DC cut → transistor Q832
The next stage (B
-Y) input to demodulator 76; Also, the signal applied to the base of transistor Q826 is
Emitter of transistor Q826 → capacitor C801 for DC cut → base-emitter of transistor Q831 to the next stage (R-Y)
The signal is input to a demodulator 77. (1)-4 [Gain in the pulse matrix circuit] The gain of the pulse matrix circuit 75 is automatically switched between when receiving the PAL system and when receiving the NTSC system. That is, during PAL reception, vector addition of the direct chroma signal and the delayed chroma signal is performed on the collector side of transistor Q825, and vector subtraction is performed on the collector side of transistor Q824. Vector addition is (B-Y)
When extracting the components, the resistor R825 acts as a load for the transistor Q823 that amplifies the direct chroma signal, and the resistor (R825+R826) acts as a load for the transistor Q825 that amplifies the delayed chroma signal. On the other hand, regarding vector subtraction, vector subtraction extracts the (R-Y) component, and resistor R822 acts as a load for transistor Q820, which inverts the direct chroma signal, and transistor Q822, which amplifies the delayed chroma signal, For, resistor (R822+
R823) becomes the load. Next, when receiving the NTSC method, the load on transistor Q822 becomes resistor (R825 + R826). The load on transistor Q821 is a resistor (R822 + R823 + R829). As described above, the loads for the (B-Y) and (R-Y) components in the pulse matrix circuit can be switched in accordance with the reception of the PAL system and the NTSC system. By switching this load, the relative amplitude ratio (B-Y)/(R-Y) of the components of the B-Y axis and the R-Y axis
can be set to 1 when receiving PAL format and 0.56 when receiving NTSC format. In other words,
An amplitude ratio suitable for each method can be automatically switched and obtained. However, the output DC potential does not change in response to system switching. (1)-5 [Pal matrix operation] In the pulse matrix circuit 75,
It operates to automatically switch the amplitude ratio of (B-Y)/(R-Y) during PAL system processing and NTSC system processing. Now, the current vectors of the direct chroma signal and the dire chroma signal will be explained as α and β. However, in FIG. 6, the collector current of Q813 is α, the collector current of Q810 is −α, and the collector current of Q814 is β (the collector currents of Q825 and Q824 are both β/2). FIG. 11a shows the vector of the direct chroma signal when receiving the PAL system, and FIG. 11b shows the vector of the daytime chroma signal.
The (B-Y) component can be derived as 2(B-Y) as shown in Figure 11c, and the amplitude is α(R825)+β/2(R825+R826).
It can be expressed as However, R825,
R826 is the resistor R825 in Figure 6, respectively.
This is the value of R826. Next, the (R-Y) component is derived by inverting the phase every horizontal period, and as shown in FIG. 11d, -2(R-
Y) or 2(RY). At this time, the amplitude is β/2 (R822 + R823) − α
(R822). However, R822 and R823 are the values of the resistors R822 and R823 in FIG. 6, respectively. When the system is then switched to NTSC processing, only the direct chroma signal shown in FIG. 12a is processed. The chroma signal applied to the (B-Y) demodulator consists of 2 (R-Y) components and 2 (B-Y) components, as shown in Figure 12b.
It is derived as a composite vector of components, and the amplitude in this case can be expressed as α(R825+R826). However, R825 and R826 are
These are the values of resistors R825 and R826 in FIG. Also, the chroma signal applied to the (RY) demodulator is 3.56 (B-
Y) component and 3.56(R-Y) component, and the amplitude in this case is -α
It can be expressed as (R822+R823+R829). However, R822, R823, and R829 are the 6th
These are the values of resistors R822, R823, and R829 in the figure. (1)-6 [Modification of the pulse matrix circuit 75] Figures 13a and 13b show other embodiments of the pulse matrix circuit. To explain from the circuit of FIG. 13a, 91 is a reference ground potential line, 92 is a constant current bias line, 93 is a base bias line, 75
b is the direct chroma signal input line, 75
a is a day chroma signal input line.
Furthermore, 94 is a switching signal input line from the system switch circuit, and 95 is supplied with a reference voltage. When receiving the NTSC system, the switching signal input line 94 becomes low level. Therefore, transistors Q31, Q35, Q36, and Q34 are turned off. Therefore, the direct chroma signal passes through the path from the base collector of transistor Q11 to the emitter collector of transistor Q32,
(RY) component output line 96.
It is also led to the (BY) component output line 97 through the base-emitter of the transistor Q11 -> the resistors R11 and R12, and the emitter-collector of the transistor Q12 -> the emitter-collector of the transistor Q33. Next, when receiving the PAL system, the switching signal input line 94 becomes high level. For this reason,
Transistors Q35, Q36, Q34, and Q31 are turned on, and transistors Q32 and Q33 are turned off. Therefore, the direct chroma signal is led out to the (RY) component output line 96 via transistor Q11 → transistor Q31 → resistor R32, and also from transistor Q11 → resistor R11.
→R12→Transistor Q12→Transistor
Q34 → is led out to the (B-Y) component output line via resistor R34. On the other hand, the delay chroma signal is transmitted from transistor Q21 to resistor R21 to R22.
→After passing through transistor Q22, it is distributed to the transistor Q36 side and Q35 side, and the (RY) component output line 96 and (B-Y)
It is led to the component output line 97 side. This makes it possible to obtain matrix processing during PAL processing. The signal applied to transistor Q21 is F _(p
)o and the signal applied to transistor Q11 is F′ _(p)o+1 , then the signal appearing on the output line 97 is F′ _(p)o +F′ _(p)o+1 = {α′(B −Y)±jβ′(R−Y)} +{α′(B−Y)〓jβ′(R−Y)} =2α′(B−Y) Similarly, the signal appearing on the output line 96 is F′ _{( p)o} −F′ _(p)o+1 = ±j2β(R−Y). Next, the pulse matrix circuit shown in FIG. 13b will be explained. In Figure 13b, the first
The same parts as in Figure 3a will be explained using the same reference numerals.In the case of this circuit, the constant current source _I1 of the transistors Q41 and Q42, which can receive and amplify the day chroma signal, is an NTSC system,
It is configured to turn off or on depending on PAL processing. During NTSC processing, constant current source _I1 is turned off, so only the direct chroma signal is processed.
It is led out to the collector side of transistor Q43 and the collector side of transistor Q44. During PAL processing, by turning on the constant current source _I1 , the day chroma signal is transferred to the transistor
After passing through the path Q41→Q42, it is distributed by transistors Q45 and Q46, enabling matrix processing. (2) [(B-Y), (R-Y), (G-Y) demodulator and phase synthesizer] Figure 7 shows (B-Y), (R-Y), (G-Y) demodulation. FIG. 8 shows a phase synthesizer 88. (2)-1 [(B-Y), (R-Y), (G-Y) demodulator] (When receiving PAL system) The (B-Y) component derived from the emitter of transistor Q832 is
Supplied to the bases of Q855 and Q861, and derived from the emitter of transistor Q831 (R
-Y) component is supplied to the base of transistor Q856. (B-Y) In the demodulator 76, transistors Q854, Q855, Q862,
Q863, Q864, and Q865 constitute a multiplication circuit, and the (B-Y) demodulation subcarrier (B-Y) CW from the phase synthesizer 88 is added to the common base of the transistors Q864 and Q863.
The demodulated signal (B-Y) of the (B-Y) component is derived through a path from the base-emitter of transistor Q874 to resistor R866 via the common collector of transistors Q862 and Q864.
Further, a demodulated signal (B-Y) of opposite polarity is led out from the common collector of transistors Q863 and Q865 to a matrix resistor R868. On the other hand, in the (RY) demodulator 78, transistors Q856, Q857, Q866, Q867, Q868,
Q869 also constitutes a multiplication circuit, and the (RY) demodulation subcarrier (RY) CW from the phase synthesizer 88 is added to the common base of transistors Q867 and Q868. (RY)
The demodulated signal (R-Y) of the component is transmitted through the transistor
Common collector of Q867, Q869 → transistor
It is derived through the path from the base emitter of Q875 to resistor R870. Also, the demodulated signal -(RY) of opposite polarity is transmitted by transistors Q866 and Q868.
is derived from the common collector of resistor R871. Therefore, the demodulated signal (B-Y) and -(R-
The demodulated signal (G-Y) obtained as a result of the matrix of
It is derived through the path of emitter → resistor 872. That is, the demodulated signal (G-Y) is obtained by vector synthesis of the demodulated signal -(B-Y) and the demodulated signal -(RY). (2)-2 [(B-Y). (RY). (G-Y) Demodulator] (When receiving the NTSC method) The operation of the (B-Y) demodulator 76 and (R-Y) demodulator 77 when receiving the NTSC method is PAL.
It is the same as when receiving the method. however,
When receiving the NTSC system, the transistor is switched on by the operation of the system switch circuit 79.
The collector potential of Q844 decreases and the collector potential of transistor Q843 increases. When the collector potential of transistor Q844 decreases,
(GY) Transistors Q859 and Q860 forming the demodulator 78 are turned off. As a result, transistors Q861 and Q858 are turned on, and the chroma signal from matrix circuit 75 is transferred to transistors Q861 and Q858.
Derived to the collector via the base of Q861. At this time, transistors Q858, Q861,
Q870, Q871, Q872, and Q873 function as a multiplier circuit, and the common collector of transistors Q873 and Q871 is connected to the (G-Y) subcarrier for demodulation (G-Y) CW (actually, the vector phase of the G-Y axis). For correction) and the (B-Y) component, a multiplication output, that is, a demodulated signal for correction (G2-Y) is obtained. Therefore, when receiving the NTSC method,
Demodulated signal (B-Y), -(R-Y), (G2-Y)
A matrix calculation is performed on the three signals, and the resulting signal is a regular demodulated signal (G-
Y). (3) [Description of phase synthesizer 88 and demodulation axis] FIG. 8 shows the phase synthesizer 88. This phase synthesizer 88 and the (B-Y), (RY), (G
-Y) The relationship between the demodulation axes of the demodulators 76, 77, and 78 will be explained with reference to FIGS. 7 and 8. (3)-1 [Demodulation axis during PAL reception] The subcarrier required for color demodulation is generated by a phase synthesizer using a reference oscillation signal created using a burst signal as a reference by an automatic phase control (APC) loop. 88. (B-Y) subcarrier for demodulation (B-Y) for the (B-Y) axis
CW is created using the second reference oscillation signal b applied to the base of transistor Q734 forming phase synthesizer 88. This second reference oscillation signal b is a signal created by delaying the first reference oscillation signal a,
The first reference oscillation signal a is a signal generated in an APC loop including the voltage controlled oscillator 87 in phase synchronization with the burst signal. When the second reference oscillation signal b is applied to the base of the transistor Q734, a signal b having the same phase appears at the collector of the transistor Q735. This signal b is transmitted to the (B-Y) demodulation subcarrier (B-Y) via the transistor Q737.
derived from its collector as CW, the seventh
It is added to the common base of transistors Q863 and Q864 shown in the figure. Next, the subcarrier (RY) of the (RY) axis
Regarding CW, this (RY) demodulation subcarrier (RY) CW is generated by the first phase synthesis circuit 88a. The first phase synthesis circuit 88a includes transistors Q742,
Consists of Q743, Q744, Q745, Q746, Q747, etc. A first reference oscillation signal a is applied to the base of the transistor Q742, and a second reference oscillation signal b is applied to the base of the transistor Q743. Transistor Q742,
Q743 has a differential amplifier circuit configuration, and its emitters are commonly connected and connected to the collector of transistor Q740, which constitutes a constant current source.
Therefore, the collector of transistor Q742 has −(a-b)=(ba-a), and the transistor
Signals (a-b) appear at the collector of Q743. Then, the signal (b-a) is connected to the collector side of the transistor Q745, and the signal (a)
-b) can be derived on the collector side of transistor Q747 with resistor R729 as a load. Here, which signal (ba) or signal (a-b) is derived depends on the output from the flip-flop circuit 86 (P4, P5) Determined by condition. That is,
Of the outputs P4 and P5 of the flip-flop circuit 86, when the output P4 is at a high level, -(a-b) is output through the transistor Q745.
= (b-a) is derived to resistor R729, output P4
is at a low level, transistor Q747
(a-b) is led out to resistor R729 via. As explained in FIG. 5, the state of the flip-flop circuit 46 is inverted every horizontal period, so when receiving the PAL system,
Signals (ba-a) and (a-b) are output alternately every horizontal period. In other words, the phase of the RY demodulation subcarrier (RY) CW is inverted every horizontal period, and the (RY) component is demodulated. The (RY) demodulation subcarrier (RY) CW is added to the bases of transistors Q867 and Q868 shown in FIG.
When receiving the PAL method, the subcarrier is 90
This is done with a phase difference of °. During PAL reception, the base potential of transistor Q818 in system switch circuit 79 shown in FIG. 6 is high and the collector potential is low. The emitter potential of transistor Q842 also becomes low, so the collector potential of transistor Q844 becomes high and the collector potential of transistor Q843 becomes low. The collector potential of transistor Q843 of system switch circuit 79 is also applied to the bases of transistors Q751 and Q755 in phase synthesizer 88. Therefore, during PAL reception, the base potentials of the transistors Q751 and Q755 in the phase synthesizer 88 are low, and the transistors Q751 and Q755 are turned off. Therefore, when transistor Q755 is off, its collector
Since it is disconnected from R729, the signal (a-b),
Only (ba) is derived as a subcarrier. Next, the (G-Y) axis during PAL reception will be explained. When receiving the PAL system, the system switch circuit 7 shown in Figure 6
Transistors Q818, Q819,
Depending on the states of Q841, Q842, Q843, and Q844, transistors Q861 and Q858 of the (GY) demodulator shown in FIG. 7 are turned off.
Therefore, the chroma signal (B-Y) component obtained through the emitter of transistor Q832 is
It has been discontinued in Q861. As a result, (G-
In the Y) demodulator, the (G-Y) demodulation subcarrier (G-Y) CW and the (B-Y) component are not multiplied. However, in this case, a predetermined DC voltage appears at the collector of transistor Q873. When receiving the PAL method, as explained in Figure 4b, -(B
A (G-Y) demodulated signal is obtained by a matrix of the -Y) demodulated signal and the -(R-Y) demodulated signal. (3)-2 [Demodulation axis when receiving the NTSC method] When receiving the NTSC method, the pulse matrix circuit 7 used when receiving the PAL method
5 is shared, and serves as a chroma signal transmission path as well as a separation path.
During NTSC reception, the operation of the flip-flop circuit 86 is stopped by the system switch circuit 79. During NTSC system reception, the demodulation phase of the demodulation axis is different from that during PAL system reception, and the relative phase difference between the (B-Y) axis and the (R-Y) axis is set to about 105 degrees. The relative amplitude ratio of demodulated signals also differs between the NTSC system and the PAL system.
This is because the white color temperature settings are different between the PAL system and the NTSC system. This system is switched to satisfy such conditions. During NTSC reception, the state of each transistor constituting the system switch circuit 79 is reversed from the state during PAL reception. Therefore, in the phase synthesizer 88, transistors Q741, Q751, and Q755 are turned on, and transistor Q760 is turned off. When transistor Q741 turns on, the transistor
Q742 and Q743 are turned off. Then, when transistor Q751 turns on, transistor
Q752 and Q753 are turned off. Subcarrier for B-Y demodulation (B-Y) during NTSC reception
CW is extracted in the same way as when receiving the PAL system. On the other hand, transistors Q749, Q750, Q751,
Q752, Q753, Q755, etc. form a second phase synthesis circuit 88b. transistor Q750
Since _the resistor R733 is connected to the base _of
1) Its absolute value is varied and the transistor
Applied to the base of Q750. In addition, since the resistor R731 is also connected to the base of the transistor Q749, the absolute value of the reference oscillation signal b is varied to k ₂ · b, and the reference oscillation signal b is
added to the base of. As a result, the emitter of transistor Q755 has a Vekult signal.
k ₂・b−k ₁・a will appear. When receiving the NTSC system, the operation of the flip-flop circuit 86 is stopped and the output
Since P4 and P5 are at low level, transistors Q756, Q752, Q746, Q745,
Q754, Q753, Q747, and Q744 are off. Therefore, on the collector side of the transistor Q755, there is a signal (k ₂・b−k ₁・
a) is (RY) subcarrier for demodulation (RY)
Derived as CW. Since the phase adjustment is based on vector composition, the resistor
This is done by selecting the values of R732 and R731. It was extracted like this (R-
Y) Demodulation subcarrier (RY) CW is the 7th
It is added to the common base of transistors Q867 and Q868 shown in the figure. In this way, (R-
The subcarrier (R-Y) CW of the Y) axis is (B-
(Y) axis with a phase difference of 105°. Furthermore, in the (RY) demodulator 77, the (RY) component is inputted after the amplitude of the (B-Y) component is adjusted in the pulse matrix circuit 75, so that Demodulation is performed. Next, the (G-Y) axis during NTSC reception will be explained. Even when receiving data using the NTSC method, the (G-Y) axis must have the same phase as when receiving data using the PAL method. However, the system
When switching from PAL processing state to NTSC processing state, the pulse matrix circuit 7
5, the gain for the (RY) component is larger during NTSC processing than during PAL processing. Therefore, if the (G-Y) demodulator 78 simply performs matrixing as in the PAL system processing, the demodulated signal (B-
Since the vector distribution of Y) and (RY) is different from that during PAL processing, the (G-Y) axis cannot be obtained at the desired phase. Therefore, when receiving the NTSC system, the (G-Y) of the (G-Y) signal
It is necessary to correct the axis phase. The (G-Y) axis correction means during NTSC reception will be explained. The (G-Y) demodulated signal is (B-Y) when receiving the PAL method.
The demodulated signal and the (R-Y) demodulated signal were demodulated by performing matrix processing, but when receiving the NTSC system, the (B-Y) demodulated signal, (R-Y)
In addition to the demodulated signal, the (B-Y) component is
Y) Demodulation processing is performed using the detection output of the subcarrier for demodulation (G-Y) CW. That is, in the phase synthesizer 88, the transistor
Q764, Q765, Q767, Q768, Q769, etc. constitute the third phase synthesis circuit 88c. Since the resistor R737 is connected to the base of the transistor Q764, the reference oscillation signal a is
It is attenuated to l ₁ ·a (0<l ₁ <1) and is applied to the base of transistor Q764. Also,
The base of the transistor Q765 is a low anti-resistance R739
is connected, the reference oscillation signal b is
It is attenuated to l ₂ ·b (0<l ₂ <1) and is applied to the base of transistor Q765. Therefore, the collector of transistor Q764 has
A vector signal of (l ₂・b−l ₁・a) is obtained, and this signal is used as a (G−Y) demodulation subcarrier (G−Y) to generate a correction vector.
As CW, it is added to the common base of transistors Q872 and Q871 of the (GY) demodulator 78. As a result, in the (G-Y) demodulator 78, the chroma signal applied to the base of the transistor Q861 is multiplied by the (G-Y) demodulation subcarrier (G-Y) CW,
The vector signal obtained as a result becomes one of the matrix elements as a correction vector signal. Through this operation, when receiving the NTSC system, it is possible to have the correct demodulation axis (G-Y).
A demodulated signal is obtained. That is, it is adapted for PAL processing.
Since the correct (G-Y) axis cannot be obtained in the matrix circuit, a subcarrier (G-Y) CW for correction is generated in the phase synthesis circuit 88c, and as shown in FIG. Y)
A correction vector (G-Y) UD is created so that the axis is at the position of the solid line. As a result, a correct (G-Y) axis demodulated output can be obtained. (3)-3 [Stabilization of phase synthesis in the second phase synthesis circuit 88b and third phase synthesis circuit 88c] In the phase synthesis circuit, the reference oscillation signal a,
Although phase synthesis of phase b is performed, it is necessary to ensure that the synthesized output is not affected by the current amplification factor h _fe of the transistor. We will now explain the measures taken for the phase synthesis circuit made up of transistors Q749 and Q750. Now, in this phase synthesis circuit, the resistance
If R733 were not present, the following problems would arise. FIG. 15a shows a simplified phase synthesis circuit in which the resistor R731 is removed, but with this configuration, the phase synthesis output is unstable. In Figure 15a, the reference signal a is the base emitter of transistor Q1→
Transistor Q750 through the path of resistor R732
The reference signal b is input to the base of transistor Q749 via the base emitter of transistor Q2. The value of resistor R732 is 1kΩ, the value of resistor R733 is 5k
Let it be Ω. Figure 15b shows an equivalent circuit as seen from reference signal a, and Figure 15c shows reference signal b.
This is an equivalent circuit when viewed from above. However, in the figure, h _ie1 and h _ie2 indicate the base input impedance of Q749 and Q750, respectively, and r _e indicates the emitter resistance. Using this circuit, the transistor
Let's find the base input voltage of Q749 and Q750. h _ie1 = h _ie2 = KT/q×2(h _fe +1)/ _ip K...Boltzmann multiplier (1.38×10 ^-23J/K ) q...Electron charge (1.6×10 _- ¹⁹ coulombs) T... ...Absolute temperature KT/q...26mV (approximate at room temperature) io...Transistor emitter current r _e =KT/q×1/i _p =0.045K Base input v _io (a) of transistor Q750 is The base input v _io (b) of the transistor Q749 becomes v _io (b)=b. When h _fe is changed to 50, 100, and 300, the input vectors are 0.733a, 0.792a, and 0.792a, respectively.
0.818a, b, and the output color subcarrier composite vector c is amplified by resistor-divided k ₁ , a and b, and its phase error ΔQ changes by about 7°. That is, the combined vectors c ₁ , c ₂ , and c ₃ shown in FIG. 15d are influenced by the current amplification factor h _fe . When the subcarrier fluctuates in this way, accurate color demodulation cannot be obtained. Furthermore, when the phase synthesis output is used in a killer detection circuit, a malfunction may occur in the color killer operation. In order to prevent the above-mentioned phase fluctuation, in the system of the present invention, a resistor R731 is further provided as shown in _FIG . to obtain stable phase synthesis output. That is, the simplified circuit configuration in this case is shown in FIG. 16a, and the equivalent circuit is as follows.
The result is as shown in FIGS. 26b and 26c. From this circuit, the base input voltages of transistors Q749 and Q750 are determined as follows. Resistor R732 = 1kΩ, resistor R733 = 5kΩ, resistor R731 = 800Ω. The base input h _io (a) of transistor Q750 is The base input υ _io (b) of transistor Q749 is becomes. When h _fe changes to 50, 100, and 300, the input vectors are (0.744a, 0.896b), respectively.
(0.794a, 0.935b) (0.818a.0.981b), and the output phase composite vector c is differentially amplified by k ₁・a and k ₂・b, which are resistance-divided at the input, and the phase error is approximately Within 1°. That is, as shown in FIG. 16d, the low phase composite vector c has a stable phase almost unaffected by the current amplification factor h _fe . Therefore, it can be used for accurate color demodulation and phase detection operations. (4) [Color Killer Detection and Color Killer Operation] Since the Color Killer detector is shared for PAL signal and NTSC signal processing, the Color Killer detection axis is the NTSC signal when processing either system signal. (R-Y) during color demodulation
The phases of demodulation subcarriers are made substantially equal. The color killer detection circuit 83 required to control the color killer operation detects PAL signals and
Commonly used for NTSC signals, and the phase of the color killer detection axis for PAL signals is obtained by phase synthesis circuits 88 and 88b during NTSC signal processing (R-Y)
The phase shall be substantially equal to that of the demodulation subcarrier. That is, the color killer detection axis signal for the PAL signal is obtained using the phase synthesis circuit 88b that generates the (RY) demodulation subcarrier of the NTSC signal. Therefore, when performing color killer processing on a PAL signal, there is no need for a separate circuit for generating a phase signal of the color killer detection axis. The ident and killer circuit 85 also includes a killer filter 90 that holds the detected output voltage of the color killer detection circuit 83 at predetermined intervals.
It functions as a switching circuit that performs switching operations in response to the voltage. The switching function of the ident and killer circuit 85 allows color killer operation to be performed on both NTSC and PAL signals, and also controls the burst swing timing of the transmission burst signal and the (R-Y) demodulation subcarrier during PAL signal processing. An identification operation is performed to determine whether the phase inversion timings match. That is, the switching function of the ident and killer circuit 85 performs the ident operation. The above IDENT operation controls the output phase of the flip-flop circuit 86 during PAL signal processing to match the phase of the (RY) demodulation subcarrier with the burst swing phase, but the flip-flop circuit 86 is used for NTSC signal processing. The above ident circuit and killer circuit 85
The oscillation operation is stopped by the control of For this reason,
The phase inversion control operation of the (R-Y) demodulation subcarrier used as the color killer detection axis in PAL signal processing is stopped during NTSC signal processing, and the (R-Y) demodulation operation of the NTSC signal is performed when receiving the NTSC signal. . FIG. 9 shows the killer detection circuit 83 and the ident and killer circuit 85. Killer detection circuit 83
is the burst and killer detection subcarrier separated by the burst chroma separation circuit 63.
CW), and as a result, a killer detection output voltage Vo is derived to the killer filter 90. The above-mentioned ident and killer circuit 85 is composed of two comparators, a killer comparator and an ident comparator, and each compares the killer detection output voltage with predetermined reference voltages V _H and V _L , and as a result, various circuits operate. stipulates. Here, the reference voltage V _L is the base voltage of the transistor Q664 of the ident and killer circuit 85,
V _H indicates the base voltage of transistor Q662. In the embodiment of the present invention, the color reception mode is set when V _O >V _H , the killer operation mode is set when V _O <V _H , and the ident operation mode is set when V _O <V _L. Note that the Ident operation mode is valid only in the PAL reception mode, and the Ident operation is not performed in the NTSC reception mode. The circuit operation will be explained below for each case. (4)-1 [Color killer operation when receiving NTSC signal] When the system switch 74 shown in FIG. 6 is connected to the NTSC side, the system enters the NTSC reception mode. At this time, the collector voltage of transistor Q843 of system switch circuit 79 is high, and the collector voltage of transistor Q844 is low. Therefore, in FIG. 8, the transistor Q755 in the phase synthesizer 88 is turned on and the transistor Q755 is turned on.
Q756 and Q754 are turned off, and at the same time transistor Q760 is turned off and the transistor
Q758 and Q759 are turned on. As a result, transistors Q758 and Q759 are connected to the voltage controlled oscillator 87.
It operates as a differential amplifier that receives the output signal b of the transistor Q762, and generates a vector component of the signal b at the collector of the transistor Q762. This is the transistor Q633 of the killer detection circuit 83 as the color killer detection subcarrier (Killer-CW).
Supplied on the common base of Q634. Assuming that we are currently receiving NTSC color broadcasting, a burst signal is added to the base of transistor Q630, and as a result of multiplication with the color killer detection subcarrier (Killer-CW) described above, killer filter 90 is activated. The voltage (killer detection voltage) V _O increases. This killer detection voltage V _O is the identity and killer circuit 8
5 is applied to the base of transistor Q663. Furthermore, the aforementioned reference voltage V _H is applied to the base of the transistor Q662.
Therefore, the killer detection voltage V _O increases, and V _O >V
When it becomes _H , transistor Q659 turns on, Q658
turns off and the current in Q655 decreases. In this way, during NTSC processing, when a burst signal is detected at a normal electric field strength,
Transistor Q665 is turned off, which turns off transistor Q840, which controls the pulse matrix circuit 75 described in FIG. transistor
When Q840 is off, the pulse matrix circuit 75 acts as a transmission path and distribution path for gain-controlled NTSC chroma signals.
A predetermined color demodulation operation is performed in the color demodulation circuit. On the other hand, when a black and white broadcast is received or in a weak electric field, the transistor of the killer detection circuit 83
No burst signal appears on the base of Q630. Therefore, the voltage V _O of the killer filter 90 is
Regardless of the output voltage of the killer detection circuit 83, it becomes a constant value determined by the base voltage of the transistor Q652. This voltage is lower than the base voltage (V _H ) of transistor Q662, and transistor Q665 of ident and killer circuit 85 is turned on. As a result, the pulse matrix circuit 7
Transistor Q840, which controls 5, turns on. When this transistor Q840 turns on,
Regardless of when processing NTSC or PAL format,
Transistors Q810, Q813, Q814 in Figure 6,
All Q817s are turned off, the chroma signal transmission path is cut off, and color killer operation is performed. In this way, the pulse matrix circuit 75 which functions as an amplifier for the NTSC color signal by the collector output of the transistor Q665.
In addition, the collector output of the transistor Q665 is also supplied to a switch circuit (not shown) that turns on and off the output of the bandpass filter in the color control circuit 64. The output of the filter itself is also cut off, making it possible to perform a double color killer operation. FIG. 10 shows a flip-flop circuit 86. During NTSC reception, the collector potential of transistor Q843 of system switch circuit 79 is high, and therefore transistors Q845, Q846, Q847, and
Q667 is on. Therefore, the switch composed of transistors Q668 and Q669 is
When receiving the NTSC system, it is turned off and the transistor
Q670 is off. When transistor Q670 is turned off, flip-flop circuit 86 is not supplied with energizing voltage and stops operating. Therefore, the outputs P4 and P5 of the flip-flop circuit 86 are both at low level during NTSC processing, and (R-Y)
Phase synthesis circuit 88 that synthesizes subcarriers for demodulation
The phase reversal control operation at b is stopped, and (R-
Y) Color demodulation is appropriately performed in a color demodulation circuit. (4)-2 [Color killer operation and ident operation when receiving PAL system signal] In PAL system, burst signal is -
(B-Y axis), the phase is swung by ±45° every horizontal period, and the subcarrier for color killer detection (Killer-
CW) needs to be synchronized. For this reason
A flip-flop circuit 86, which is not necessary for receiving NTSC signals, and an identification circuit are provided. When the system switch 74 shown in FIG. 6 is installed on the PAL side, the system enters the PAL reception mode.
At this time, the collector potential of transistor Q843 of the system switch circuit 79 becomes low,
The transistors Q845, Q846, Q847, and Q667 of the flip-flop circuit 86 in FIG. 10 are turned off, and the transistors forming the switch are turned off.
Q668 and Q669 are turned on. Therefore, transistor Q670 turns on and
An energizing voltage is applied to this flip-flop circuit 86 and it becomes operational. Furthermore, a gate pulse synchronized with the horizontal synchronizing signal is applied to the base of the transistor Q677 of this flip-flop circuit 86, thereby causing the output
The states of P4 and P5 are inverted every horizontal period. Next, in the phase synthesis circuit 88 shown in FIG.
Q755 turns off. For this reason, the transistor
Q752, Q753, Q754, and Q756 can be turned on, but which of the pair of transistors Q753 and Q754 and the pair of transistors Q752 and Q756 is turned on depends on the outputs P4 and P5 of the flip-flop circuit 86. Determined by state. That is, the output P4 of the flip-flop circuit 86 is applied to the bases of transistors Q752 and Q756, and the output P5 is applied to the bases of transistors Q752 and Q756.
It is added to the base of Q753 and Q754.
Now, when output P4 is at high level and output P5 is at low level, a signal of (k ₂ · b - k ₁ × a) is transmitted to the killer detection subcarrier (Killer detection subcarrier) via the collector of transistor Q750 → the collector of transistor Q756. -CW), and when the output P4 is low level and the output P5 is high level, the signal of (k ₁ · a - k ₂ × b) is killer detected via the collector of transistor Q749 → collector of transistor Q753. It is derived as a subcarrier (Killer-CW). In other words, the output of flip-flop 86
Depending on the states of P4 and P5, the subcarrier for killer detection (Killer-CW) is (k ₁・a−k ₂・b),
−(k ₁ ·a−k ₂ ·b) and is applied to the killer detection circuit 83 . Furthermore, during PAL reception, the collector potential of transistor Q844 of system switch circuit 79 is high, so phase synthesizer 8
Transistor Q760 in No. 8 is on, and transistors Q758 and Q759 are off. Therefore, transistor Q762 is also off, and resistor R734 is connected to transistors Q756 and Q753.
acts as a load alternately every horizontal period. The color killer detection subcarrier (Killer-CW) obtained as described above is the transistor Q633 of the killer detection circuit 83 shown in FIG.
Added to Q634 common base. In the killer detection circuit 83 shown in FIG. 9, as described above, the killer detection subcarrier (Killer-CW) whose phase is inverted by the output of the flip-flop circuit 86 and whose phase swings every horizontal period. A multiplication operation with the burst signal is performed. Therefore, the output obtained from the killer detection circuit 83 during PAL signal processing includes information on whether the color killer operation is performed or not, as well as information on whether the output phase of the flip-flop circuit 86 matches the burst swing phase. It also includes identity information indicating whether or not the ID is rejected. (5) [Control operation for flip-flop circuit by ident operation] Now, in the color color detection circuit 83, the phase of the killer detection subcarrier (Killer-CW) added to the bases of transistors Q633 and Q634 and the swing of the burst signal ( If the relationship (with a deviation of ±45°) is correct, that is, the subcarrier (Killer-CW) and the (RY) component are in phase, the currents flowing through transistors Q639 and Q641 will increase. When the current of transistor Q641 increases, the output voltage of killer filter 90 V _O
increases, and the terminal voltage of the killer filter also increases. As a result, the emitter current of transistor Q663 of the ident and killer circuit 85 increases, turning on transistors Q660 and Q659. When transistors Q660 and Q659 turn on,
Transistors Q661 and Q658 are turned off, and accordingly, transistors Q666 and Q665 are turned off.
Therefore, no current is supplied from the collector of transistor Q666 to the emitter of transistor Q675 constituting flip-flop circuit 86. This means that the flip-flop circuit 86
This means that the flip-flop circuit 86 continues to oscillate at the current phase without any control over the oscillation operation. In other words, the subcarrier (Killer
-CW) and the (RY) component of the burst signal or when they are in phase, the state of the flip-flop circuit 86 is not controlled. During PAL reception, the demodulation subcarrier (R-Y) obtained from the second phase synthesis circuit 88b in FIG.
The phase of CW is inverted by the outputs P5 and P4 of the flip-flop circuit 86 every horizontal period. Furthermore, when flip-flop circuit 86 is operating in the correct phase as described above, transistor Q665 is turned off. This causes transistor Q840 to remain off. Therefore, the pulse matrix circuit 75 also operates normally without being subjected to the killer operation. Also, at this time, the pulse matrix circuit 75
As described above, the chroma signals are subjected to addition and subtraction processing to derive the (RY) and (BY) components. Next, when receiving the PAL method, if the phase inversion state of the killer detection subcarrier (Killer-CW) and the phase inversion state of the (R-Y) component of the burst signal are opposite and different. I will explain about it. During NTSC signal processing, the (R-Y) demodulation carrier phase is used as the killer detection subcarrier (Killer-CW) during PAL signal processing, so the swing phase of the burst signal and the killer detection subcarrier phase do not match. In the killer detection circuit 83 of FIG. 9,
The detection voltage becomes low. In other words, the output voltage V _O of the killer filter 90 becomes low. Therefore, the emitter potential of transistor Q663 of the ident and killer circuit 85 becomes low, transistors Q660 and Q659 are turned off, and the transistor
Q661, Q658 are on, transistor Q666,
When Q665 is turned on and transistor Q666 is turned on, its collector current flows to the emitter of transistor Q675 of flip-flop circuit 86, that is,
It is supplied to the base side of transistor Q674, thereby causing flip-flop circuit 86 to stop oscillating. In this state, the killer filter output voltage V _O
The base voltage of the Q660, which has dropped from V _F , is further reduced to a _voltage ( _V
It continues as long as it is lower than _L - V _F ). On the other hand, the phase of the killer detection subcarrier (Killer-CW) supplied to the killer detection circuit 83 is as follows:
It is set near the (RY) axis during NTSC signal demodulation so that the (RY) axis component of the burst signal is large when it is positive and small when it is negative, and from the killer detection circuit 83 to the flip-flop circuit 86. The phase of the killer detection subcarrier (Killer-CW) when the flip-flop circuit 86 enters the stop mode is set so that the (RY) axis component is in the positive direction. ing. Therefore, from the moment the flip-flop circuit 86 stops, the killer detection output in the killer detection circuit 83 generates a large positive output and a small negative output, and as a result, the killer filter output voltage V _O increases. . At the moment when this filter output voltage V _O becomes V _O V _L with respect to the above-mentioned V _L , the on/off states of transistors Q660 and Q661 of the ident and killer circuit 85 are reversed, and as a result, transistor Q666 becomes The flip-flop circuit 86 is turned off, and the base voltage of the transistor Q674 of the flip-flop circuit 86 is controlled by the transistor Q677, and the flip-flop circuit 86 starts oscillating from the next horizontal synchronizing pulse. At this time, if the (R-Y) component of the input burst signal and the subcarrier for killer detection (Killer-CW) are in the correct phase relationship, the killer detection voltage will further increase, and the killer comparators of transistors Q659 and Q658 will Inverted, therefore the transistor
The Q665 turns off, clears the color killer state, enters color reception mode, and displays the correct colors on the screen. Next, as mentioned above, if we go back to the time when the voltage became V _O V _L and the flip-flop circuit 86 started inverting/non-inverting operation, we can see that the (RY) component of the input burst signal and the killer detection The subcarriers used (Killer-CW) do not always have the correct phase relationship, and there is a probability that they will have a phase difference of 180°. At this time, the killer filter output voltage starts to drop again from V _O V _L , and after several horizontal periods, transistors Q661 and Q660 as identity comparators are inverted again, which turns on transistor Q666 and turns on the flip-flop. The base of transistor Q674 of circuit 86 is forced high, causing flip-flop circuit 86 to stop operating. As a result, as described above, the killer filter's butterfly V _O starts to rise again toward V _L , and when it reaches V _O V _L , the (RY) component of the burst signal and the subcarrier ( Killer−CW),
It is determined whether V _O will rise further or fall again. In reality, when the flip-flop circuit 86 is released from the stopped state, the (RY) component of the burst signal and the subcarrier (Killer-
The probability of whether the phase relationship with CW) is correct or incorrect is assumed to be 50%, and the probability that the flip-flop circuit 86 will continue to be in a stopped state in an incorrect state is small. Therefore, correct color reception conditions can be obtained within a finite time. As mentioned above, if the phase relationship between the (R-Y) component of the burst signal and the subcarrier (Killer-CW) is wrong, the ident and killer circuit 8
The flip-flop circuit 86 is temporarily stopped and restarted by the function of the ident comparator formed by the transistors Q661 and Q660 in FIG. Furthermore, in the ident and killer circuit 85, a killer comparator is also constituted by transistors Q659 and Q658, and a killer voltage can be outputted via the collector of transistor Q655. When receiving the PAL method, the subcarrier (Killer
-CW) and the (R-Y) component of the burst signal are out of phase, the killer detection voltage becomes a low voltage (voltage lower than the set voltage V _L ) and the operation of the flip-flop circuit 86 stops (the killer detection voltage operation starts as the temperature rises), and color killer operation is obtained. Furthermore, when a burst signal is not detected during PAL reception, a color killer operation is obtained first, and the killer filter output voltage V _O at that time is V _L V
_O V _H. Therefore, in this case, the operation of flip-flop circuit 85 continues. Next, when the (R-Y) component of the burst signal and the subcarrier (Killer-CW) have the correct phase relationship, a high voltage V _H or higher is obtained as the killer detection voltage, and both transistors Q665 and Q666 are off. . That is, as shown in FIG. 17, if the output voltage of the killer filter 90 that samples and holds the detection output is equal to or higher than _VH , the color killer operation is stopped and the swing phase of the (RY) demodulation subcarrier is changed. If it is determined to be correct and the output voltage of the killer filter 90 is V _H V _O V _L , then
A color killer operation is performed, but the above (R-
Y) The swing phase of the demodulation subcarrier is determined to be correct. Next, when V _O >V _L , a color killer operation is performed, and it is determined that the swing phase of the (RY) demodulation subcarrier is incorrect, and the flip-flop circuit is controlled. [Effects of the Invention] As described above, according to the color demodulation device of the present invention, in a multi-system common color television receiver, the phase control of the detection axis in the color killer detection operation is performed according to the transmitted color signal to be processed. Phase inversion control and inversion stop control can be performed without malfunction. Therefore, it is possible to provide a color signal processing device suitable for processing multi-system color signals.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing a color signal processing circuit for NTSC system, Figure 2 is a block diagram showing a color signal processing circuit for PAL system, and Figure 3 is a color signal processing circuit for both PAL and NTSC systems. The configuration diagram shown in FIG. 4a is
FIG. 4 is a circuit diagram showing a color demodulation circuit of the circuit shown in FIG. 3, FIG. 4 b and c are vector diagrams shown to explain the operation of the circuit shown in FIG. 4 a, and FIG. FIG. 6 is a circuit diagram specifically showing the pulse matrix circuit and system switch circuit in FIG. 5, FIG. 7 is a circuit diagram specifically showing the demodulator in FIG. 5, and FIG. is a circuit diagram specifically showing the phase synthesizer shown in Fig. 5, and Fig. 9 is a circuit diagram showing the killer detection circuit shown in Fig. 5.
FIG. 10 is a circuit diagram specifically showing the flip-flop circuit and the IDENT and killer circuit in FIG. 5. FIGS. 11 and 12 are circuit diagrams specifically showing the operation of the pulse matrix circuit. Vector diagram shown for explanation, No. 13
Figures a and b are circuit diagrams showing other embodiments of the pulse matrix circuit, respectively, and Figure 14 is a circuit diagram for explaining the (G-Y) axis demodulation operation of the demodulator and phase synthesizer in Figure 5. Fig. 15a is a basic circuit diagram of the phase synthesizer, Fig. 15b and c are diagrams showing an equivalent circuit of the circuit in Fig. 15a, and Fig. 15d is a phase synthesis diagram of the circuit in Fig. 15a. The explanatory diagram shown to explain the operation, FIG. 16a, is a basic circuit diagram of the phase synthesizer used in the device of FIG. 5, and FIGS. 16b and c
16 is an equivalent circuit diagram of the circuit shown in FIG. and FIG. 7 is an operation explanatory diagram shown to explain the operation of the killer circuit. 66...1H delay device, 75...Palmatrix circuit, 76-78...Demodulator, 79...System switch circuit, 83...Killer detection circuit, 8
5...Ident and killer circuit, 86...Flip-flop circuit, 87...Voltage controlled oscillator, 8
8... Phase synthesizer.

Claims (1)

[Claims] 1. The color signal is transmitted by first and second modulation axes that are perpendicular to each other, and includes a carrier color signal in which the subcarrier for the second modulation axis is inverted every horizontal period. Processing of a first composite color signal, and a second composite color signal in which the color signal is transmitted by first and second modulation axes orthogonal to each other and without inversion of subcarriers with respect to the second modulation axis. a system switch that generates a system switching signal for switching which signal to process, the first composite color signal or the second composite color signal; According to switching control,
When performing color killer processing on the first composite color signal, (R-
One input signal is a phase signal substantially the same as the (R-Y) subcarrier for which Y) axis color demodulation is to be performed, and a burst signal separated from the first composite color signal is applied as the other input signal. A color killer detection circuit having the phase signal as a detection axis; and a first detection circuit for detecting the output level of the output circuit of the color killer detection circuit and controlling the color killer operation of the color killer circuit according to this detection level. output terminal, and outputs an identification signal indicating suitability of the phase of the (RY) color subcarrier with phase inversion for each horizontal period, which is used for (R-Y) axis color demodulation of the first composite color signal. an Ident circuit having a second output terminal for outputting the Ident circuit, a voltage level of the output terminal is regulated according to the output of the Ident circuit, and an Ident signal outputted to the second output terminal of the Ident circuit has the phase inversion. When the voltage is appropriate, a transmission operation is performed to set the level of the output terminal to the first voltage level and the second voltage level in synchronization with the horizontal synchronization signal, thereby controlling the phase of the (R-Y) color subcarrier. and a flip-flop circuit for processing the second composite color signal under switching control of the system switch, the voltage level of the output terminal of the flip-flop is different from the first and second voltage levels. A color signal processing device characterized by setting a different third voltage level and stopping the phase inversion operation.