JPS6137878B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a device that generates a pulse train for driving a pulse motor or the like in numerical control or the like.

Numerical control devices have both automatic and manual operation functions, and when a pulse motor is used as the driving means for this device, the pulse train generation must be switched between automatic operation and manual operation in order to obtain the above functions. I have to. That is, in automatic operation, the generation period of the pulse train is determined in advance according to the target position, and in manual operation, the generation period of the pulse train can be arbitrarily changed using a dial or the like. In addition, if pulses with a constant period are applied consistently during operation, the rotation cannot follow when starting and stopping, so the period of the pulses applied at starting and stopping is changed gradually to provide acceleration and deceleration characteristics. There is a need.

Conventionally, a circuit as shown in FIG. 1, for example, has been used as a circuit for generating a pulse train. In this example, the automatic operation pulse train Pa is given from the outside by a magnetic tape or the like, and the manual operation pulse train Ph is generated by the variable frequency oscillator 1 in response to a command from the manual speed command dial 3. Both pulses P _a and P _h are applied to the automatic/manual changeover switch _SW1 , and one of them is selected and applied to the automatic acceleration/deceleration circuit 2. The automatic acceleration/deceleration circuit 2 provides an input pulse train with acceleration characteristics and deceleration characteristics (gradually changing the pulse generation period) at the time of starting and stopping, respectively, and outputs the resultant pulse train.

In the configuration shown in Figure 1 above, the automatic acceleration/deceleration circuit 2
is complicated, and it is not possible to simply use a pulse motor or the like.

Therefore, there is a device that improves this point and is configured as shown in FIG. The circuit shown in FIG. 2 includes dedicated pulse generating circuits 4 and 5 for automatic operation and manual operation, respectively. Each of the pulse generating circuits 4 and 5 includes a time constant circuit, a voltage-frequency converter, etc. (not shown). In these pulse generation circuits 4 and 5, the speed command is given as an analog voltage, and the rise (start) and fall (stop) of this voltage are slowed down and accelerated by a time constant circuit consisting of a capacitor, a resistor, etc. Furthermore, the analog voltage imparted with the acceleration characteristic is converted by a voltage-frequency converter into a pulse having a frequency corresponding to the magnitude of the voltage. Then, these pulses are taken out from the pulse generation circuits 4 and 5 as an automatic operation pulse train P _a and a manual operation pulse train P _h , respectively, and are
Either one is selected using a manual changeover switch S _W2 .

The configuration shown in FIG. 2 has the disadvantage that the time constant of the time constant circuit must be adjusted in each circuit 4, 5, making the adjustment troublesome.

This invention was made in view of the above points,
The present invention aims to provide a speed command pulse train generator such as a pulse motor with a simple configuration.

According to this invention, one pulse generation circuit is shared between automatic operation and manual operation, and during automatic operation, an analog voltage corresponding to a preset speed is applied to this pulse generation circuit, and a period corresponding to this analog voltage is applied. A pulse train is generated and used directly to control the speed of a pulse motor, etc. During manual operation, the pulse generator circuit generates the highest frequency pulse that can be generated, and this pulse is used to control the speed of a manual dial, etc. The speed is controlled by creating a pulse train with a frequency corresponding to the speed specified by . With this configuration, it is sufficient to provide one oscillator and one circuit (for example, a time constant circuit) for obtaining acceleration/deceleration characteristics, thereby simplifying the configuration and making it easy to adjust the time constant, etc.

The present invention will be described in detail below based on one embodiment of the accompanying drawings.

In FIG. 3, a pulse generating circuit 6 is similar to the automatic driving pulse generating circuit 4 shown in FIG. 2, and is comprised of, for example, a time constant circuit 6a and a voltage-frequency conversion circuit 6b. The analog voltage V applied to the pulse generation circuit 6 as a speed command has an increasing characteristic (acceleration characteristic) at the rising edge (meaning the start of operation) in the time constant circuit 6a, and attenuates at the falling edge (meaning the stopping of the operation). A characteristic (deceleration characteristic) is given. The speed command voltage V to which the increase and attenuation characteristics have been applied is applied to the voltage-frequency conversion circuit 6b, and the pulse train has a frequency corresponding to its magnitude, that is, the frequency gradually increases at the beginning, and reaches a constant frequency at a certain point. It outputs a pulse train that is maintained and gradually becomes lower as it progresses further. In this embodiment, during automatic operation, the speed command voltage V is determined according to the target position, etc.
is added to the pulse generation circuit 6 to obtain a pulse train with a frequency corresponding to the magnitude of the voltage.
For example, when the speed command voltage V is given as a DC voltage as shown in FIG. This signal is further converted into a pulse train as shown in c in the figure in the voltage-frequency converter 6b.

Also, during manual operation, the pulse generation circuit 6 receives a large speed command voltage as shown in Figure 5a.
Vmax, and the pulse train of the highest frequency that can be generated from this pulse generation circuit 6 (shown in Figure 5c)
(Figure 5b shows the voltage output from the time constant circuit 6a at this time). The pulse train Pb output from the pulse generating circuit 6 is applied to the frequency limiting circuit 7. The frequency limiting circuit 7 acts only during manual operation, and the output pulse train Pb of the pulse generation circuit 6 passes through this circuit 7 as is during manual operation. This frequency limiting circuit 7 is for creating a pulse train for manual operation using pulse train Pb during manual operation. That is, during manual operation, as described above, the pulse generator circuit 6 generates a pulse train Pb as shown in FIG. 5c.
is output, but the period of this pulse train Pb corresponds to the speed set with the manual speed command dial 8 (this is T, and the frequency at that time is F).
If the pulse train Pb is longer (frequency is lower than F), the pulse train Pb is output as is, and if it is shorter (frequency is higher than F), a pulse train of period T is generated and output based on this pulse train Pb. The upper limit of the frequency of the pulse train is limited. In other words, during manual operation, the frequency limited circuit 7
The output pulse train (hereinafter referred to as pulse train Pc) is generated by the pulse generation circuit 6 as shown in FIG. 5d.
When the period of the output pulse train is short, the period is limited to T.

A detailed example of the frequency limiting circuit 7 is shown in FIG.

A pulse train Pb as shown in FIG. 7a output from the pulse generating circuit 6 shown in FIG. 3 is applied to an AND circuit 10 of the frequency limiting circuit 7. The AND circuit 10 has a pulse interval T of the pulse train Pb set by the manual operation speed designation dial 8.
If it is longer, operation is possible and the relevant pulse train
Pb is passed through the OR circuit 11 to the pulse generation circuit 1
Lead to 2. 1 pulse generation circuit 12 is an OR circuit 11
This is to shape the pulses, which have irregular widths, derived from , into a constant width.

The output pulse train Pc of the 1-pulse generation circuit 12 is output from the frequency limiting circuit 7, and in addition to being used as a speed command pulse for a pulse motor etc. (not shown), it is also applied to the pulse interval detection circuit 13 to determine the pulse interval of the pulse train Pb. It is used as a signal to determine the timing for starting detection. Pulse interval detection circuit 1
3 is the output pulse Pc of the above-mentioned 1 pulse generation circuit 12
In addition, the output pulse Pb of the pulse generating circuit 6 and the manual operation speed command signal V _h guided through the manual speed command dial 8 are inputted, respectively, and the period T corresponding to the command signal V _h is calculated from the generation of the pulse Pc. This is to detect whether or not a pulse Pb is generated within (shown by diagonal lines in FIG. 7). That is,
If pulse Pb does not occur within this detection period (here, if it rises at the same time as the start of the detection period, it will not be detected), the period of pulse Pb is longer than the period T specified by dial 8 (the specified frequency The output S _t of the pulse interval detection circuit 13 becomes "0" after the detection period T. Furthermore, if a pulse Pb is generated within the above detection period, the period of the pulse Pb is considered to be shorter than the period T (higher than the specified frequency), and the output St of this circuit 13 continues to be "1". . The output signal St of the pulse interval detection circuit 13 is applied to a flip-flop circuit 14 and a pulse generation suppression circuit 16. In addition, the pulse interval detection circuit 1
3 outputs to the self-exciting circuit 15, in addition to the above-mentioned signal St, a signal Sp which becomes "0" when the signal Pc falls and becomes "1" after the detection period T has elapsed. In addition,
Details will be described later.

The pulse generation suppressing circuit 16 is a circuit for preventing the input pulse Pb from being outputted from the frequency limiting circuit 7 when the generation period of the input pulse Pb is shorter than the specified period T. That is, the pulse generation suppression circuit 16 outputs a signal "1" in synchronization with the pulse interval detection period in order to prevent the input pulse Pb from being output even if it enters the pulse interval detection period.
This signal "1" is applied to the inverting input of the AND circuit 10 to disable the AND circuit.
Therefore, during the pulse interval detection period, the pulse
Even if Pb is input, it is no longer output from the frequency limiting circuit 7.

The self-exciting circuit 15 to which the output signal S _f of the signal Sp of the flip-flop circuit 14 and the pulse interval detection circuit 13 is applied operates while the conduction of the input pulse Pb is blocked by the AND circuit 10 (the period of the pulse Pb is shorter than T). ), a pulse with a period T is generated instead of this pulse Pb and the frequency limited circuit 7
This is for outputting from. That is, as described above, the flip-flop circuit 14 sets the output signal S _f to "1" when the pulse Pb is input within the pulse interval detection period, and the self-excitation circuit 15 receives the signal from the pulse interval detection circuit 13 in synchronization with the detection period. When the output signal S _f of the flip-flop circuit 14 is "1" at the end of the detection period, a trigger pulse P _t as shown in FIG. 7d is generated in synchronization with the end of the detection period. Output. This trigger pulse _Pt is applied to flip-flop circuit 14 and resets this circuit. Further, the trigger pulse P _t is applied to the one-pulse generating circuit 12 via the OR circuit 11, and the pulse width is corrected to be constant and output from the frequency limiting circuit 7. As mentioned above, the detection period in the pulse interval detection circuit 13 is
It starts in synchronization with the rise of the output pulse Pc of the pulse generation circuit 12, and the self-excitation circuit 15 does not generate the trigger pulse _Pt unless the detection period ends, and the 1-pulse generation circuit 12 generates the trigger pulse It generates a pulse Pc based on _Pt , and even if the period of the input pulse Pb continues and is shorter than the period T, the output pulse of the one pulse generation circuit 12
Pc, that is, the generation period of the output pulse of the frequency limiting circuit 7 is consistently T.

Here, an example of the operation of the frequency limiting circuit 7 will be described in the seventh section.
The explanation will be based on the timing chart shown in the figure.

First, a pulse Pb ₁ is input at time t ₁ (FIG. 7a), and if the AND circuit 10 is enabled at this time, a pulse Pc ₁ is output from the 1-pulse generating circuit 12 in synchronization with the pulse Pb. (Figure 7f). The first detection period begins in synchronization with the rise of this pulse Pc (FIG. 7b). Further, in synchronization with the first detection period, the output of the pulse generation suppressing circuit 16 becomes "1", and this signal prevents the pulse train Pb from conducting during the detection period. Since no other pulse is input within the first detection period after the pulse Pb ₁ is applied, the output signal S _f (FIG. 7c) of the flip-flop circuit 14 is "0", and therefore the self-excitation occurs at this time. Trigger pulse P _t (seventh
Figure d) is not generated. pulse at time t ₃
When Pb ₂ is input, since the first detection period has ended at this time, the pulse Pb ₂ is directly output as the pulse Pb ₂ via the one-pulse generating circuit 12. Furthermore, since the pulse Pb ₃ is generated after the end of the second detection period starting from time t ₂ , it is output as is. Pulses Pb ₄ to Pb ₇ are applied during the third detection period starting from time t ₃ , but since the AND circuit 10 is inactive at this time, its conduction is blocked. Also,
At this time, the output of the flip-flop circuit 14 becomes "1" in synchronization with the rise of the pulse _Pb4 , and based on this signal "1", the trigger pulse _Pt is generated at the end of the third detection period. Based on this trigger pulse _Pt , a pulse _Pc4 is output at the same time _t4 . The time interval from pulse Pc ₃ to generation of pulse Pc ₄ thus corresponds to the detection period, ie T. The fourth detection period starts simultaneously with the end of the third detection period by pulse Pc ₄ . During this fourth detection period, pulses Pb ₃ and Pb ₉ rise, and the output signal S _f of the flip-flop circuit 14 becomes "1".
Therefore, a trigger pulse is generated again at the end of the detection period. In this way, the pulse within the detection period
When Pb is input, a trigger pulse P _t is generated every time T, whereby a pulse Pc with a period T is output from the frequency limiting circuit 7.

As described above, during manual operation, the frequency limiting circuit 7 operates when the generation period of the input pulse train Pb is longer than the period T corresponding to the speed set on the dial 8 shown in FIG. 3 (when the frequency is low).
outputs this pulse Pb as is, and conversely, if it is shorter than the period T (if the frequency is high), the pulse
Pb is prevented from conducting, and instead, this frequency limiting circuit 7 generates and outputs pulses with period T.

By the way, during automatic operation, by setting dial 8 to the maximum speed, the input pulse
Pb is allowed to pass through the frequency limiting circuit 7 as it is no matter what its period. That is, as mentioned above, the frequency limiting circuit 7 is connected to the dial 8.
Since the conduction of this pulse train Pb is blocked only when the period of the input pulse train Pb is shorter than the period T set in Pb is always output from the frequency limiting circuit 7 as is.

Specifically, the block diagram shown in FIG. 6 is constituted by a circuit as shown in FIG. 8, for example. In FIG. 8, circuits and signals corresponding to those shown in FIG. 6 are given the same numbers. As shown in FIG. 8, the one-pulse generation circuit 12 can be configured as a monostable multivibrator, the pulse generation suppression circuit 16 can be configured as a positive edge trigger D flip-flop circuit, and the self-excitation circuit 15 can be configured as an AND circuit. . Furthermore, the monostable multivibrator 13a receives a signal indicating the detection period according to the signal _Vh among the functions of the pulse interval detection circuit 13.
It has the function of outputting Pp. Further, the positive edge trigger D flip-flop circuit 14a takes over the remaining functions of the pulse interval detecting circuit 13, that is, detecting pulse intervals and the functions of the flip-flop circuit 14. The operation of the circuit shown in FIG. 8 is almost the same as the operation of the block diagram shown in FIG. I'll keep it. In Fig. 9, a is the input pulse train
Pb represents the output signal of the monostable multivibrator 13a, c and d represent the output signals of the positive edge trigger D flip-flop circuits 16 and 14a, respectively, and e represents the output pulse train Pc, respectively.

As explained above, according to the present invention, an oscillator used in a circuit that generates a pulse train used to operate a pulse motor, etc. and a circuit for obtaining acceleration/deceleration characteristics (for example, a time constant circuit) can be used in automatic operation or manual operation. Since it can be shared by both, the overall circuit configuration is simplified and acceleration/deceleration adjustment (adjustment of a specific number) is easy.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional pulse train generating circuit, FIG. 2 is a block diagram showing another conventional pulse train generating circuit, FIG. 3 is a block diagram showing an embodiment of the present invention, and FIGS. 5 is a timing chart showing an outline of the operation of the embodiment shown in FIG. 3, FIG. 6 is a block diagram showing a detailed example of the frequency limiting circuit shown in FIG. 4, and FIG. A timing chart showing an example of the operation of the detailed example shown, FIG. 8 is a circuit diagram showing a specific example of the configuration of the block diagram shown in FIG. 6, and FIG. This is a timing chart showing an example. 6... Pulse generation circuit, 6a... Time constant circuit,
6b... Voltage-frequency conversion circuit, 7... Frequency limited circuit, 12... 1 pulse generation circuit, 13... Pulse interval detection circuit, 14... Flip-flop circuit, 15... Self-excitation circuit, 16... Pulse width Inhibitory circuit.

Claims (1)

[Scope of Claims] 1. Speed command voltage output means that outputs a speed command voltage indicating a preset speed during automatic operation, and outputs a speed command voltage indicating the maximum speed instead of the speed command voltage during manual operation; a time constant circuit that moderates the rise and fall of the speed command voltage input from the speed command voltage output means and outputs a speed command voltage having gentle acceleration and deceleration characteristics; A voltage-frequency conversion circuit that generates the first pulse of frequency, and a means for setting the minimum period of the output pulse, which is set to a period corresponding to the maximum speed during automatic operation, and corresponds to the desired speed during manual operation. a minimum period setting means for setting the period to a period of 1, pulse interval detecting means for measuring the period of the set minimum period from the output point every time the output pulse is output; and inputting the first pulse; The output of the first pulse that is input after the output pulse that is the starting point of the period within the period measured by the pulse interval detection means is blocked, and the unblocked first pulse is converted into a second pulse. pulse generation suppressing means for outputting a pulse as a pulse, and means for detecting whether or not the first pulse is blocked during the measurement period, and generating a third pulse at the end of the period if the first pulse is blocked. A speed command pulse train generation device for numerical control, etc., comprising: a means for synthesizing the second pulse and the third pulse and using this as the output pulse.