JPS6138510B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a buffer memory control method for a communication control device connected to a main body processor and accommodating a plurality of line terminals. The buffer memory control method conventionally implemented in communication control devices of data communication systems divides a predetermined buffer area into multiple subareas corresponding to the number of lines accommodated, and each subarea is fixedly assigned to each terminal. "Individual allocation method". In this method, the subarea corresponding to each line is either (1) a fixed size for all terminals regardless of the operating speed of the line terminal, or (2) a variable size depending on the operating speed of the line terminal. However, in either case, the following drawbacks can be considered. In other words, in the fixed size method, the scan frequency of each subarea must be changed at least according to the line terminal speed, but if the line terminal or communication control device of the other station is a different model and has a low operating speed, the transmission data This is insufficient because the confirmation response may not be returned within the expected time. On the other hand, even in the variable size method, the start address of each subarea is affected by the operating speed of the terminal, so terminal speed information must always be referenced when accessing a subarea, and data reading and writing may occur frequently. This causes a significant decrease in the processing capacity of the communication control device. At the same time,
Flexibility for changing line capacity also decreases. Furthermore, in the individual line allocation method described above, each subarea is fixedly allocated to each line terminal, so even if the traffic applied to other line terminals is low and there is a lot of free space in the subarea, the subarea of the own line terminal It cannot handle traffic larger than .
Therefore, when the traffic handled by each terminal fluctuates over a wide range, it is customary to set the subarea size in anticipation of high traffic, which reduces the efficiency of buffer area usage and increases the number of terminals that can be accommodated. It may be limited by the upper limit of the buffer size. In addition, the individual line allocation method is generally highly affected by the addition of accommodated lines and has low flexibility. The present invention has been made in view of the above-mentioned drawbacks of the conventional system, and its purpose is to provide a buffer memory control system that can efficiently accommodate and process a large number of different speed line terminals. The above-mentioned object of the present invention is achieved by the configuration of the present invention in which all line terminals commonly use the entire buffer area, ie, the so-called "line common allocation system." The details of the present invention will be explained below with reference to Examples. The communication control device of the present invention accommodates a plurality of line terminals of different speeds and has a variable length data unit (however, "data unit" refers to one transfer unit of data).
It has a general form of transmitting and receiving data and performing error control functions such as data sequence error detection and retransmission processing. First, an overview of the configuration and operation of the communication control device of the present invention will be explained with reference to FIG. 1 regarding the portions directly related to the present invention. A communication control device 1 which accommodates m line terminals 3, 4...5 and is connected to a main body processor 2.
is composed of an input/output control section 6, an internal memory 9, and others (not shown). The input/output control section 6 stores the transmission data from the main body processor 2 in the internal memory 9.
Once captured, it is read out by a predetermined process and transferred to a specific line terminal. In addition, the input/output control unit 6 once imports data received by the line terminal into the internal memory 9 in predetermined units (for example, bytes), reads the received data from the internal memory 9 through a predetermined process, and transfers it to the main body processor 2. . In addition, the communication control device 1 includes conventional control means for performing error control such as assigning sequence numbers to transmitted or received data taken into the internal memory 9 and checking for sequence errors, as well as various other control means. However, illustration of these is omitted. Note that 7 and 8 are lines. Next, the configuration of the internal memory 9 in the present invention will be explained with reference to FIGS. 2 and 3. As shown in FIG. 2, the internal memory 9 has a buffer area 1.
It is divided into two parts: 1 and a control area 20. The buffer area 11 has n data cells 1 of equal size.
It is divided into 2, 13, 14...15. Each data cell is divided into a field If16 for holding external input data and a field Cf17 for making a chain connection with other data cells, and the Cf field is further divided into multiple data cells holding the same data unit. It is divided into a field Cf _i 18 for connecting between different data units, and a field Cf _p 19 for connecting between different data units. Next, the structure of the control area will be explained with reference to FIG. The control area 20 and the buffer area 11 constitute the internal memory 9 of the communication control device 1 . The control area 20 includes two types of pointers P _CH 21 and P _{CT 20 that indicate the first and last data cells of a queue common to all lines, which is configured by connecting empty data cells in a chain, and a data pointer P CH 21 and P CT} 20 . Four types of pointers indicating the first and last data cells of the queue for each line terminal (representatively #i line) configured by connecting the retained data cells in a chain; P ⁱ _HR 23-25 and P ⁱ _TR 26-28, and
P ⁱ _HS 29-32 and P ⁱ _TS 33-3 on the sending side
5
It is composed of. Communication control device 1 of FIG. 1 configured as described above
The operation will be explained with reference to FIGS. 4 and 5. Before data transmission/reception is started within the communication control device 1, the buffer area 11 and control area 20 in the internal memory 9 are initialized by the input/output control unit 6 in the communication control device 1 as shown in FIG. Set. That is, all empty data cells in the buffer area 11 are connected in a chain to form a queue 36 common to all lines. Of the pointers in the control area 20, P _CH and P _CT point to cells 12 and 15 at the beginning and end of the queue 36, but other pointers point to any data cell as indicated by reference number 100. It does not even instruct. When the initial settings are completed, data input/output via the memory 9 is executed, but in one embodiment of the present invention, the processing on the transmitting side and the receiving side is symmetrical, so the receiving side The present invention may be fully understood with a limited explanation. Furthermore, since the processing for the line terminal is the same for each terminal, line terminal #i will be described as a representative. In addition, the size of the data cell is, for example, 1 byte/word x 18 words, of which 4 words (i.e. 2 words as Cf _i and 2 words as Cf _p)
shall be assigned to the field for chain connection. After the initial settings described above, as shown in FIG. 5A,
For example, assume that a 16-byte data unit 37, a 32-byte data unit 38, and a 9-byte data unit 39 are input from line terminal #i. The three units of data 37 to 39 are stored in the free data cell queue 36 by the input/output control section 6.
Figure 5B
They are connected and stored in a chain as shown in the figure.
In FIG. 5B, data cells 40-42, 43-4
6, 47-48 correspond to the input data units, , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , of FIG. 5A, respectively. These data cells are each chained together by a _Cfi field, and queues 49, 50,
51. Each queue 49, 50, 51
The length (number of bytes) of the corresponding data unit is held in the first cells 40, 43, and 47 of the data unit. The leading cells 40, 43, and 47 are further chain-connected in the order of data unit input by the Cf _p field to form a queue for each line terminal (here, the receiving side of terminal #i), and the leading cells 40
is indicated by the control area pointer P ⁱ _HR , and the last cell 47 is indicated by P ⁱ _TR . The data stored in the buffer area 11 by the input/output controller 6 as shown in FIG. Output to.
In the case of FIG. 5, data in data cells 41 and 42 are output in the same order, and then data cells 44 and 4 are output.
Data in cells 5 and 46 are output in the same order, and finally data in data cell 48 is output. The data cell from which data has been outputted in this way becomes empty and is released from the chain connected by the input/output control unit 6, and the remaining cells of the empty data cell queue 36 (control area pointer P _CT It is added after the (indicated by the word). In FIG. 5, the data cells are 41,4
2, 40 (and above, compatible with data units), 4
4, 45, 46, 43 (corresponding to a data unit), 48, 47 (corresponding to a data unit), and returned to the empty data cell queue 36 shown in FIG. 4 in the order of release. It can be done. As the data cell is released and added to the free data cell queue, the control area pointer P
ⁱ _HR , P ⁱ _TR , and P _CT are updated. Note that the release order of data cells is defined by tracing the chain of the Cf _i field and the chain of the Cf _p field. FIG. 6 is a block diagram of one embodiment of the input/output control section 6 of FIG. 1. 60 is a microprogram memory (μPM) that stores a microprogram;
1 is a microinstruction register (μIR) that holds the microinstruction currently being processed, and 62 is a microprogram sequence control unit that determines the conditions of input signals based on the instructions of the microinstruction and controls the execution order of the microprograms. (μPSQC), 6
Reference numeral 3 denotes a register-built-in arithmetic and logic unit (RALU) which has a plurality of registers and performs various specified arithmetic operations and outputs the operation results and status. 6
Reference numeral 4 denotes a transmit/receive data buffer (PDBUF) for the processor interface which performs temporary storage for transmitting and receiving data to and from the processor main body 2, and is used for both transmitting and receiving. 65 is a decoder (DEC) that decodes the microinstruction held in μIR 61 and issues a processing request to the processor body 2;
Reference numeral 66 denotes a control data buffer (PCBUF) for the processor interface that temporarily stores data for controlling transfer with the processor. The RALU 63 counts the number of bytes taken in a data cell, the number of cells in a unit configuring a unit level queue, the length of a received data unit, etc.
It also includes various registers for holding the queue pointer and other control parameters read from the control area 20 of the MEM 9 in order to control referencing, changing, etc. of the queue pointer. The table below shows an example of the allocation of the counters and pointers to the registers during the input/output process on the line side.

[Table] The RALU63 executes various arithmetic operations on various control parameters held in each register in the above table based on microinstructions, and returns the status "0", "overflow", "carry", etc.
It is output on the signal line 73 connected to the PSQC 62. On the other hand, the line terminals 3, 4... are connected to the transmission lines 7, 8...
Receives bit serial data from... and sends it to the line terminal transmit/receive buffers (TBUF) 70, 71...
It is temporarily held in... In addition, these TBUF70, 71
... is installed independently for each transmission and reception, and in addition to the above value parallel conversion, a delimiter code (flag)
It also detects, removes, etc. These line terminals 3 and 4
When TBUF70, 71... receives 1 byte of data or completes the reception of 1 unit of data, it sends information indicating that to μ.
It is output onto the signal line 72 that is input to the PSQC 62.
Similarly, line terminals 3, 4... are TBUF70, 71...
When one byte of data has been sent or one unit of data has been sent, information indicating this is output onto the signal line 72. The μPSQC 62 receives data reception information from the line terminals 3, 4, .
Literal information used for creating fixed addresses, initializing the RALU, etc. is transferred to the RALU 63 via the μIR 61. The μIR 61 also causes the μPSQC 62 to input information such as +1 (next microinstruction) specifying the execution order of the microprogram, jump, subroutine call, test item designation, and so on. μIR61 also has an empty signal indicating that there is no sending signal, and a data unit delimiter (flag).
The line terminal control information instructing the sending of the information, etc., is sent to the line terminals 3, 4, . . . via the control signal line 75.
In this way, the received data is transmitted from line terminals 3 and 4 to
RALU63→MEM9→RALU63→PDBUF64
->Processor 2, while the transmitted data is transferred in the opposite direction along the same route as the above-mentioned received data. A specific example of the process of initializing the memory (MEM9) shown in FIG. 4 is shown in FIG. First, in step 1 of FIG. 7, the address of the first cell in the buffer area is loaded into _PCH.This step is shown in more detail as follows. (1) MAR lower ← 0 MAR upper ← 0 MEM (PCH lower) ←8m+4 (literal) MAR lower ← 1 MEM (PCH upper) ← 0 Here, MAR lower is the memory address register
This is the lower byte section of MAR (FIG. 6), and similarly on MAR is the upper byte section of the memory address register. Also 8m+4
is the address of the first cell in the buffer area when the number of accommodated terminals is m (see FIG. 4). Also, the display (literal) indicates that the operation is based on literal information from the μIR 61 in FIG. Similarly, step 2 of FIG. 7, in which the address of the last cell in the buffer area is loaded into _PCT , is shown in more detail as follows. (2)

[Table] Here, 8m+4+18(N-1) is the address of the last cell in the buffer area when the data cell size is 18 bytes and the number of data cells is N. (literal) has the same meaning as described above. A specific example of step 3 in FIG. 7 for creating an empty cell queue Q, step 4 for processing the last cell of the empty cell queue, and step 5 for clearing individual line control information is as follows. (3) Creating empty cell Q

【table】 (4) Processing of the last cell of empty cell Q

[Table] (5) Clear line individual control information to 0 R13←8m (literal) Lower MAR←4 (literal) Upper MAR←0 LBLB) MEM←0 R13←R13−1 Y←R13〓R13 Is Y=0? If it is 0, jump to step 6 MAR lower ← MAR lower + 1 Jump to LBLB The above clearing operation is performed from address 4 to address 8m+3. FIG. 8 shows an overview of input/output operations on the line terminal side.
The figure shows an example of the operation when the number of line terminals is m, and this m value is lateral information. Further, the number terminal number is held in a register in the RALU 63 in FIG. An example of the process of "line terminal #i input processing" in FIG. 8 is shown in FIG. The details of each step 1, 2, 3...19 in FIG. 9 are as follows. Step 1 Check for data reception request. If not, go to step 9. A test command is used to test whether there is a data reception request from line #i, and a jump or sequence to the specified jump destination address is specified.
. . .μPSQC Here, the description “μPSQC” in the operation description indicates that the block that actually operates in response to a microinstruction is μPSQC 62 in FIG. Similarly, the names of the blocks shown in FIG. 6 described in the explanation of the operations indicate the blocks that perform the actual operations. Details of Step 2 and subsequent steps are as follows. (2) Is IC ₁ = 14? If No, go to step 4. Instruct RALU to “R0 (IC ₁ ) – 14”, 14
is a literal...RALU Checks the operation result (0 or not)...μ
PSQC (3) Hunt for empty cells, IC ₁ ←0, IC ₂ ←IC ₂ +1

【table】

[Table] Ral
(4) Input 1 byte of data from line terminal #i (TBUF) to the cell, IC ₁ ←IC ₁ +1, IC ₃ ←IC ₃ +1

[Table] (5) Is IC ₁ = 14? If No, go to step 19. The only difference is the jump destination address, but the rest is the same as step 2. (6) Is IC ₂ = 1? If Yes, go to step 8 Perform R1-1 operation...literal, RALU
0 test...μPSQC (7) Register the cell to unit level Q. Go to step 19

[Table] (8) HP←P _I , TR←P _I , go to step 19 HP←P _I :R5←R3...RALU R6←R4...RALU TP←P _I :R7←R3...RALU R8←R4 ...RALU Go to step 19: Unconditional jump...MPSQC (9) Is 1 unit reception complete? If No, go to step 19. Check by test command (specify whether or not a termination flag has been received from line #i, specify jump destination address, and sequence)...
MPSQC (10) IC ₁ = 14? If Yes, go to step 12. Basically the same as step 2. (11) Register the cell to the unit level Q See step 7 (12) Hunt for empty cells See step 3 (13) The cell ← IC ₃ (data unit length) Lower MAR ← R3 (lower P _I )... ...MAR, RALU On MAR←R4 (on P _I )... MEM←R2 (IC ₃ )...MEM, RALU (14) Place the cell at the beginning of unit level Q

[Table] (15) IC ₁ ←14, IC ₂ ←0, IC ₃ ←0 R0 (IC ₁ ) ←14...Literal, RALU R1 (IC ₂ ) ←0... Literal, RALU R2 (IC ₃ ) ← 0...Literal, RALU (16) Is P ⁱ _HR (=P ⁱ _TR )=0? If yes, go to step 18

【table】 (17) Register the unit level Q to the line level Q

[Table] (18) P ⁱ _HR ←HP, P ⁱ _TR ←HP

[Table] 〓Literal
MEM←R5 (lower HP)…MEN, RALU
MAR lower ← MAR lower + 1…MAR, RALU, literal
MAR top←MAR top＋Carry…MAR, RALU
MEM←R6 (on HP)…MEM, RALU
P _TR ⁱ ←HP: Same as the second half of step (17)
be.
(19) Proceed to the next process FIG. 10 shows an example of the process of "line terminal #i output processing" in FIG. 8. The details of each step 1, 2, 3...17 in FIG. 10 are as follows. (1) Check for data transmission request. If not, go to step 17. Check by test command (designation of data transmission request existence test for line #i. Specify jump destination address and sequence). ...μ
PSQC (2) Is P ⁱ _HS (= P ⁱ _TS ) = 0? If yes, go to step 16

[Table] (3) Is OC ₃ = 0? If No., go to step 5. Execute R10 = R10 (logical OR). Run the result 0 test. If ≠0, jump to step 5. (4) OC ₃ ←P ⁱ _HS ↑． Unit length, P ₀ ← ⁱ _HS ↑.
Cf _i , OC ₁ ←0

【table】

[Table] (5) Output 1 byte of data from the cell to line terminal #i (TBUF) OC ₁ ←OC ₁ +1 OC ₃ ←
OC ₃ -1 Data output: MAR lower ← R11 (P _p lower) + R9
(OC ₁ ) MAR top←12 (P _p top) + Carry TBUF←MEM OC ₁ ←OC ₁ +1: R9←R9+1 OC ₃ ←OC ₃ −1: R10←R10−1 (6) Is OC ₃ = 0? If yes, go to step 10 Basically the same as step 3 (only the jump destination is different) (7) Is OC ₁ = 14? If No, go to step 17 and execute R9-14. Test the result, if ≠0, jump to step 17. (8) Release of the cell and registration in empty cell Q P _CT ↑. Cf _i ←P _p : MAR lower ← 2 MAR upper ← 0 WR ← MEM (lower byte of P _CT ) MAR lower ← MAR lower + 1 MAR upper ← MAR upper + Carry WR′ ← MEM (higher byte of P _CT ) MAR lower ← WR + 14 (P _CT ↑. Lower address of Cf _i ) Upper MAR ← WR' + Carry (P _CT ↑. Upper address of Cf _i ) MEM ← R11 (lower byte of P _p ) Lower MAR ← Lower MAR + 1 Upper MAR ← Upper MAR +Carry MEM←R12 (upper byte of P _p ) P _CT ←P _p : MAR lower ← WR MAR upper ← WR' MEM←R ₁₁ (lower byte of P _p ) MAR lower ← MAR lower + 1 MAR upper ← MAR upper + Carry MEM ←R12 (upper byte of P _p ) P _p ←P _CT ↑． Cf _i : MAR lower ← WR + 14 MAR upper ← WR′ + Carry R11 (P _p lower) ← MEM (P _CT ↑. Cf _i lower) MAR lower ← MAR lower + 1 MAR upper ← MAR upper + Carry R12 (P _p upper) ← MEM (P _CT ↑. Cf _i top) P _CT ↑. Cf _i ←0: MAR lower ← WR + 14 MAR upper ← WR' + Carry MEM (P _CT ↑. Cf _i lower) ← 0 MAR lower ← MAR lower + 1 MAR upper ← MAR upper + Carry MEM (P _CT ↑. Cf _i upper) 0 P _CT ↑. Cf _p ←0: MAR lower ← WR + 16 MAR upper ← WR' + Carry MEM (P _CT ↑. Cf _p lower) ← 0 MAR lower ← MAR lower + 1 MAR upper ← MAR upper + Carry MEM (P _CT ↑. Cf _p upper) ( 9) OC ₁ ← 0 R9 ← 0 (10) Termination flag (delimiter) transmission instruction Execute termination flag transmission instruction directly from μIR to line terminal #i. (11) Release of the cell, registration to the cell Q Same as step 8. (12) Release of cell pointed to by P ⁱ _HS , registration in empty cell Q

[Table] (13) Is P _p = 0? If Yes, go to step 15. Execute R11 = R12 (logical OR). Test result, if 0, jump to step 15. (14) P ⁱ _HS ←P _p

[Table] (15) P ⁱ _HS ←0, P ⁱ _TS ←0

[Table] (16) Instruct to send out empty signal Directly instruct line terminal #i to send out empty signal from μIR. (17) Proceed to the next process As explained in detail in one embodiment above, the free data cells in the buffer area are collectively managed for all line terminals, and the allocation of free data cells to each line terminal is controlled. can be controlled. As a result, a so-called "common line allocation system" in which all line terminals share the buffer area has been achieved. As explained above, the buffer memory control method of the present invention has a configuration in which all line terminals commonly use the entire buffer area, so (1) there is no need to change the scanning frequency of the buffer area depending on the difference in line terminal speed; In addition, data can be read and written without referring to terminal speed information, which not only makes it easier to accommodate terminals with different speeds, but also reduces the impact of adding lines or changing accommodation, and (2) reduces the buffer area. Since all line terminals can be used in common, even if the traffic on a particular line is congested, it is sufficient as long as the total traffic on all lines is within the allowable range. Therefore, the size of the buffer area is estimated to be the sum of the average traffic handled by each line. In general, it is possible to accommodate more line terminals than the conventional individual line allocation method.
Effects such as this can be achieved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the outline of the configuration of the communication control device of the present invention, FIGS. 2 to 5 are diagrams showing the configuration and operation of the internal memory 9 of FIG. 1, and FIG. 6 is a block diagram showing the configuration of the communication control device of the present invention. The block diagrams of one embodiment of the control device, FIGS. 7 through 10, are flowcharts for explaining the operation of the device shown in FIG. 1...Communication control device, 2...Main processor,
3, 4, 5... line terminal, 6... input/output control unit,
7, 8... Line, 9... Internal memory, 11... Buffer area, 12, 13, 14, 15... Data cell, 20... Control area, 21, 22...
35... Data cell pointer, 36... Queue common to all lines, 49, 50, 51... Queue for each data unit, 60... Micro program memory, 61... Micro instruction register, 62...
Microprogram sequence control section, 63...
Arithmetic logic unit with built-in registers.

Claims (1)

[Claims] 1. In a buffer memory control method for a communication control device that accommodates multiple line terminals, empty data cells are sequentially extracted from a buffer area divided into equally sized data cells and from a group of empty data cells common to all lines connected by a chain. data input means for storing externally input data in empty data cells and further forming a queue for each line terminal in a chain; and a data input means for sequentially selecting non-empty data cells forming queues for each line terminal, a data output means for outputting the data held in the data cells, untying free data cells from the chain and returning them to the free data cell group, and each of the free data cell group common to the line and the queue for each line terminal A buffer memory control system comprising a control area for instructing the position of the next data cell to be taken out and the position of the next data cell to be added.