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JPS6138852B2 - - Google Patents
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JPS6138852B2 - - Google Patents

Info

Publication number
JPS6138852B2
JPS6138852B2 JP54070856A JP7085679A JPS6138852B2 JP S6138852 B2 JPS6138852 B2 JP S6138852B2 JP 54070856 A JP54070856 A JP 54070856A JP 7085679 A JP7085679 A JP 7085679A JP S6138852 B2 JPS6138852 B2 JP S6138852B2
Authority
JP
Japan
Prior art keywords
metal wiring
insulating film
wiring layer
layer
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP54070856A
Other languages
Japanese (ja)
Other versions
JPS55163846A (en
Inventor
Hiroo Sasaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP7085679A priority Critical patent/JPS55163846A/en
Publication of JPS55163846A publication Critical patent/JPS55163846A/en
Publication of JPS6138852B2 publication Critical patent/JPS6138852B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60Formation of materials, e.g. in the shape of layers or pillars of insulating materials

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)

Description

【発明の詳細な説明】 本発明は半導体装置の製造に於ける絶縁膜の化
学気相成長方法の改良に関す。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a chemical vapor deposition method for insulating films in the manufacture of semiconductor devices.

例えば集積回路等の半導体装置の製造に於い
て、素子形成の完了した半導体基板上に形成した
金属配線層上に絶縁膜を被着し、該絶縁膜上に更
に上層の金属配線を形成させる多層配線工程があ
る。
For example, in the manufacture of semiconductor devices such as integrated circuits, an insulating film is deposited on a metal wiring layer formed on a semiconductor substrate on which element formation has been completed, and an upper layer of metal wiring is further formed on the insulating film. There is a wiring process.

然して該多層配線工程等に於ける絶縁膜の形成
に際しては、一般にアルミニウム(Al)、アルミ
ニウム/シリコン(Al/Si)等の下層配線を完了
させたシリコン(Si)基板に、シラン(SiH4)或
るいはシラン+フオスフイシ(SiH4+PH3)を用
いて化学気相成長(CVD)法により二酸化シリ
コン(SiO2)或るいはりん珪酸ガラス(PSG)等
の絶縁膜を成長させる方法が行われている。
However, when forming an insulating film in the multilayer wiring process, silane (SiH 4 Alternatively, an insulating film such as silicon dioxide (SiO 2 ) or phosphosilicate glass (PSG) is grown by chemical vapor deposition (CVD) using silane + phosphorus (SiH 4 + PH 3 ). ing.

然し該CVD法に於いては、被成長基板が例え
ば10〜20分程度約400〜500℃の高温にさらされる
ために、被成長基板に形成されている下層配線層
のAlやAl/Siが再結晶を起こし、時間とともに
結晶粒が粗大化して金属配線層上に突起やホイス
カーが形成せしめられる。
However, in this CVD method, the substrate to be grown is exposed to a high temperature of about 400 to 500°C for about 10 to 20 minutes, so the Al and Al/Si in the lower wiring layer formed on the substrate to be grown are Recrystallization occurs, and the crystal grains become coarser over time, resulting in the formation of protrusions and whiskers on the metal wiring layer.

従来は上記のような状態でSiO2或るいはPSGの
絶縁膜を被着させていたため、前記突起やホイス
カーが絶縁膜上に突出したり、絶縁膜にひび割れ
やピンホールが発生して、該絶縁膜上に被着させ
る上層金属配線と前記絶縁膜下層の金属配線との
絶縁劣化を起こしたり、又上層金属配線の断線を
起こすというような問題があつた。
Conventionally, insulating films of SiO 2 or PSG were deposited under the conditions described above, resulting in protrusions and whiskers protruding onto the insulating film, cracks and pinholes in the insulating film, and damage to the insulating film. There have been problems such as insulation deterioration between the upper layer metal wiring deposited on the film and the metal wiring below the insulating film, and disconnection of the upper layer metal wiring.

本発明は上記問題点に鑑み下層の金属配線層に
突起やホイスカーを発生させることのない化学気
相成長(CVD)方法を提供する。
In view of the above problems, the present invention provides a chemical vapor deposition (CVD) method that does not generate protrusions or whiskers in the underlying metal wiring layer.

即ち本発明は半導体装置の製造に於いて、半導
体基板上に形成した金属配線層上に化学気相成長
により絶縁膜を形成するに際して、該絶縁膜の形
成に先立つて該金属配線層を予め電子ビームによ
り前記絶縁膜の気相成長温度より高い温度で熱処
理することを特徴とする。
That is, in the manufacture of semiconductor devices, when an insulating film is formed by chemical vapor deposition on a metal wiring layer formed on a semiconductor substrate, the metal wiring layer is previously exposed to electrons prior to the formation of the insulating film. The method is characterized in that the heat treatment is performed using a beam at a temperature higher than the vapor phase growth temperature of the insulating film.

以下本発明を図示実施例により詳細に説明す
る。
The present invention will be explained in detail below with reference to illustrated embodiments.

第1図乃至第4図は本発明の一実施例のプロセ
ス説明図である。
1 to 4 are process explanatory diagrams of an embodiment of the present invention.

本発明によれば、まず例えば半導体集積回路等
の製造に於いて本発明の方法は第1図に示すよう
に素子形成の完了したSi基板1の表面を覆うSiO2
膜2に電極窓3を形成させ、厚さ1〜1.5〔μ
m〕程度のAlはAl/Siによる下層金属配線層4
を形成させる。
According to the present invention, for example, in the production of semiconductor integrated circuits, etc., the method of the present invention first uses SiO 2 to cover the surface of a Si substrate 1 on which element formation has been completed, as shown in FIG.
An electrode window 3 is formed on the membrane 2 to a thickness of 1 to 1.5 [μ
m] of Al is the lower metal wiring layer 4 made of Al/Si.
to form.

次いで第2図に示すように該Si基板1を電子ビ
ーム露光装置の陽極5上に載置し、該基板の金属
配線層4に対して106〜107〔W/cm〕のエネルギ
密度を有する電子ビーム6を10-7〔sec〕程度の
極めて短時間照射し、金属配線層4の表層部を約
500℃程度に昇温し熱処理(アニール)する。こ
の結果第3図に示すように金属配線層4の表層部
に500Å程度の薄いAl又はAl/Siの再結晶7が形
成される。
Next, as shown in FIG. 2, the Si substrate 1 is placed on the anode 5 of an electron beam exposure device, and an energy density of 10 6 to 10 7 [W/cm] is applied to the metal wiring layer 4 of the substrate. The surface layer of the metal wiring layer 4 is irradiated with an electron beam 6 for a very short period of time of about 10 -7 [sec], and the surface layer of the metal wiring layer 4 is
Heat treatment (annealing) is performed by raising the temperature to approximately 500℃. As a result, as shown in FIG. 3, a thin Al or Al/Si recrystallization 7 of about 500 Å is formed on the surface layer of the metal wiring layer 4.

然して該アニールは極めて短時間になされるの
で、形成されるAl又はAl/Siの再結晶粒は非常
に微細である。このため該工程以降に熱処理が施
されても金属配線層に突起やホイスカーを発生さ
せることがない。
However, since the annealing is performed for a very short time, the recrystallized grains of Al or Al/Si formed are very fine. Therefore, even if heat treatment is performed after this step, no protrusions or whiskers will be generated in the metal wiring layer.

次に該Si基板1を減圧CVD装置内で、SiH4
PH3とを流しつつ約450℃で10分間程度加熱し、
第4図に示すようにSi基板1表面のSiO2膜2及び
金属配線層4の再結晶層7上に約1〔μm〕程度
の厚さにPSGからなる絶縁膜8を堆積させる。
Next, the Si substrate 1 is treated with SiH 4 in a low pressure CVD equipment.
Heat at about 450℃ for about 10 minutes while flowing PH 3 ,
As shown in FIG. 4, an insulating film 8 made of PSG is deposited to a thickness of about 1 [μm] on the SiO 2 film 2 on the surface of the Si substrate 1 and the recrystallized layer 7 of the metal wiring layer 4.

然して前記電子ビームによる金属配線層のアニ
ール温度は該気相成長の温度より高く設定されて
いるので、該気相成長中に金属配線層の再結晶が
進行することはなく、従つて大きな突起やホイス
カーのない金属配線層上に均一な絶縁膜の堆積を
行うことができる。
However, since the annealing temperature of the metal wiring layer by the electron beam is set higher than the temperature of the vapor phase growth, recrystallization of the metal wiring layer does not proceed during the vapor phase growth, and therefore large protrusions and A uniform insulating film can be deposited on a metal wiring layer without whiskers.

上記電子ビームアニールは、(1)金属の結晶構造
によらない、(2)所望のビーム面積を作ることがで
きる、(3)電子に与える加速エネルギーを変えるこ
とによりアニール深さのコントロールが出来る、
(4)パルス照射により瞬間アニールが可能である、
等の多くの利点を有するので、種々の金属に対し
て望みの深さのアニール層を形成することがで
き、又アニールにより結晶粒のコントロールや混
合金属に於ける組識の均一化促進等を行うことも
できる。
The above electron beam annealing method (1) does not depend on the crystal structure of the metal, (2) can create a desired beam area, and (3) can control the annealing depth by changing the acceleration energy given to the electrons.
(4) Instantaneous annealing is possible by pulse irradiation.
As it has many advantages such as, it is possible to form an annealed layer of desired depth on various metals, and annealing can control crystal grains and promote uniformity of structure in mixed metals. You can also do this.

従つて本発明の方法は前記実施例に限らず、上
記以外の各種金属或るいは合金からなる配線層上
に化学気相成長によりSiO2、PSG更には窒化シリ
コン(Si3N4)等の絶縁膜を堆積させる際にも適用
し得ることは勿論である。
Therefore, the method of the present invention is not limited to the above-mentioned embodiments, but can also be applied to SiO 2 , PSG, silicon nitride (Si 3 N 4 ), etc. by chemical vapor deposition on wiring layers made of various metals or alloys other than those mentioned above. Of course, this method can also be applied when depositing an insulating film.

以上説明したように本発明の方法によれば金属
配線層上に化学気相成長により絶縁膜を堆積させ
るに際して、金属配線層の再結晶により突起やホ
イスカーが発生することを防止できるので、絶縁
膜に再結晶金属の突きぬけやひび割れ、ピンホー
ル等を発生させることがなくなり、集積回路等の
半導体装置の製造歩留りや信頼度の向上に対して
極めて有効である。
As explained above, according to the method of the present invention, when an insulating film is deposited on a metal wiring layer by chemical vapor deposition, it is possible to prevent protrusions and whiskers from occurring due to recrystallization of the metal wiring layer. This eliminates the occurrence of penetration, cracks, pinholes, etc. in the recrystallized metal, and is extremely effective in improving the manufacturing yield and reliability of semiconductor devices such as integrated circuits.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図乃至第4図は本発明の一実施例の工程を
示す断面図である。 図に於いて、1はシリコン(Si)基板、2は二
酸化シリコン(SiO2)膜、3は電極窓、4は下層
金属配線層、5は電子ビーム露光装置の陽極、6
は電子ビーム、7は再結晶層、8は絶縁膜。
1 to 4 are cross-sectional views showing the steps of an embodiment of the present invention. In the figure, 1 is a silicon (Si) substrate, 2 is a silicon dioxide (SiO 2 ) film, 3 is an electrode window, 4 is a lower metal wiring layer, 5 is an anode of an electron beam exposure device, and 6 is an anode of an electron beam exposure device.
7 is an electron beam, 7 is a recrystallized layer, and 8 is an insulating film.

Claims (1)

【特許請求の範囲】[Claims] 1 半導体基板上に形成した金属配線層上に化学
気相成長により絶縁膜を形成するに際して、該絶
縁膜の形成に先立つて該金属配線層を予め電子ビ
ームにより前記絶縁膜の気相成長温度より高い温
度で熱処理する工程を有することを特徴とする半
導体装置の製造方法。
1. When forming an insulating film by chemical vapor deposition on a metal wiring layer formed on a semiconductor substrate, prior to forming the insulating film, the metal wiring layer is heated with an electron beam to a temperature lower than the vapor growth temperature of the insulating film. A method for manufacturing a semiconductor device, comprising a step of heat treatment at a high temperature.
JP7085679A 1979-06-06 1979-06-06 Manufacture of semiconductor device Granted JPS55163846A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7085679A JPS55163846A (en) 1979-06-06 1979-06-06 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7085679A JPS55163846A (en) 1979-06-06 1979-06-06 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS55163846A JPS55163846A (en) 1980-12-20
JPS6138852B2 true JPS6138852B2 (en) 1986-09-01

Family

ID=13443618

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7085679A Granted JPS55163846A (en) 1979-06-06 1979-06-06 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS55163846A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4305973A (en) * 1979-07-24 1981-12-15 Hughes Aircraft Company Laser annealed double conductor structure
JPS63146449A (en) * 1986-12-10 1988-06-18 Sharp Corp Manufacture of semiconductor device

Also Published As

Publication number Publication date
JPS55163846A (en) 1980-12-20

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