JPS6140140B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit device, and particularly to a method for manufacturing a semiconductor device having at least two types of semiconductor elements having mutually different electrical characteristics. For example, the present invention relates to a manufacturing method for forming a vertical transistor requiring high breakdown voltage characteristics and a lateral transistor requiring high current gain characteristics in the same semiconductor substrate.

For example, in a bipolar power IC (semiconductor integrated circuit), a small-signal horizontal transistor for input and a vertical power transistor for output are formed on the same semiconductor substrate, and the semiconductor region where each transistor is formed is isolated. They are often separated from each other by (separation) areas.

In the above power IC, in order to improve its output characteristics, it is necessary to increase the breakdown voltage (V _CBO , V _CEO ) of the power transistor. As a means of increasing the withstand voltage of such a transistor, (1)
Possible solutions include increasing the resistivity of the semiconductor epitaxial layer in which the transistor is formed, and (2) increasing the thickness of the semiconductor epitaxial layer to increase the base width or collector layer thickness. However, if a lateral transistor for small signals is formed in a semiconductor epitaxial layer that satisfies these conditions, the high frequency characteristics of this lateral transistor will deteriorate. The reason for this is that in lateral transistors, the semiconductor epitaxial layer is the base.As mentioned above, this is made thicker and its specific resistance is increased, which causes the base to expand and the resistance to increase.As a result, the high frequency characteristics of the lateral transistor deteriorate. .

In the present invention, we investigated a method for increasing the thickness and resistivity of the semiconductor epitaxial layer in the power IC described above, without deteriorating the high frequency characteristics of the lateral transistor formed in the semiconductor epitaxial layer. As a result, it is possible to satisfy the above requirements by changing the resistivity and thickness of the semiconductor epitaxial layer in individual regions in the manufacturing process of power ICs from semiconductor substrates. Although it is possible to configure the semiconductor device in this way, in that case, the number of steps will be significantly increased, which will increase the manufacturing cost, and if the number of steps is increased, it will be difficult to make the characteristics of the semiconductor element uniform. I can't.

Therefore, an object of the present invention is to provide a method for forming elements having different electrical characteristics by a simple method. For example, when forming a vertical transistor and a horizontal transistor in the same semiconductor substrate, (1) Increase the breakdown voltage of vertical transistors, (2)
The object of the present invention is to reduce the base spread resistance of a lateral transistor, and (3) provide a manufacturing technology that simultaneously satisfies the above (1) and (2) without increasing the number of manufacturing steps.

The present invention will be specifically described below with reference to Examples.

FIG. 1 shows the manufacturing process for an example in which an NPN vertical transistor and a PNP lateral transistor are formed on the same p-type Si substrate according to the present invention.

(a-1) Prepare a p-type Si (silicon) substrate (wafer) with high resistivity, and prepare n ⁺ The mold buried layer regions 2 and 3 are formed by selective diffusion using an oxide film (not shown) formed by photoetching as a mask. In this case, Sb (antimony) is used as a donor to create the n ⁺ type impurity.

(a-2) A lower p ⁺ -type diffusion region 4 for an isolation region for separating the regions is formed on the p-type substrate 1 by selective diffusion. In this case, B (boron) is used as an acceptor that creates a p ⁺ type impurity.

(b) A lower n ⁺ type diffusion layer 5 for the collector extraction portion is formed in a part of the n + type buried region 2 of the region, and at the same time, a lower n ⁺ type diffusion layer 5 for the base extraction portion is formed for the entire n ⁺ type buried region 3 of the region. An n ⁺ type diffusion layer 6 is formed. At this time, p (phosphorus) is used as the donor that creates the n ⁺ type impurity. This diffusion coefficient of p is the above-mentioned Sb
It is much larger than that of .

(c) A silicon epitaxial layer 7 containing a low concentration of n-type impurities is formed on the substrate on which the above layer is formed.
Form to a thickness of 25μ.

(d) An isolation upper p ⁺ type diffusion region 8 is formed in the epitaxial layer 7 and connected to the lower p ⁺ type diffusion region 4 to form an isolation region.

(e) Perform upper n ⁺ type diffusion in each epitaxial layer 7 to form a collector extraction portion 9 connected to the n ⁺ type diffusion layer 5 in the region, and connected to the n ⁺ type diffusion layer 6 in the region A base extraction portion 10 is formed.

(f) P ⁺ -type diffusion is performed in each region, and the base 11 of the vertical transistor is formed in the region, and the emitter 12 and collector 13 of the lateral transistor are formed in the region. B (boron) is used as an acceptor for p ⁺ type diffusion at this time.

After this, an emitter 14 is formed in the area by n ⁺ type diffusion, a window is opened in the surface oxide film 15 by contact photoetching as shown in FIG. Each element is completed by etching unnecessary parts and forming electrodes B ₁ , B ₂ , C ₁ , C ₂ , E ₁ , and E ₂ connected to the base, collector, and emitter of each region.

According to the present invention as described in the embodiments above, the object can be achieved and the effects can be obtained for the following reasons.

(1) In a conventional lateral transistor, as shown in FIG.
Since the n ⁺ type buried layer 3 is formed with a sufficiently wide interval between the n + type buried layer 3 and the emitter 13 in order to improve the breakdown voltage characteristics of the power transistor, the base spread resistance (r _bb ′) is r _bb ′=R ₁ +R ₂ +R ₃ (1) Here R ₁ is the base operating part B ₁
R ₂ is the resistance in the lateral direction in the ^{n + type} buried layer 3, and R ₃ is the resistance from the n ⁺ type buried layer 3 to the n ⁺ type base extraction portion 10. The specific resistance of the n-type epitaxial layer 7 is 5 to 6 Ωcm, and the specific resistance of the n ⁺ type buried layer is 0.004 Ωcm.
and the thickness of the epitaxial layer is 20μ.

Therefore, r _bb ′≒R ₁ +R ₃ ≫R ₂ (2), and the main part of the base spreading resistance is related to the impurity concentration and thickness of the n-type epitaxial layer.

On the other hand ^, in the lateral transistor according to the present ^invention , as shown in FIG. Since the emitter 13 is configured to be sufficiently close to the n ⁺ type diffusion layer 6, the base spreading resistance (r _bb ′) in this case is r _bb ′≒R ₄ +R ₅ +R ₆ (3). revealed. Here R ₄ is the base operating part B ₁
and the resistance up to the n ⁺ type diffusion layer 6, R ₅ is the lateral resistance (combined value) of the n ⁺ type diffusion layer 6 and the n ⁺ type buried layer 3, and R ₆ is the resistance from the n ⁺ type diffusion layer 6 to the n ⁺ This is the resistance up to the mold base extraction part 10. The specific resistance of the n-type epitaxial layer 7 is 5 to 6 Ωcm, and the specific resistance of the n ⁺ type diffusion layer 6 and the n ⁺ type buried layer 3 is
It is 0.004Ωcm. In this _case , due to the _{presence of the} n ⁺ -type diffusion layer 6 _, in contrast to the case shown in _FIG . _bb ′≒R ₄ ≫R ₅ +R ₆ (4) r _bb ′ can be made extremely small.

High frequency characteristics FM is generally expressed as FM = ft/(C _c × r _bb ′) (where ft: cutting frequency, C _c : collector capacitance), and since r _bb ′ is small as mentioned above, FM improves. do.

(2) On the other hand, in a vertical output transistor, since the n-layer (epitaxial layer) is thick, a sufficiently high breakdown voltage can be achieved.

(3) In step (b), when forming the n ⁺ type diffusion region 5 for the collector extraction portion of the output vertical transistor, the formation of the n ⁺ type diffusion region 6 of the horizontal transistor is performed at the same time. The number does not particularly increase.

(4) By forming the collector extraction part in a ring shape, it is possible to isolate the vertical npn transistor from the outside and prevent parasitic transistor effects.

In addition to the embodiments described above, the present invention can be implemented in the following embodiments.

(1) In the lateral pnp transistor, the n ⁺ buried layer 3 is not formed. In other words, using p (phosphorus)
Only n ⁺ type diffusion layer is used.

(2) Form the upper base extraction portion diffusion layer of the lateral PNP transistor into a ring shape.

The present invention is mainly applicable to power ICs, especially when horizontal transistors and vertical transistors are formed on the same semiconductor substrate. It is also effective when applied to the formation of etc. Furthermore, the present invention can be applied to so-called self-isolation in which the conductivity type of the epitaxial layer is made the same as that of the substrate and the elements are isolated by a collector buried layer.

[Brief explanation of the drawing]

1A to 1F are process diagrams showing one embodiment of the manufacturing method according to the present invention, FIG. 2 is a vertical cross-sectional view of the finished product, and FIGS. FIG. 3 is a principle explanatory diagram showing base spreading resistance in a manufactured device. 1...p-type silicon substrate, 2, 3...n ⁺ type buried layer (region) 4...lower p ⁺ type diffusion region for isolation, 5...lower n for collector extraction part ⁺ type diffusion layer, 6...n ⁺ type diffusion layer for base extraction portion, 7...n type epitaxial layer, 8...upper p ⁺ type diffusion region for isolation, 9...n ⁺
Mold upper diffusion collector extraction section, 10...n ⁺ type upper diffusion base extraction section, 11...p type base, 1
2...p-type collector, 13...p-type emitter, 1
4...n ⁺ type emitter, 15...insulating film, C ₁ ,
B ₁ , E ₁ ...Each electrode in the area, C ₂ , B ₂ , E ₂
...Each electrode in the area.

Claims (1)

[Claims] 1. A method for manufacturing a semiconductor integrated circuit device, comprising forming a semiconductor layer having a substantially uniform impurity concentration distribution on a first conductivity type semiconductor substrate, and forming at least two semiconductor elements with different characteristics in the semiconductor layer,
An impurity of a second conductivity type is introduced into a region of the surface of the first conductivity type semiconductor substrate to form a first semiconductor region, and another region of the surface of the semiconductor substrate spaced apart from the first semiconductor region is introduced with impurities of a second conductivity type. A second semiconductor region is formed by introducing another impurity of a second conductivity type having a large diffusion coefficient, and a single semiconductor layer of a second conductivity type is formed on the surface of the semiconductor substrate on which the first and second semiconductor regions are formed. and by diffusing impurities of a second conductivity type into the semiconductor layer from each of the first semiconductor region and the second semiconductor region, a first semiconductor layer extending between the semiconductor layer and the semiconductor substrate is formed. forming a buried layer and a second buried layer, such that the distance from the surface of the semiconductor layer to the first buried layer is larger than the distance from the surface of the semiconductor layer to the second buried layer; A method for manufacturing a semiconductor integrated circuit device, characterized in that: