JPS6141080B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an inspection method for functional testing of an IC memory.

In IC memory function tests, address decoder failures, word line and digit line failures,
Furthermore, tests are applied to detect failures due to interference between memory cells, but among the above failure tests,
Particularly in tests for detecting failures due to interference between memory cells, test patterns vary depending on the semiconductor manufacturer. The reason is that IC
Various conditions such as mask manufacturing methods and diffusion techniques vary due to differences in manufacturing processes and how the internal circuits of IC memories are constructed. Therefore, a test pattern with a high failure detection rate is taken that corresponds to the manufacturing process, circuit configuration, etc. mentioned above. However, as a general means of detecting failures due to interference between cells, the stored information of one bit of any particular cell (cell of interest) is stored as the inverse information of the stored information of all remaining cells, and By alternately selecting the cell and other cells (field cells) based on a certain algorithm, it is possible to ensure that the stored information of the cell of interest does not become reversed information due to interference, or that the field cell mentioned above does not experience interference in the same way. The usual test pattern is to sequentially change the cell of interest and check whether the information is reversed or not.

However, in the fault detection test described above, when a defective cell is found, a memory section (hereinafter referred to as fail memory) with the same storage capacity as the IC memory under test (hereinafter referred to as MUT) is used to search for the defective cell. The address information generated from the pattern generator and applied to the MUT is applied in parallel to the fail memory, and when the judgment result is a failure, the failure information is stored in the fail memory, and this information is stored until all patterns are completed. The conventional method is to search for defective cells by repeating them, but the address of the defective cell detected by this method is the cumulative number of times the defective cell is selected in all test patterns. (logical sum) result, for example, especially in tests that look at the interference state between cells as described above, an address that is identified as a defective cell may be considered as a defective background that causes the cell to become the cell of interest. Is it defective when it is located, or is the cell of interest another cell and the cell itself identified as defective?
It is not easy to determine whether the defect occurs when it is located in a field cell, and analysts are forced to use other means to analyze the address of the defective cell. This cannot be done quickly, resulting in a huge loss of opportunity.

The present invention provides an inspection method that solves these problems and enables efficient failure analysis.

According to the inspection method according to the present invention, a program counter in a control memory section that stores a program for pattern generation in a microprogram pattern generator that generates an address pattern to be applied to the MUT, and a program counter that is the same as the above program counter. A register in which an arbitrary value can be set using the number of bits (hereinafter referred to as
The defect information is stored in the fail memory in the inspection device only when the test result is determined to be defective and the comparison result between the synchronization register and the program counter matches. The defective background of cells determined to be defective can be easily known. Furthermore, input information to the comparison matching circuit is selected not only from the program counter information but also from expected information and background register information of the address information generation unit (for example, a register pointing to the address of the cell of interest). If this is possible, the analysis of the defect background described above can be performed even more easily.

As described above, the effects of the inspection method according to the present invention are as follows:
The advantage is that it is possible to easily analyze the address of a defective cell during a failure detection test of an IC memory and the background of address information generation for the occurrence of the defective cell.

A specific example of the inspection method according to the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the inspection method according to the present invention, in which address information generated from the address generation section 6 of the microprogram pattern generator 1 is
Apply to MUT10 and fail memory 1 at the same time.
1 in parallel, and MUT is applied by the judgment circuit 13.
The output signal of the pattern generator 1 is compared with the expected information from the expected pattern generating section 7 of the pattern generator 1, and when the result is a mismatch (defective), the write signal generating circuit 12
At this time, a failure information write signal is generated to the fail memory 11. At this time, the output signal of the program counter 3 that controls the address designation of the control memory section 2 that stores the pattern generation program in the pattern generator 1 is generated. The multiplexer circuit 8 selects any one set of expected information from the background register 5 of the address pattern generating section 6 and the expected pattern generating section 7, and uses the preset synchronization information before running the test pattern. The register 9 is compared with the comparison circuit 14, and when they match, a synchronization signal is generated, and the judgment circuit 1
Only when the mismatch signal from 3 and the synchronization signal occur simultaneously, the defect information write signal generation circuit 12
generates a write signal, writes defective information to the memory cell of the fail memory 11 corresponding to the address of the defective cell of the MUT, repeats this series of operations until all patterns are completed, and confirms the stored information of the fail memory 11 at the time of analysis. By this,
It is possible to find the address of a defective cell in the IC memory under test. For example, when analyzing the address of a defective cell in a test pattern (generally called a PINGPONG pattern) such as the one shown in the flowchart in Figure 2 or the model cell in Figure 3, the current cell of interest is When looking at the interference received, it is only necessary to synchronize so that writing to the fail memory is possible only when the target cell is read, and by this method, it is possible to write to the fail memory only when the target cell is read.
Figure 4 shows an example of a defect map as a result of inspecting the MUT.

Conversely, FIG. 5 shows a defect map obtained in synchronization when the field cells are read.

With conventional inspection methods, it is not possible to obtain a defect map by focusing only on the cell of interest or only on the field as described above, and when testing a MUT with defective cells as described above using conventional inspection methods, the defects shown in Figure 6 are detected. As shown in the map, the defect map is a superimposition of the interference defects experienced during the focused cell (Figure 4) and the interference defects experienced during the field cell (Figure 5), and it is clear that the ease of analysis is different from this inspection method. be.

[Brief explanation of the drawing]

Figure 1 is an inspection block diagram based on this occurrence, Figure 2 is a flowchart showing the generation of interference test patterns between memory cells, Figure 3 is a cell model of the flowchart in Figure 2, and Figure 4. FIG. 5 is a diagram showing an example of a defect map obtained by the present inspection method, and FIG. 6 is a diagram showing an example of a defect map obtained by the conventional inspection method. 1 is a test pattern generator, 2 is a control memory section, 3 is a program counter, 4 is a decoder, 5 is a background register that contributes to address information generation, 6 is an address information generation section, 7 is an expected information generation section, and 8 is an expected information generation section. Multiplexer, 9 is a synchronization information register, 10 is an IC memory under test, 11 is a fail memory, 12 is a failure information write signal generation circuit, 13 is a judgment circuit, 14 is a comparison circuit, 15 is a cell of interest, 16 is a field cell, 17 is a The fail memory has a memory capacity of 64 bits, and 18 indicates a defective cell.

Claims (1)

[Claims] 1. In a method for analyzing the address of a defective cell in an IC memory under test, address information applied to an address terminal of the IC memory under test is also applied in parallel to a storage unit in a test device that stores judgment results for the IC memory under test. a program counter of a program pattern control memory in which test pattern information generated by application to the program counter is stored; and a register that can preset the count position of the program counter in order to extract the execution position of the program counter. are compared during inspection execution, and only when the judgment result is defective and the comparison results match, failure information is written in the storage section corresponding to the address of the IC memory under test, and the storage section is written at the time of failure analysis. An IC memory inspection method that makes it possible to analyze in what address generation history a defective cell occurred by reading memory information.