JPS6141142B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device, and particularly to a semiconductor storage device (memory) configured by connecting two Esaki (tunnel) diodes in series.

[Technical background of the invention]

In Figure 1, two Esaki diodes D ₁ and D ₂ with the same characteristics are connected in series between terminal 1 and ground, electrode 2 is provided at the connection point c, and a voltage of V _DD is applied to terminal 1. This shows a 1-bit static memory element.

In this memory element, if the value of the voltage V _DD applied to the terminal 1 is set near the valley voltage of the Esaki diodes D ₁ and D ₂ , the current I flowing through each of the Esaki diodes D ₁ and D ₂ and the potential V at the connection point c The relationship with _C is shown in Figure 2. Therefore, connection point c
If electrode 2 is not connected to the external circuit,
There are stable points A ₁ , A ₂ , and A ₃ .

Therefore, after fixing the potential V _C of the connection point c (electrode 2) near the potential V _A1 , V _A2 or V A3 of the stable point A ₁ , A ₂ or A ₃ by an external circuit, the potential V C of the connection point _c (electrode 2) When , the memory element maintains the stable state of A ₁ , A ₂ or A ₃ and writing has been performed. Further, when the potential V _C at the connection point c is detected by an external circuit, reading is performed. In particular, by using the stable points A ₁ and A ₂ , a low current 1-bit static memory can be obtained.

The above technique is considered by the applicant. By the way, the above memory element is manufactured by connecting two single Esaki diodes D ₁ and D ₂ and has never been formed as an integrated circuit. As an integrated circuit of this, a structure as shown in FIG. 3 can be considered. The memory element shown in FIG. 3 has two Esaki diodes D ₁ and D ₂ formed on a semiconductor (silicon) substrate 11 of one conductivity type, for example, P type, with an insulating layer (field oxide film SiO ₂ ) 12 in between. It is something. The Esaki diode _D1 has a thin island-shaped semiconductor layer with a highly doped P-type region 13 and a highly doped N-type region 13.
The type regions 14 are formed adjacent to each other, and the Esaki diode _D2 is also formed by forming a highly doped P-type region 15 and an N-type region 16 adjacent to each other in a thin island-shaped semiconductor layer. and Esaki diode
The N-type region 14 of D ₁ and the P-type region 15 of Esaki diode D ₂ are formed on the insulating layer 12 by a conductive layer, for example.
They are connected by an Al (aluminum) wiring layer 17.

[Problems with background technology]

However _, in the memory element having the structure as shown in _FIG .
A PN junction is formed. Therefore, the PN junction diodes (parasitic diodes) 18 and 19 are connected in parallel to the Esaki diodes D ₁ and D ₂ , and as a result, the valley point current in Fig. 2 increases and the power consumption increases. . Further, a junction capacitance C formed between the semiconductor substrate 11 and the N-type regions 14 and 16 is connected in parallel to the PN junction diodes 18 and 19, and the junction capacitance C and the wiring resistance R are connected in parallel. The operating speed of the memory is slowed down by the time constant τ=CR determined by .

[Purpose of the invention]

This invention was made in view of the above circumstances.
The purpose is to provide an integrated semiconductor device that can achieve high operating speed with low power consumption by preventing the generation of parasitic diodes and junction capacitance.

[Summary of the invention]

This invention forms two Esaki diodes connected in series in the same direction on an insulating substrate.

[Embodiments of the invention]

A first embodiment of the present invention will be described below with reference to the drawings. In FIG. 4, reference numeral 21 denotes an insulating substrate, such as a sapphire substrate, on which a thick field oxide film (SiO ₂ ) 24 having openings 22 and 23 is formed. In the openings 22 and 23, island-shaped thin semiconductor layers such as silicon layers 25 and 26 are formed, respectively. This silicon layer 25 has a P-type region 27 with a high concentration, for example, an impurity concentration of 1×10 ¹⁹ /cm ³ or more, and an N-type region 28 with a high concentration, for example, an impurity concentration of 1×10 ¹⁹ /cm ^{3 .}
are formed adjacent to each other, and similarly in the silicon layer 26, a heavily doped P-type region 29 and a heavily doped N-type region 30 are formed.
are formed adjacent to each other. Then, the N-type region 28 of one silicon layer 25 and the other silicon layer 2
Between the P-type region 29 of 6 and the silicon layer 25, 2
They are electrically connected by a conductive layer such as an Al wiring layer 31 provided on the field oxide film 24 between the two. The silicon layer 25 on which the PN junction is formed corresponds to the Esaki diode _D1 in FIG. 1, the P-type region 27 is connected to the _VDD power supply, and the silicon layer 26 corresponds to the Esaki diode _D2. , N-type region 30 is grounded.

In a memory element with such a structure, since the two Esaki diodes D ₁ and D ₂ are each formed on the insulating sapphire substrate 21, unnecessary parasitic diodes as shown in FIG. Also, the junction capacitance connected in parallel to this does not occur. Therefore, compared to the structure shown in FIG. 3, the valley point current of the Esaki diode is smaller, power consumption is reduced, and operating speed is increased.

Next, an example of a method for manufacturing the above memory element will be described. First, a thin silicon layer is formed on the sapphire substrate 21 by, for example, CVD (Chemical Vapor Daposition), and then a nitride film (Si ₃ N ₄ film) is formed on this silicon layer by CVD. And this nitride film Esaki diode
When parts other than the regions where D ₁ and D ₂ are to be formed are etched away and thermal oxidation is performed using the remaining nitride film as a mask, thin island-shaped silicon layers 25 and 26 are formed together with the thick field oxide film 24. . next,
After removing the nitride film, a portion of each of the silicon layers 25 and 26 is doped with a P-type impurity, such as boron, to form highly concentrated P-type regions 27 and 29, and further adjacent to these P-type regions 27 and 29. The N-type regions 28 and 30 are doped with an N-type impurity, such as phosphorus, respectively. Finally, silicon layer 2
5 N-type region 28 and silicon layer 26 P-type region 2
An Al wiring layer 31 is formed by vapor deposition on the field oxide film 24 between the oxide film 9 and the oxide film 9 to connect the two.

FIG. 5 shows a second embodiment. In the first embodiment, two silicon layers 25, 2
6 was provided through an insulating layer, and the two were connected by an Al wiring layer 31 on the insulating layer.
In this embodiment, both are provided adjacent to each other, and the N type region 28 of the silicon layer 25 and the P type region 29 of the silicon layer 26 are directly connected.

With such a structure, the operation is similar to that of the first embodiment, but the degree of integration is improved compared to the first embodiment.

Although the first and second embodiments have been described using sapphire as the insulating substrate, the present invention is not limited to this, and other insulating materials such as silicon oxide (SiO ₂ ) may be used. In addition to silicon, germanium Ge, gallium arsenide GaAs, and gallium phosphorus can be used as a thin semiconductor layer on an insulating substrate.
GaP, gallium arsenide phosphorus GaAsP, gallium aluminum arsenide GaAlAs, etc. may also be used. In particular, the use of gallium compounds allows the valley point potential of the Esaki diode to be around 1V (0.4V for silicon), making it possible to create memory elements that are more resistant to noise.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to prevent the generation of unnecessary parasitic diodes and junction capacitances, so the valley point current of the Esaki diode is small, and power consumption can be reduced and the operating speed is improved. , it is possible to provide a semiconductor device suitable for integration.

[Brief explanation of the drawing]

Figure 1 is a circuit configuration diagram of a 1-bit memory element using an Esaki diode, Figure 2 is a characteristic diagram for explaining the operation of the circuit in Figure 1, and Figure 3 shows the conventional structure of the circuit in Figure 1. Sectional perspective view shown, No. 4
The figure is a cross-sectional perspective view showing the structure of a memory element according to one embodiment of the present invention, and FIG. 5 is a cross-sectional perspective view according to another embodiment of the present invention. 21...Sapphire substrate, 24...Field oxide film, 25, 26...Silicon layer, 27, 29
...P type region, 28, 30...N type region, 31...
...Aluminum wiring layer.

Claims (1)

[Claims] 1. An insulating substrate, and two island-shaped semiconductor layers formed on the insulating substrate, each having a highly doped P-type region and a highly doped N-type region adjacent to each other. A semiconductor device characterized in that a P-type region of one of the island-shaped semiconductor layers and an N-type region of the other island-shaped semiconductor layer are electrically connected. 2. The semiconductor device according to claim 1, wherein the P-type region of one of the island-shaped semiconductor layers and the N-type region of the other island-shaped semiconductor layer are formed adjacent to each other. 3. A patent in which the P-type region of one of the island-shaped semiconductor layers and the N-type region of the other island-shaped semiconductor layer are formed via an insulating layer, and the two are connected by a conductive layer provided on the insulating layer. A semiconductor device according to claim 1. 4. The semiconductor device according to any one of claims 1 to 3, wherein the insulating substrate is sapphire. 5 The island-shaped semiconductor layer is made of silicon, germanium, gallium arsenide, gallium phosphorus, gallium elemental phosphorus,
Claims 1 to 4 formed using at least one type of gallium aluminum arsenide
A semiconductor device according to any one of paragraphs.