JPS6141178B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital AGC system, particularly a digital AGC system used in a data transmission system.
Regarding AGC method.

Generally, in the case of a data modulator/demodulator that performs data communication using a telephone line, the received signal level is between 0 and 0.
It is specified as 40 dBm, and if the level is below -40 dBm, it is not determined to be a signal. Therefore, the presence or absence of a received signal is determined by comparing the received signal level with a certain threshold.

A general AGC circuit modulates a digital data signal into a voice band signal and sends it out as an analog signal on the transmitting side of a data transmission system using a telephone line, and when demodulating this analog signal on the receiving side, it depends on the line conditions etc. Since the level of this received analog signal has a large fluctuation range of 0 to -40 dBm, this analog signal is first subjected to AGC to maintain a constant level before demodulation is performed.

An analog AGC circuit is generally used as an AGC circuit to achieve this. but,
This analog AGC circuit has the disadvantages that it is difficult to reduce the scale of the circuit because its components are analog parts, and its characteristics are unstable and the characteristics vary widely during manufacturing, requiring adjustment. There is.

Therefore, digital AGC is implemented using a digital circuit that is configured with uniform gates and is easy to integrate into LSI.
This method has come into use in recent years.

A major problem in realizing this digital AGC method was how to digitize the analog input signal, which has a large fluctuation range of 0 to -40 dBm, into a digital signal using an analog-to-digital conversion circuit. Ta.

That is, converting an analog input signal into a digital signal with the necessary precision without causing overflow.

For this reason, if the analog input signal is directly analog-to-digital converted, the number of bits becomes large, so an analog-to-digital conversion circuit with a large number of bits is required, which becomes very expensive.

Therefore, in order to correct this, for example, a companding type analog-to-digital converter circuit may be used, or a variable operational amplifier may be used in the front stage of a linear analog-to-digital converter circuit to convert the variable operational amplifier depending on the level of the analog input signal. The gain of the converter is roughly switched to reduce the range of variation in the input level of the analog input signal supplied to the analog-to-digital conversion circuit.

In this way, the general digital AGC method first digitizes the analog input signal by using the analog-to-digital conversion circuit as described above, and then converts it into AGC through digital processing.
It became possible to apply

The conventional digital AGC method consists of an analog-to-digital conversion circuit that converts an analog input signal and outputs a digital signal, and a long-term average value of the digital signal, which is held when the digital signal is interrupted for a short period of time. a level detection circuit that generates an average value signal that is set to an initial value when there is a time break; a multiplier generation circuit that generates a multiplier signal according to the average value signal; and a multiplier generator that multiplies the digital signal and the multiplier signal. and a multiplier that generates a digital output signal.

An example of a conventional digital AGC method will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an example of a conventional digital AGC method. An analog input signal Sin applied to an input terminal 1 is digitized by an analog-to-digital conversion circuit 3 and multiplied by a multiplier 4 to produce a digital output signal. It is output from output terminal 2 as Sout. Here, the analog-to-digital conversion circuit 3 is for converting the analog input signal Sin in the range of 0 to -40 dBm into a digital signal a that does not cause overflow and has a sufficient S/N ratio due to quantization noise. It is. The level detection circuit 5 rectifies this digital signal a, calculates its average value, and outputs it as an average value signal b. This average value signal b is compared with a reference level in a multiplier generating circuit 6, and as a result, when this average value signal b is smaller than the reference level, the magnitude of the multiplier signal c supplied to the multiplier 4 is increased according to the difference. If the difference is greater than the reference level, the magnitude of the multiplier signal c supplied to the multiplier 4 is reduced in accordance with the difference.

In this way, the analog input signal Sin
AGC is applied, and a digital output signal Sout to which AGC is applied is obtained at output terminal 2. Furthermore, when the analog input signal Sin rises, the digital output signal Sout rises quickly, and in a steady state, the multiplier signal c supplied to the multiplier 4 is This is done so that the magnitude does not change, that is, the average level of the digital output signal Sout does not change. That is, the smoothing time constant of the level detection circuit 5 is made small when the analog input signal Sin rises and becomes large when the steady state is reached.

This digital AGC method is similar to conventional analog except for the analog-to-digital conversion circuit 3.
It is a digital version of the AGC circuit, and like analog AGC circuits, it has some drawbacks.

The first drawback is that it is difficult to control the rising edge of the analog input signal Sin. In other words, in the conventional analog AGC circuit, the analog input signal Sin
(i.e., the time from the fall to the rise of the analog input signal Sin)
For example, when there is a long disconnection of 20 msec or more, the smoothing part in the level detection circuit 5 is cleared and the initial value is set at the rise of the analog input signal Sin (in the analog AGC circuit, this corresponds to the discharge of the capacitor charge). ), and by shortening its time constant, the rise of the digital output signal Sout was made faster. Also, conversely, when it is short,
For example, a short interruption of 20 msec or less is regarded as an instantaneous interruption of the analog input signal Sin, and the control at the rise time as described above is not performed, and the average value signal c
is held and outputted one by one until it starts up.
If such control is performed, the following problems will occur. In other words, during polling, etc., because the time during which the analog input signal Sin is disconnected is short, even though the analog input signal Sin is input at a different level from the previous time, it is mistakenly regarded as a momentary interruption. The rise of the digital output signal Sout becomes extremely slow. And vice versa,
When there is a long momentary interruption in the analog input signal Sin, the level fluctuation of the digital output signal Sout becomes large because the time constant of the smoothing section in the level detection circuit 5 is short, and it takes a long time for the digital output signal Sout to stabilize. It will take time.

The second drawback is that the analog input signal Sin has a wide variety of types and the rise time is shortened. This is because in recent years, each circuit within a data modulation/demodulation device has come to be constructed using a microprocessor, etc.
It became possible to handle signals of various modulation methods with a single device, and the digital AGC method also needed to be compatible with various analog input signals Sin. Analog input signal Sin before transmitting
A training signal is sent out to indicate that the values are different. This training signal is a reference for adjusting the gain to remove distortions such as frequency distortion and group delay distortion, so it is a specific test sequence, that is, a signal consisting only of several predetermined frequency components. Initial training of the demodulator is performed using the training signal. In recent years, there has been a demand for the initial training time to be as short as possible in order to improve service efficiency, and therefore it is desirable that the digital AGC circuit placed before the demodulator also start up as soon as possible.

However, in the conventional digital AGC method, the level detection circuit outputs an average value signal as the long-term average value of the digital signal, and this average value signal is held when the interruption occurs for a short time, but when the interruption occurs for a long time. Sometimes it is set to the initial value, so when the analog input signal is input as a continuous signal after a long interruption, the average value signal has become the initial value, so the long-term average value cannot be taken. As a result, the level fluctuates until a long-term average value is taken, which requires a long stabilization time for the digital output signal, and also causes the analog input signal to oscillate after a short period of time. , when signals of different levels (including signals of different types) are input, the average value signal is maintained, so even though the first input signal and the next input signal are different, , and the average value is output as the same, so it does not become a regular output signal until the influence of the initial input signal disappears. Therefore, the training signal supplied to the demodulator is also not a regular signal. Therefore, the training signal needs to be supplied over a long period of time, and the initial training time is therefore also long.

Therefore, the conventional digital AGC method has the disadvantage that the stabilization time of the output signal and the initial training time are long.

An object of the present invention is to provide a digital AGC method that can shorten the stabilization time of an output signal and shorten the initial training time.

The digital AGC method of the present invention includes an analog-to-digital conversion circuit that converts an analog input signal and outputs a digital signal, and a training detection signal that is a long-term average value of the digital signal and is held when the digital signal is disconnected. a level detection circuit that generates a first average value signal whose initial value is set when the digital signal is supplied, and a second average value signal that is a second average value indicating a short-time average of the digital signal; a multiplier generating circuit that generates a multiplier signal according to the average value signal of the multiplier signal; a multiplier that generates a digital output signal by multiplying the digital signal and the multiplier signal;
and a training detection circuit that generates the training detection signal when the training signal is detected based on the average value signal.

Furthermore, the digital AGC method of the present invention is configured to include a delay circuit for delaying the digital signal and supplying the delayed digital signal to the multiplier and the training signal detection circuit.

That is, the digital AGC method of the present invention is
An analog-to-digital conversion circuit that appropriately digitizes an analog input signal to be subjected to AGC;
a delay circuit that receives the output of the analog-to-digital conversion circuit as an input; a multiplier that uses the output of the delay circuit as a first input; a level detection circuit that has one output and a second output that is the average level of the analog input signal Sin over a long period; and a multiplier generation circuit that calculates the ratio of the reference level Th to the second output of the level detection circuit. a training signal detection circuit that takes the first output of the level detection circuit as a first input, takes the output of the pre-AGC circuit as a second input, and detects whether the second input is a training signal; By using the output of the multiplier generating circuit as the second input of the multiplier, AGC is applied to the analog input signal as the output of the multiplier.
is a digital AGC circuit that obtains a digital output signal applied with the level detection circuit changes its operation when a certain sequence is detected by the sequence detection circuit; and the transmission mode of the analog input signal from the outside. The level detection circuit is configured to receive information regarding the level detection circuit, etc., and change its operation accordingly.

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 2 is a block diagram showing one embodiment of the present invention. Analog input signal applied to input terminal 1
Sin is properly digitized by the analog-to-digital conversion circuit 3 and output as a digital signal a. This digital signal a is sent to the delay circuit 7,
It passes through the multiplier 4 and is outputted from the output terminal 2 as a digital output signal Sout. Here, the digital signal a, which is the output of the analog-to-digital conversion circuit 3, is also input to the level detection circuit 5', and the level of the analog input signal Sin is detected by rectification and smoothing. An average value signal b and a second average value signal b' which is a short-time average value are output. The ratio of this average value signal b to a reference level is determined in a multiplier generating circuit 6 composed of a divider or a coefficient ROM, etc.
It is output as a multiplier signal c. This multiplier signal c is input to the second input of the multiplier 4, and multiplied by the digital signal a' obtained by being delayed by the delay circuit 7. Therefore, the analog input signal Sin
AGC is applied to the output terminal 2, and the AGC-applied digital output signal Sout is obtained from the output terminal 2. Here, the level detection circuit 5' is constructed as shown in an example shown in FIG. That is, the digital signal a is rectified by the rectifier circuit 903 and then sent to the average value detection circuit 904.
The average value is determined by . However, the average value detection circuit 904 is constructed as shown in the example shown in FIG. 4, and the number of stages N thereof is, for example, 32 stages.

Now, assuming that the analog input signal Sin is in a steady state, the digital signal a is also in a steady state, and the switch 907 is connected to the average value detection circuit 9.
It is closed once every N times of output of 04. This corresponds to the fact that the average value detection circuit calculates the N-point sample average. Thus adder 90
9, 911, a multiplier 910, and a one-stage shift register 908. As an output of the low frequency circuit, the average level of the analog input signal Sin is outputted from an output terminal 902 as an average value signal b. The multiplier of multiplier 910 is given by control circuit 905, but is set to a very small value in a steady state, and the time constant of this low frequency circuit is a sufficiently large value.

Here, the level of the analog input signal Sin is -
When the signal becomes lower than 40 dBm and the signal is turned off, the control circuit 905 compares the output of the average value detection circuit 904 with a predetermined threshold level and learns that the analog input signal Sin has turned off. Fix the switch 907 in the open state. After that, when the level of the analog input signal Sin increases again and becomes -40 dBm or more, the control circuit 905 compares the output of the average value detection circuit 904 with a certain predetermined threshold level, thereby increasing the level of the analog input signal Sin. Upon noticing the appearance of , the system shifts to the steady-state operation described above.

By doing this, if the disconnection state is a momentary interruption, the low frequency circuit will stop operating only during the disconnection state, and the average level of the analog input signal Sin before the disconnection state will be shifted. Since it is held in the register 908, the average level output from the output terminal 902 hardly changes before and after the momentary interruption, and therefore the average level of the digital output signal Sout obtained at the output terminal 2 also does not change.

Therefore, when the analog input signal Sin has a momentary interruption, the digital signal also has a momentary interruption. In this case, the signal level does not change, so the previous level is maintained during the instantaneous interruption, so after recovery, the AGC rises. Doesn't require time.

Next, we will discuss the case where another signal with a different average level is input after the disconnection state.

The second average value signal b', which is a short-time average value, from the average value detection circuit 904 is input to the training signal detection circuit 8 shown in FIG. The digital signal a' from is passed through a band pass filter and the analog input signal is determined based on the output thereof and the average value signal b' from the average value detection circuit 904.
It is determined whether or not Sin is a training signal consisting only of predetermined frequency components, and if it is a training signal, a training detection signal d is output. The training signal is a predetermined data series sent before transmitting information, and since its spectrum is a line spectrum, it can be detected by a bandpass filter. The average value signal b' is used to check whether this line spectrum exceeds a reference value. When the training signal is detected and the training detection signal d is output, the cut-off state is eliminated, so the training detection signal d is sent from the training signal detection circuit 8 to the control circuit 905 shown in FIG. 3. When the control circuit 905 receives this training detection signal d, it closes the switch 906 only once. As a result, the value of the shift register 908 is cleared and set to the initial value, and the output of the average value detection circuit 904 is set to the shift register 908 as the initial value.

In other words, when the training signal is detected, the operation starts to rise, and since the appearance of the training signal indicates that it is a completely new and different signal, the average of the previously detected digital signal a is Ignore the level and find the level according to the new analog input signal Sin.

In this way, the average level of the new analog input signal Sin is obtained at the output terminal 902, and therefore the digital output signal Sout output from the output terminal 2 can rise quickly. The control circuit 905 also receives a transmission mode instruction signal I _IN regarding the transmission mode of the analog input signal Sin from the outside, and the magnitude of the multiplier signal c output from the multiplier 910 in accordance with the transmission mode instruction signal I _IN . change.

That is, the multiplier signal c from multiplier 910 typically corresponds to a steady state time constant. In the case of a signal with large level fluctuations, the multiplier signal c is selected to be very small, and conversely, in the case of a signal with almost no level fluctuations, the multiplier signal c is selected not to be so small, depending on the mode of the analog input signal Sin.

Further, in the case of a signal with a large distortion at the rising edge, control is performed such that the multiplier signal c is increased for a certain period of time after the rising edge, and thereafter is decreased. This is because the waveform and distortion of the analog input signal Sin, especially at the rising edge, vary depending on the transmission mode, so by setting the multiplier signal c from the multiplier 910 to an appropriate value at the rising edge. Appropriate control can be performed on the analog input signal Sin in various transmission modes.

Next, the effect of the delay circuit 7 will be explained. When the analog input signal Sin rises, the training signal is first detected in the training signal detection circuit 8 as described above, but for this purpose, the average level of the analog input signal Sin is required as well as the analog signal Sin. Therefore, a second average value signal b' which is a short-time average value from the average value detection circuit 904 in the level detection circuit 5' is used.
has a configuration, an example of which is shown in FIG. 4, and after the analog input signal Sin appears, the average value detection circuit 90
There is a delay of N stages of shift registers for the average value signal b' from 4 to rise. Therefore, a delay circuit 7 is used to cancel the delay. Therefore, the delay circuit 7 is composed of N stages of shift registers.

Next, another embodiment of the present invention shown in FIG. 5 will be described.

In FIG. 5, a demodulation circuit 9 is inserted between the output of the delay circuit 7 shown in FIG. 2, the multiplier 4, and the training signal detection circuit 8. Training signals can be detected. The demodulation circuit 9 was placed after the output terminal 2 in the embodiment shown in FIG. It is possible to move.

The digital AGC method of the present invention changes the function of the level detection circuit and adds a training signal detection circuit. The output signal can be stabilized because it can output an average value signal of This has the effect of shortening the initial training time as well as shortening the initial training time.

That is, the digital AGC method of the present invention is
Appropriate AGC can be applied to analog input signals in various transmission modes, and in addition to ensuring a faster start-up and higher compression ratio than conventional analog AGC circuits, it is also said to be unaffected by momentary interruptions. effective.

[Brief explanation of the drawing]

Fig. 1 is a block diagram for explaining the outline of a conventional digital AGC circuit, Fig. 2 is a block diagram showing an embodiment of the present invention, and Fig. 3 is a detailed diagram of an example of the level detection circuit shown in Fig. 2. FIG. 4 is a circuit diagram for explaining details of an example of the average value detection circuit shown in FIG. 3, and FIG. 5 is a block diagram showing another embodiment of the present invention. . 3... Analog-digital conversion circuit, 4... Multiplier, 5, 5'... Level detection circuit, 6... Multiplier generation circuit, 7... Delay circuit, 8... Training signal detection circuit, 903... Rectifier circuit , 904...
Average value detection circuit, 905... Control circuit, 906,
907... Switch, 908... Shift register, 909, 911... Adder, 910... Multiplier, 9... Demodulation circuit, Sin... Analog input signal, Sout... Digital output signal, a, a' ...digital signal, b, b'...average value signal, c...multiplier signal, d...training detection signal.

Claims (1)

[Claims] 1. An analog-to-digital conversion circuit that converts an analog input signal and outputs a digital signal, and a training detection signal that is a long-term average value of the digital signal and is held when the digital signal is disconnected. a level detection circuit that generates a first average value signal whose initial value is set when the digital signal is supplied, and a second average value signal indicating a short-time average of the digital signal; a multiplier generating circuit that generates a multiplier signal; a multiplier that generates a digital output signal by multiplying the digital signal and the multiplier signal;
a training signal detection circuit that generates the training detection signal when the training signal is detected based on the average value signal of the digital AGC method. 2. The digital AGC method according to claim 1, wherein the digital signal is delayed by a delay circuit and then supplied to the multiplier and the training signal detection circuit.