JPS6142336B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is an apparatus for converting an analog signal into a digital signal and recording and reproducing the signal.The present invention performs error correction and correction of the reproduced signal by performing parity check and dropout detection on data obtained by dividing digital data into several blocks. The purpose is to do so by:

Generally, when converting an analog signal to a digital signal for recording and playback, errors such as dropouts occur in the digital signal during playback, and when the digital signal is converted to an analog signal with the error included, the original analog signal An analog signal containing pulse noise that is significantly different from the original signal will be reproduced. Various correction methods are being considered for such errors. For example, there is a parity check method, but in this method, if there are multiple errors, the probability of overlooking the error increases. Furthermore, the system based on monitoring the reproduced digital signal has the disadvantage that it is susceptible to noise and is prone to malfunction. If we try to implement error detection and correction for multiple bits using error correction codes, redundancy will increase;
The disadvantage is that the number of recording bits increases and the effective recording density decreases.

In the present invention, dropout monitoring and parity checking of the reproduced digital signal are performed for each block of digital data, a single error in the block is corrected, and if the block contains multiple errors, the error occurs. This is intended to prevent pulse noise from being mixed into the reproduced analog signal by inserting previous digital data in place of digital data containing errors.

Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 shows an example of the configuration of a recording section that implements the present invention. The analog signal is converted into an analog-to-digital converter (A-D converter) 1, for example.
Converted to a 12-bit digital signal. This 12
The bit data is divided into, for example, 4 bits by the dividing circuit 2.
Divide the data into 3 blocks of data. Various methods can be considered for dividing 12 bits, but for example, consider dividing into 4 bits each starting from the most significant bit. The 4-bit data of each block is sent to the parity generation circuit 3 to form parity bits. This parity bit and 4-bit data form block data to be recorded. This is done by the recording data generation circuit 4.
It is. In FIG. 1, three blocks are shown to be executed in parallel, but the data divided by the dividing circuit 2 may be used to generate the above-mentioned recording data in series for each block. The 5-bit data from the recording data generation circuit 4 is sent in parallel to the modulation circuit 5, frequency modulated to two frequencies for each bit, and recorded in the recording device 6 in parallel. Here, the recording device 6 rearranges the sent modulated signals in a direction intersecting the traveling direction of the recording medium so that signals of the same group of data are not adjacent on the recording medium, and then records the signals. The modulation method is not limited to FM, but other methods such as phase modulation and NRZI can be considered. During recording, it is essential that each bit within a block be recorded in parallel, but blocks do not necessarily need to be recorded in parallel.

Next, an example of the configuration of the recording section shown in FIG. 1 during reproduction will be explained based on FIG. 2. The reproduction signal reproduced bit by bit in parallel from the recording device 6 is collected into blocks by a distribution circuit 7 and sent to a dropout detection circuit 8 and a demodulation circuit 9. The 5-bit data including demodulated parity bits is sent to a parity check circuit 10, where a parity check is performed. When an error is detected by this parity check, the information is transferred to the error correction circuit 11.
sent to. On the other hand, the dropout detection circuit 8 performs dropout detection for each bit in the data from the reproduced signal. The dropout detection method may be a known method such as detecting when the reproduced signal level falls below a predetermined level, or any other method.

As mentioned above, the dropout detection circuit 8 detects the presence or absence of a dropout for each bit, so that the circuit 8 can obtain information that a dropout has occurred and information about the position of the bit. If the number of dropouts is one per block, the output of the parity check circuit 10 simultaneously generates "error detection" information, so the error correction circuit 11 that receives this output detects the dropout detection circuit. Based on the dropout bit position information from 8, error correction is performed by inverting the bit at the position where the dropout occurred.

When the number of dropout bits is plural, the output of the parity check circuit 10 may or may not indicate error detection. Since error correction is impossible at this time, the error correction circuit 11 sends an error detection signal indicating that there are multiple errors in the block to the correction control circuit 1.
Send to 3. Next, the dropout detection circuit 8 indicates that a 1-bit dropout exists in the block, but the parity check circuit 1
If it is 0 and no error is detected, the dropout detection circuit 8 is malfunctioning, so the error correction circuit 11 sends out the data as is without correcting the error or sending out the error detection signal. Receiving the data from the error correction circuit 11, the correction circuit 12 combines three pieces of 4-bit data by removing the parity bit from the data of each block to restore 12-bit data, and performs digital-to-analog (D-A) conversion. to circuit 14.

The correction circuit 12 is composed of a register circuit, and sends the data from the three error correction circuits 11 to the digital-to-analog conversion circuit with the timing aligned using the clock reproduced by the clock reproduction circuit 15. By the way, if the signal indicates the presence of multiple errors from any of the three error correction circuits 11, it is necessary to maintain the 12-bit data as it was before the error occurred. A correction control circuit 13 is provided to realize this. This correction control circuit 13 includes an OR circuit that responds to one or more of the signals from the error correction circuit 11 provided for each block, and an output from the OR circuit that sends the clock from the clock recovery circuit 15 to the correction circuit 12. It consists of a gate circuit that gates the clock. When there is no signal from any error correction circuit 11, the clock is supplied to the correction circuit 12, and when there is a signal from any error correction circuit 11, the gate circuit does not supply the clock to the correction circuit 12. The above operation can be realized by Since the clock is supplied to the digital-to-analog conversion circuit 14 without being gated, when the clock is gated and stopped by the correction control circuit 13, the reproduced analog signal becomes a waveform holding the previous value. If there are no other errors or if error correction has been performed, a correct reproduced analog signal will be obtained. Digital
Since the output of the analog conversion circuit 14 is a staircase wave, the original analog signal can be obtained by passing this through the low-pass filter circuit 16.
The condition that causes an error due to multiple dropouts in a block does not continue for a long time and returns to normal within a few clocks. Also, the probability that such a situation will occur is very small. Therefore, even if the error is corrected by holding the previous value, it does not significantly affect the reproduced analog signal waveform.

In the above embodiment, if a block of data contains an error at one location, it can be corrected, so if the number of blocks is a, errors scattered at a locations can be corrected. This has improved error correction capability compared to a method in which data is divided into one block and a parity bit is provided. Because data is 1
If the data is divided into blocks, it is possible to correct only one error, but if the data is divided into a blocks and the bits of each block are distributed and recorded, it is almost impossible for the same block to contain multiple errors. This is because a number of errors can be corrected. Furthermore, according to the method of the present invention, even if errors are included in two or more locations, the value before the error is retained while the error continues. Waveform diagram of the reproduced analog signal at this time (D-
The output waveform of the A conversion circuit 14) is shown in FIG.

Figure 3 (A) shows the case where errors are not included in any block at two or more locations, and if data containing errors at two or more locations in any block continues during the period shown in (1), the block As shown in Figure 2, the waveform becomes significantly different from the waveform in A, and pulse noise is mixed in. At this time, with the method of the present invention, the value before the continuous error is held, resulting in the waveform shown in C, which does not differ greatly from the normal waveform A, and pulse noise does not occur. If the bits in a block are distributed and recorded, this situation in which it is necessary to maintain the previous value will almost never occur, and even if it does occur, the period will be very short, so the negative effect of correction will not appear. do not have.

As described above, according to the method of the present invention, dropout detection is performed for each bit and information on the presence or absence of a dropout and the position of the bit is used. Therefore, if the number of dropouts is one in one block, Error correction can be performed for one block by using only one parity bit. Furthermore, when recording M-bit data on a recording medium in a direction intersecting the direction of travel of the recording medium, it is divided into a blocks and the correctable unit (one correction unit) is made smaller.
Since the probability that the number of dropouts occurring within one correction unit will be two or more can be reduced, a high correction ability can be achieved with only one parity bit. In other words, in this method, it is possible to correct a bits (total when one bit is added to each block) by adding a parity bit, and generally an error correction code having a redundancy of a bits, such as a Hamming code, is used. Although the correction ability is a/2-1 bit, it has an excellent effect.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the recording section in one embodiment of the present invention, FIG. 2 is a block diagram of the reproducing section, and FIG.
The figure is a reproduction output waveform diagram. 1...A-D converter, 2...Division circuit, 3...
Parity check circuit, 4...Record data generation circuit, 5...Modulation circuit, 6...Recording device, 7...Distribution circuit, 8...Dropout detection circuit, 9...
Demodulation circuit, 10... Parity check circuit, 11
...Error correction circuit, 12...Correction circuit, 13...
Correction control circuit, 14...D-A conversion circuit, 15...
...Clock regeneration circuit, 16...Low pass filter circuit.

Claims (1)

[Claims] 1. Convert an analog signal to an M-bit digital signal, divide the M-bit digital signal into a blocks, add 1 parity bit to each block, make a (M+a)-bit digital signal, and convert each block into a Bits are recorded on a recording medium in a direction that intersects the traveling direction of the recording medium, and during playback, dropout detection for each bit and parity check are performed for each block. If an error is detected, one-bit error correction in the block is performed by inverting the data of the bit where the dropout was detected, and if multiple dropouts are detected in any block, the digital data of (M+a) bits is corrected. A signal error detection and correction method which assumes that a signal contains an error and replaces the reproduced digital signal with a correction signal created from the reproduced signal before the error occurs.