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JPS6142429B2 - - Google Patents
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JPS6142429B2 - - Google Patents

Info

Publication number
JPS6142429B2
JPS6142429B2 JP56186321A JP18632181A JPS6142429B2 JP S6142429 B2 JPS6142429 B2 JP S6142429B2 JP 56186321 A JP56186321 A JP 56186321A JP 18632181 A JP18632181 A JP 18632181A JP S6142429 B2 JPS6142429 B2 JP S6142429B2
Authority
JP
Japan
Prior art keywords
semiconductor element
inorganic material
semiconductor
organic
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56186321A
Other languages
Japanese (ja)
Other versions
JPS5886750A (en
Inventor
Kenzo Hatada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP56186321A priority Critical patent/JPS5886750A/en
Publication of JPS5886750A publication Critical patent/JPS5886750A/en
Publication of JPS6142429B2 publication Critical patent/JPS6142429B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • H10W74/10Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/121Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/701Tape-automated bond [TAB] connectors

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Description

【発明の詳細な説明】 本発明は半導体装置、特に半導体素子上の電極
に設けた金属突物と可撓性フイルム上に形成した
金属リードとを接合してなるいわゆるフイルムキ
ヤリヤ実装方式のパツケージングに関するもの
で、前記半導体素子の両面に有機又は無機材を介
して蒸着層を形成する事によつて、小型で信頼性
の高いフイルムキヤリヤ実装におけるパツケージ
ングを提供するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, particularly a so-called film carrier mounting type package in which a metal protrusion provided on an electrode on a semiconductor element and a metal lead formed on a flexible film are bonded. The present invention relates to packaging, and provides compact and highly reliable packaging in film carrier mounting by forming vapor deposited layers on both sides of the semiconductor element via an organic or inorganic material.

従来のパツケージングを施した半導体装置につ
いて第1図を参照して説明する。
A semiconductor device using conventional packaging will be described with reference to FIG.

先ず半導体素子1のアルミニウム配線からなる
電極上に真空蒸着法による例えばCr:1000Å,
Cu:5000Åを連続蒸着していわゆる多層膜のバ
リヤメタル層を形成する。次いで前記バリヤメタ
ル層上に選択的に電解メツキ法によりAuの突起
物2を10〜20μmの高さに設け、Auの突起物2
の周辺以外の不要となつた前記Cr〜Cu膜のバリ
ヤメタル層を除去する。このようにして前記半導
体素子上の電極にAu突起物が形成される。次に
ポリイミイド樹脂からなる厚さ125μmのフイル
ム3に前記半導体素子を挿入するための開孔部を
設け、次に例えば35μmのCu箔を貼りつけ、フ
オトリソグラフイ技術によつて前記半導体素子の
電極の位置に合致する如く前記Cu箔をエツチン
グ除去しCuリード4を形成し表面にSnを0.4μm
の厚さにメツキ処理する。このようにしてフイル
ムキヤリヤが出来上る。
First, Cr: 1000 Å, for example, is deposited on the electrode made of aluminum wiring of the semiconductor element 1 by vacuum evaporation.
Cu: 5000 Å is continuously deposited to form a so-called multilayer barrier metal layer. Next, Au protrusions 2 are selectively provided on the barrier metal layer with a height of 10 to 20 μm by electrolytic plating.
The barrier metal layer of the Cr--Cu film that is no longer needed except around the area is removed. In this way, Au protrusions are formed on the electrodes on the semiconductor element. Next, an opening for inserting the semiconductor element is provided in the film 3 made of polyimide resin with a thickness of 125 μm, and then, for example, a 35 μm Cu foil is pasted, and the electrodes of the semiconductor element are formed using photolithography technology. The Cu foil is etched away to form a Cu lead 4 that matches the position of
Plating process to a thickness of . In this way, a film carrier is completed.

前記半導体素子1上のAu突起物2に前記可撓
性フイルム3に設けた前記SnメツキしたCuリー
ド4を位置合せし、加圧しながら加熱すれば、
SnとAuの合金が形成され、前記Au突起物2とSn
メツキしたCuリードとは完全に接合されるもの
である。しかしこのままの状態では半導体素子が
露出しているから、雰囲気からの汚染に対して、
無防備であり、著しく信頼性が低い。
By aligning the Sn-plated Cu lead 4 provided on the flexible film 3 with the Au protrusion 2 on the semiconductor element 1 and heating while applying pressure,
An alloy of Sn and Au is formed, and the Au protrusion 2 and Sn
The plated Cu leads are completely bonded. However, in this state, the semiconductor elements are exposed, so they are susceptible to contamination from the atmosphere.
Unprotected and extremely unreliable.

このために前記半導体の周囲をシリコーン樹
脂、エポキシ樹脂5等で被覆するわけである。フ
イルムキヤリヤに実装された半導体素子1は第1
図に示した如くCuリード4によつて空中にぶら
さがつた状態であるから液状の前記シリコーン、
エポキシ樹脂で被覆することは困難である。例え
ば破線6で示した如くの被覆では、表面張力によ
り半導体素子1の中央部は厚くなるが周縁部は薄
くなつてまう。このためにこの薄くなつた周縁部
の樹脂から外気が浸入してしまい、半導体素子の
特性を劣化させるものであつた。したがつて、5
に示すように前記半導体素子1の全体を被覆する
必要があるが、この場合、シリコーン、エポキシ
樹脂が流動性を有するために、半導体素子1の周
囲に樹脂の流動性を止めるポリイミイドの片3を
形成する必要がある。前記ポリイミイドの片3に
よつて樹脂5はここで流れを止め一定の形状を有
することが出来るものである。
For this purpose, the periphery of the semiconductor is coated with silicone resin, epoxy resin 5, or the like. The semiconductor element 1 mounted on the film carrier is a first
As shown in the figure, the liquid silicone is suspended in the air by the Cu lead 4.
It is difficult to coat with epoxy resin. For example, with a coating as shown by the broken line 6, the central portion of the semiconductor element 1 becomes thicker due to surface tension, but the peripheral portion becomes thinner. For this reason, outside air infiltrates through the thinned peripheral resin, degrading the characteristics of the semiconductor element. Therefore, 5
As shown in the figure, it is necessary to cover the entire semiconductor element 1. In this case, since silicone and epoxy resin have fluidity, a piece of polyimide 3 is placed around the semiconductor element 1 to stop the fluidity of the resin. need to be formed. The polyimide piece 3 stops the flow of the resin 5 and allows it to have a certain shape.

ところが、こようなパツケージの方法では、樹
脂の被覆領域が半導体素子の周辺以上におよぶか
ら必然的に前記被覆した樹脂の厚さも厚くなつて
しまう。前記半導体素子1の厚さは、わずか0.3
〜0.5mmしかないのに、従来の方法によつて樹脂
を被覆すれば、全体の厚さな2mm前後の厚さにな
つてしまう。又、前記被覆して樹脂の面積も少な
くとも、前記半導体素子への端部から片側で1.5
mm以上にも拡がり、実装面積を大きくするもので
あつた。
However, in this packaging method, since the resin coating area extends beyond the periphery of the semiconductor element, the thickness of the resin coating inevitably increases. The thickness of the semiconductor element 1 is only 0.3
Although it is only ~0.5 mm, if it were coated with resin using the conventional method, the total thickness would be around 2 mm. Further, the area of the covering resin is at least 1.5 on one side from the end to the semiconductor element.
It expanded to more than mm, increasing the mounting area.

本発明は前記従来の半導体装置の欠点を除去す
るためになされたものであり、以下に本発明の一
実施例における半導体装置について第2図a―c
を用いて説明する。まず、第2図aに示すように
半導体素子1の電極上に金属突起2を設ける。次
いでポリイミイドフイルム3に電極リード4を設
け、前記半導体素子1の金属突起2と前記電極リ
ード4とを位置合わせし、加圧、加熱した接合さ
せる。上述した工程は、すでに従来例でのべた通
りである。
The present invention has been made to eliminate the drawbacks of the conventional semiconductor device, and the semiconductor device according to an embodiment of the present invention will be described below with reference to FIGS.
Explain using. First, as shown in FIG. 2a, metal protrusions 2 are provided on the electrodes of the semiconductor element 1. Next, electrode leads 4 are provided on the polyimide film 3, and the metal protrusions 2 of the semiconductor element 1 and the electrode leads 4 are aligned and bonded under pressure and heat. The above-mentioned steps have already been described in the conventional example.

ついで、半導体素子1の両側に有材(例えばエ
ポキシ樹脂又はシリコン樹脂)、あるいは無機材
(例えばセラミツク、ガラス物質)12,12′を
置き、圧力11を加える事によつて第2図bの構
造を得る。次に、第2図cに示すように真空状態
下において、前記半導体素子の周囲が有機材又は
無機材で覆われたフイルムキヤリヤの電極リード
部分までを露出させる蒸着マスク20,20′を
前記半導体素子1上にじ設置し、スパツター法、
抵抗加熱法、電子ビーム法等により蒸着21,2
1′し、蒸着層22を形成せしめる。この様にし
て本発明の実施例における半導体装置が得られる
わけである。
Next, a material (e.g., epoxy resin or silicone resin) or an inorganic material (e.g., ceramic, glass material) 12, 12' is placed on both sides of the semiconductor element 1, and by applying pressure 11, the structure shown in FIG. 2b is obtained. get. Next, as shown in FIG. 2c, in a vacuum state, a vapor deposition mask 20, 20' is applied to expose the electrode lead portion of the film carrier, which is covered with an organic or inorganic material around the semiconductor element. A rainbow is placed on the semiconductor element 1, and a sputtering method is applied.
Vapor deposition 21, 2 by resistance heating method, electron beam method, etc.
1' to form a vapor deposited layer 22. In this way, a semiconductor device according to an embodiment of the present invention is obtained.

前記蒸着層22を形成する工程において、蒸着
構内において、前記半導体素子1を遊星運動させ
る事により、前記半導体素子1の有機材又は無機
材の表面を完全に優う形で、蒸着層が形成され
る。前記蒸着層22は耐蝕性を有し徴密な材料で
構成されるもので、例えば、金属であれば、
Cr,Ti,Pt等の材質、無機材であれば、アルミ
ニウムの酸化物、Tiの酸化物、Crの酸化物、Si
の酸化物、あるいはSiの窒化物、Bの窒化物等が
適するものである。又膜厚は、各材料が有する徴
密度にもよるが1000Å以上〜数10μm程度であ
る。
In the step of forming the vapor deposition layer 22, the semiconductor element 1 is caused to move in a planetary manner in the vapor deposition facility, so that the vapor deposition layer is formed in a manner that completely dominates the surface of the organic or inorganic material of the semiconductor element 1. Ru. The vapor deposition layer 22 is made of a corrosion-resistant and dense material, for example, if it is a metal,
Materials such as Cr, Ti, Pt, etc., in the case of inorganic materials, aluminum oxide, Ti oxide, Cr oxide, Si
An oxide of Si, a nitride of Si, a nitride of B, etc. are suitable. The film thickness is approximately 1000 Å or more to several tens of μm, depending on the density of each material.

すなわち、本実施例の半導体装置の場合、有機
材又は無機材の表面に耐蝕性のある徴密性の蒸着
層を有しているので、前記有機材又は無機材の板
厚がうすくても雰囲気からの湿気等の浸入を容易
に防ぐことが出来るから前記有機材又は無機材を
うすくして全体の厚さを極端にうすくすることが
出来る。
In other words, in the case of the semiconductor device of this embodiment, since the organic material or inorganic material has a dense vapor deposition layer on the surface thereof, the atmosphere can be maintained even if the thickness of the organic material or inorganic material is thin. Since it is possible to easily prevent the infiltration of moisture, etc., the organic material or inorganic material can be thinned, and the overall thickness can be made extremely thin.

又、蒸着層22と前記半導体素子1との間に介
入させる有機材又は無機材12は、液状もしくは
板状であつても良く、有機材又は無機材の厚さ
は、パツケージングの厚さを薄くするため、出来
るだけ薄い方が良い、このため、前記半導体素子
1と蒸着層22との電気的絶縁を得ることが出来
る厚さであれば良いから1μm以上の厚さで充分
である。前記介入させる有機材又は無機材12が
液状である場合には、半導体素子1の主面および
他面に前記液状の有機又は無機材を滴下して置
き、半導体素子1の両方から均一に加圧し、加熱
等の手段によつて硬化せしめれば良い。
Further, the organic material or inorganic material 12 interposed between the vapor deposition layer 22 and the semiconductor element 1 may be in a liquid or plate shape, and the thickness of the organic material or inorganic material depends on the thickness of the packaging. In order to make it thin, it is better to be as thin as possible. Therefore, it is sufficient that the thickness is such that electrical insulation between the semiconductor element 1 and the deposited layer 22 can be obtained, so a thickness of 1 μm or more is sufficient. When the intervening organic material or inorganic material 12 is liquid, the liquid organic or inorganic material is dropped onto the main surface and the other surface of the semiconductor element 1, and pressure is applied uniformly from both sides of the semiconductor element 1. , it may be hardened by means such as heating.

又、前記有機材又は無機材12が板状である場
合には、その形状は前記半導体素子1とほぼ同一
法にしておき、加圧、加熱して硬化すれば良い。
Further, when the organic material or inorganic material 12 is plate-shaped, its shape may be made almost the same as that of the semiconductor element 1, and the material may be cured by applying pressure and heating.

このようにして加圧することによつて、押しだ
された樹脂は第2図bに示す如く、半導体素子1
の側面に周り込み、半導体素子1を完全に保護す
ることになる。
By applying pressure in this manner, the extruded resin is transferred to the semiconductor element 1 as shown in FIG. 2b.
The semiconductor element 1 is completely protected by wrapping around the sides of the semiconductor element 1.

なお半導体素子1と蒸着層22との間に介入さ
せる有機材又は無機材12が液状であれば、前述
した如く、滴下した後、加圧、加熱し、硬化せし
めても良いが、第3図aに示す如く、滴下してそ
のまま、硬化せしめ、有機材又は無機材23を形
成し、第3図bに示すように蒸着マスク20,2
0′を設置し、蒸着層内で、蒸着層22を蒸着2
1,21′せしめる事も出来る。すなわち、この
実施例の場合、有機材又は無機材23の全面に徴
密な蒸着層22が被着されるので、前記有機材又
は、無機材23の厚さに、多少の不均一性が発生
しても、前記、有機材又は無機材23が完全に外
気の浸入を阻止し、半導体素子1の信頼性の劣化
を防止するものである。
Note that if the organic material or inorganic material 12 interposed between the semiconductor element 1 and the vapor deposition layer 22 is in a liquid state, it may be dropped and then pressurized and heated to be cured as described above. As shown in FIG. 3a, the organic material or inorganic material 23 is formed by dropping and curing as is, and as shown in FIG.
0', and the vapor deposition layer 22 is deposited within the vapor deposition layer.
It is also possible to make it 1,21'. That is, in the case of this embodiment, since the dense vapor deposition layer 22 is deposited on the entire surface of the organic material or inorganic material 23, some non-uniformity occurs in the thickness of the organic material or inorganic material 23. Even in such a case, the organic material or inorganic material 23 completely prevents the infiltration of outside air and prevents the reliability of the semiconductor element 1 from deteriorating.

又、本発明のパツケージングによる半導体装置
は前記ポリイミドフイルムから切断され、前記電
極リード4を成型すれば第4図の如くなり、成型
された電極リード13は容器に配線用基板に半田
づけ等の手段で接続し、回路を構成し、実装する
ことが出来る。
The semiconductor device according to the packaging of the present invention is cut from the polyimide film and the electrode leads 4 are molded to form the result as shown in FIG. It is possible to connect, configure, and implement a circuit using various means.

次に本発明のさらに他の実施例における半導体
装置についてのべる。
Next, a semiconductor device according to still another embodiment of the present invention will be described.

第5図の構成の半導体装置においては、電極リ
ード4を14で示すように半導体素子1の他面の
蒸着層22′の方向にまで折曲げ前記蒸着層2
2′と接するようにしてある。このような構成で
あれば、いわゆる半導体素子のパツケージのチツ
プキヤリヤと同一の概念を有するパツケージを得
ることが出来る。第5図の如くの構成は第4図の
構成に比較して、配線基板と接続するために必要
な電極リードの長さが半導体素子の大きさに加算
されて、実装面積が増大することがない。すなわ
ち配線基板と接続するために必要な電極リードの
長さは、第4図においては13′であるが、第5
図では14′に相当するものである。したがつ
て、第4図では折曲げた電極リード13′は1〜
1.5mm必要であるが第5図では、電極リード板1
0′の方向に折曲がつているから、1〜1.5mmの分
だけ実装密度を高くすることが出来る。
In the semiconductor device having the structure shown in FIG.
2'. With such a configuration, it is possible to obtain a package having the same concept as a chip carrier of a so-called semiconductor device package. Compared to the configuration shown in FIG. 4, the configuration shown in FIG. 5 increases the mounting area because the length of the electrode lead required for connection to the wiring board is added to the size of the semiconductor element. do not have. In other words, the length of the electrode lead required for connection to the wiring board is 13' in Fig. 4, but the length of the electrode lead is 13' in Fig.
In the figure, it corresponds to 14'. Therefore, in FIG. 4, the bent electrode leads 13' are
1.5mm is required, but in Figure 5, electrode lead plate 1
Since it is bent in the 0' direction, the packaging density can be increased by 1 to 1.5 mm.

本実施例の構成において、蒸着層は単層膜でな
くCr―Cr2O3,Ti―Ti2O3,Cr―Al2O3等の多層
膜を連続して蒸着して形成しても良いものであ
る。
In the configuration of this example, the vapor deposition layer is not a single layer film, but may be formed by successively vapor depositing multilayer films such as Cr-Cr 2 O 3 , Ti-Ti 2 O 3 , Cr-Al 2 O 3 , etc. It's good.

次に本発明の更に他の実施例における半導体装
置について第6図、第7図で説明する。半導体素
子1の全面に形成された、有機材又は無機材12
上の蒸着層22上に更に樹脂層(エポキシ,シリ
コーン樹脂)24を形成する。この様な構成にお
いては、外気浸入を一段と防止できるので、著じ
るしく、信頼も向上するものである。前記蒸着層
22上樹脂層24は、吹きつけ法、滴下法、はけ
塗り法等の方法により形成出来るものである。
Next, a semiconductor device according to still another embodiment of the present invention will be described with reference to FIGS. 6 and 7. Organic material or inorganic material 12 formed on the entire surface of the semiconductor element 1
A resin layer (epoxy, silicone resin) 24 is further formed on the upper vapor deposition layer 22. In such a configuration, since the infiltration of outside air can be further prevented, reliability is significantly improved. The resin layer 24 on the vapor deposition layer 22 can be formed by a method such as a spraying method, a dropping method, or a brushing method.

更に他の実施例における、第7図の半導体装置
の構成においては、前記有機材又はは無機材12
がフイルムキヤリヤのポリイミイド3の部分まで
拡がり、前記半導体素子をポリイミイド3と前記
有機材又は無機材12で完全に覆つた状態にあ
る。したがつて、完全に外気を遮断でき、高い信
頼性を確保できるものである。
In still another embodiment, in the configuration of the semiconductor device shown in FIG. 7, the organic material or inorganic material 12
extends to the polyimide 3 portion of the film carrier, completely covering the semiconductor element with the polyimide 3 and the organic or inorganic material 12. Therefore, it is possible to completely shut off outside air and ensure high reliability.

以上のべた如く本発明の半導体装置の構成で
は、以下の効果を奏する。
As described above, the structure of the semiconductor device of the present invention has the following effects.

(1) 半導体素子全体が有機材又は無機材を介し
て、徴密で密度の高く、かつ薄い蒸着膜で覆わ
れている。したがつて、前記蒸着膜が外気の浸
入を防止するから有機材又は、無機材は非常に
薄く形成出来る。このために従来の半導体装置
と比べ、著しく小さいパツケージを提供するこ
とが出来る。
(1) The entire semiconductor element is covered with a dense, dense, and thin vapor-deposited film using an organic or inorganic material. Therefore, since the vapor-deposited film prevents outside air from entering, the organic material or inorganic material can be formed very thin. Therefore, it is possible to provide a significantly smaller package than conventional semiconductor devices.

(2) 半導体素子全体が、有機材又は無機材と、更
に徴密な密度の高い蒸着膜で保護されるから、
外気の浸入を積極的に妨げ、高い信頼性の半導
体素子のパツケージを提供する事が出来る。
(2) Since the entire semiconductor element is protected by an organic or inorganic material and a densely deposited film,
It is possible to actively prevent the infiltration of outside air and provide a highly reliable semiconductor device package.

(3) (1)でも述べたよ如くパツケージの平面積を著
しく小さくすることが出来る他に、蒸着膜によ
つて半導体素子1を薄く保護することが出来る
から全体の厚みも、仮に半導体素子が0.5mm、
蒸着膜が10μm、間の介在する樹脂を2μm程
度にすれば0.512mmのパツケージを得ることが
出来るものである。
(3) As mentioned in (1), in addition to being able to significantly reduce the planar area of the package, the semiconductor element 1 can be protected thinly by the vapor deposited film, so the overall thickness can be reduced even if the semiconductor element is 0.5 mm,
If the thickness of the deposited film is 10 μm and the thickness of the intervening resin is approximately 2 μm, a package of 0.512 mm can be obtained.

(4) 本発明の半導体装置の構成では、例えば第2
図で述べた如く、半導体素子の両面から加圧す
れば、前記半導体素子の表面の沿つて、有機材
又は無機材が平らに成型され、更にこの上に蒸
着膜を形成するから前記半導体素子が放熱を必
要とするようなものであつても、前記蒸着膜を
配線基板に直接ダイボンデイングすることが出
来、理想的な放熱を行なうことが出来るもので
ある。
(4) In the configuration of the semiconductor device of the present invention, for example, the second
As described in the figure, when pressure is applied from both sides of the semiconductor element, the organic material or inorganic material is formed flat along the surface of the semiconductor element, and a vapor deposited film is formed on this, so that the semiconductor element is Even if the device requires heat radiation, the vapor deposited film can be die-bonded directly to the wiring board, and ideal heat radiation can be achieved.

(5) 更に既にのべた如く本発明の半導体装置の構
成は、半導体素子の両面において、平であるた
めに放熱特性が、半導体素子の平面方向におい
て均一に得られる。従来例においては、半導体
素子の中央部において樹脂が盛り上つた構成で
あるから、半導体素子からの熱が半導体素子の
中央部にこもりやすく、半導体素子を熱破壊に
招く恐れがある。これに対し本発明は板が半導
体素子と同一平面を有し、更に半導体素子とわ
ずか数μmしか近接していないから、半導体素
子の発生した熱を均一に放出することが出来る
ものである。
(5) Furthermore, as already mentioned, in the structure of the semiconductor device of the present invention, since both surfaces of the semiconductor element are flat, heat dissipation characteristics can be obtained uniformly in the planar direction of the semiconductor element. In the conventional example, since the resin bulges in the center of the semiconductor element, heat from the semiconductor element tends to be trapped in the center of the semiconductor element, which may lead to thermal damage to the semiconductor element. In contrast, in the present invention, since the plate is on the same plane as the semiconductor element and is close to the semiconductor element by only a few micrometers, the heat generated by the semiconductor element can be radiated uniformly.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の半導体装置の断面図、第2図a
〜cは本発明の一実施例における半導体装置の構
成を説明するための断面図、第3図a,bは本発
明の他の実施例における半導体装置の構成を説明
するための断面図、第4図、第5図、第6図およ
び第7図はそれぞれ本発明のさらに他の実施例に
おける半導体装置の断面図である。 1……半導体素子、2……金属突起、3……フ
イルム、4……電極リード、12……有機材又は
無機材、22……蒸着膜。
Figure 1 is a cross-sectional view of a conventional semiconductor device, Figure 2a
-c are cross-sectional views for explaining the structure of a semiconductor device in one embodiment of the present invention; FIGS. 3a and 3b are cross-sectional views for explaining the structure of a semiconductor device in another embodiment of the present invention; 4, FIG. 5, FIG. 6, and FIG. 7 are sectional views of semiconductor devices according to still other embodiments of the present invention. DESCRIPTION OF SYMBOLS 1... Semiconductor element, 2... Metal protrusion, 3... Film, 4... Electrode lead, 12... Organic material or inorganic material, 22... Vapor deposited film.

Claims (1)

【特許請求の範囲】 1 半導体素子上の電極に可撓性フイルムが一体
となつた金属リードが固定された前記半導体素子
の主面および他面に、前記半導体素子を包含する
蒸着層を有機材又は無機材の層を介して設置した
ことを特徴とする半導体装置。 2 金属リードが半導体素子の主面又は他面に設
けた蒸着層の有機材又は無機材の層を介していな
い面まで延在されたことを特徴とする特許請求の
範囲第1項記載の半導体装置。 3 半導体素子上の電極に可撓性フイルムが一体
となつた金属リードが固定された前記半導体素子
の主面および他面に、前記半導体素子を包含する
蒸着層を第1の有機材又は無機材に層を介して設
置し、更に前記蒸着層上に第2の有機材又は無機
材の層を設置したことを特徴とする半導体装置。
[Scope of Claims] 1. A vapor deposited layer containing the semiconductor element is formed using an organic material on the main surface and the other surface of the semiconductor element to which a metal lead with a flexible film integrated with the electrode on the semiconductor element is fixed. Or a semiconductor device characterized in that it is installed through an inorganic material layer. 2. The semiconductor according to claim 1, characterized in that the metal lead extends to a surface not passing through an organic material or inorganic material layer of a vapor deposited layer provided on the main surface or the other surface of the semiconductor element. Device. 3. A vapor deposited layer containing the semiconductor element is coated with a first organic or inorganic material on the main surface and the other surface of the semiconductor element to which a metal lead with a flexible film integrated with the electrode on the semiconductor element is fixed. 1. A semiconductor device, characterized in that a second layer of an organic material or an inorganic material is provided on the vapor deposition layer.
JP56186321A 1981-11-19 1981-11-19 Semiconductor device Granted JPS5886750A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56186321A JPS5886750A (en) 1981-11-19 1981-11-19 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56186321A JPS5886750A (en) 1981-11-19 1981-11-19 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS5886750A JPS5886750A (en) 1983-05-24
JPS6142429B2 true JPS6142429B2 (en) 1986-09-20

Family

ID=16186283

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56186321A Granted JPS5886750A (en) 1981-11-19 1981-11-19 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5886750A (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4633573A (en) * 1982-10-12 1987-01-06 Aegis, Inc. Microcircuit package and sealing method
JPH0831988A (en) * 1994-07-20 1996-02-02 Nec Corp Tape carrier package sealing structure
JP6227914B2 (en) * 2012-12-18 2017-11-08 花王株式会社 Method for improving the reaction selectivity of alkylene oxides

Also Published As

Publication number Publication date
JPS5886750A (en) 1983-05-24

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