JPS6142889B2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention is suitable for gain control circuits, particularly for multi-stage amplifier circuits such as radio frequency amplification stages (hereinafter referred to as REF stages) and intermediate frequency amplification stages (hereinafter referred to as IF stages) in radio reception, etc. Automatic gain control circuit (below
(referred to as AGC circuit).

Conventionally, in this type of AGC circuit, in order to improve the signal-to-noise ratio characteristics, the AGC operation of the RF stage was changed to IF.
Generally, this is performed later than the second stage. However, such a configuration
In an AGC circuit, when the gain of the IF stage is appropriately compressed, the bias conditions at the input section of the AGC circuit change, and as a result, distortion may occur in the output of the RF stage. In other words, when a multi-stage amplification amplifier circuit is equipped with an AGC function, the gain control amount is set to follow the gain distribution of each stage and to prevent distortion from occurring in the output of the previous stage. It is difficult to accurately control this set amount to a constant value, and therefore, if the gain control of the subsequent stage is performed excessively, the amplified output of the previous stage will be larger than the amplified output of the latter stage, and as a result, the amplified output of the previous stage will become larger than that of the subsequent stage. Distortion occurs in the amplified output.

An object of the present invention is to provide an automatic gain control circuit that can arbitrarily and accurately set a gain control amount.

Next, a description will be given with reference to the drawings.

Figure 1 shows an example of a conventional AGC circuit.
An input signal terminal a, a bias circuit consisting of a resistor _R1 and a Zener diode ZD1, and a transistor _Q5 with a resistor _R3 connected between the base and collector.
and a terminal a bias circuit consisting of a resistor _R2 ,
An amplifier consisting of transistors Q ₁ and Q ₂ and a transistor Q ₃ connected in cascode to both, the load RL, a terminal b from which the output signal generated at the load RL is taken out, and a signal from the terminal b is detected. Detector A outputs the detected signal to terminal c, and outputs the AGC voltage to terminal d after smoothing, and resistor _R7.
and a bias circuit of transistors Q ₁ and Q ₂ consisting of diodes D ₁ , D ₂ and DC, and a bias circuit from terminal d.
It includes a transistor _Q4 that is turned on or off by the AGC voltage and changes the current divided into the two transistors _Q1 and _Q2 according to the input signal level. Note that C ₁ and C ₂ are bias capacitors,
1 is a power supply terminal.

Next, the operation will be explained.

First, while the input signal level is low, the base voltage of transistor Q ₂ of transistors Q ₁ and Q ₂ is higher than the base voltage of Q ₁ by the voltage drop of diode D ₁ , so transistor Q ₂ becomes conductive. ,
Since transistor Q ₁ is cut off, the input signal is amplified by the amplifier circuit consisting of transistors Q ₃ and Q ₂ and then output to terminal b. terminal b
The signal output from the detector A is smoothed by the AGC
Output as voltage to terminal d and transistor Q ₄
input to the base of However, as mentioned above, since the input signal level is low, the signal is output to terminal d.
The AGC voltage is also small, so transistor _Q4 remains cut off. In this state, gain control is not performed.

Next, as the input signal level increases, the AGC voltage output to terminal d also increases,
Eventually, when the voltage increases to an extent exceeding the threshold voltage of transistor Q ₄ , transistor Q ₄ begins to conduct, and its collector current begins to flow from the power supply via resistor R ₅ , so that the base voltage of transistor Q ₂ gradually drops. The conduction state of transistor _Q2 becomes shallow. When the conduction state of transistor Q ₂ becomes shallow, transistor Q ₁ starts to conduct in turn, so that part of the collector current of transistor Q ₃ also flows into transistor Q ₁ , and is therefore supplied to load R _L. The current flowing through the circuit decreases, and the gain decreases. As the input signal level increases further, the resistance
As the voltage drop across R ₅ increases, transistor Q ₂ finally shuts off, and all of the collector current of transistor Q ₃ flows into transistor Q ₁ , so that the gain control amount becomes maximum.

As mentioned above, the conventional AGC circuit has a large gain control amount (theoretically infinite), and is therefore extremely useful when large gain control is required.
It is impossible to set the control amount accurately,
Therefore, as described above, if gain control is performed excessively, distortion will occur in the output of the previous stage amplification.

FIG. 2 is a circuit diagram showing a first embodiment of the present invention. In the circuit shown in FIG. 1, a series circuit of a transistor Q ₆ whose base is commonly connected to the base of the transistor Q ₁ and a resistor R ₈ is shown. The transistor Q ₂
are connected in parallel.

Next, the operation will be explained.

While the signal level input to terminal a is low,
No AGC operation is performed, and therefore, as described above, all of the collector current of transistor Q ₃ is supplied to load R _L via transistor Q ₂ . Assuming that the voltage gain at this time is _A1 , _A1 is expressed by the following formula.

A ₁ =R _L /26/IeQ ₃ (1) However, IeQ ₃ is the emitter current of the transistor Q ₃ , and the unit is mA.

Next, the input signal level increases, the AGC voltage output to terminal d increases accordingly, transistor Q ₄ becomes conductive, and transistor Q ₂
is cut off and transistors Q ₁ and Q ₆ conduct, at which time the gain control is at its maximum. However, in the AGC circuit according to the present invention, the transistor
Even if Q ₂ is cut off, the collector current of transistor Q ₃ is supplied to load R _L through transistor Q ₆ as well, so the maximum gain control amount is smaller than in the conventional circuit. The current flowing from transistor _Q6 to load R _L is 1/α of the collector current of transistor _Q3 .
If the voltage gain at that time is A ₂ , A ₂ is expressed as follows.

A ₂ =R _L /26/IeQ ₃ ·1/α Therefore, the maximum gain control amount B is B=A ₁ /A ₂ =α. Here α can be arbitrarily determined by resistance R ₈ ,
Moreover, it is possible to control accurately.

FIG. 3 is a diagram showing a second embodiment of the present invention. In the circuit of FIG. 2, transistors Q ₁ , Q ₂ and
Only part of _Q6 has been extracted. Transistors Q ₁ , Q ₂ and Q ₆ have resistors R ₁₄ , R ₁₅ and
_R8 is connected, and the gain control amount can be controlled by the ratio of the respective resistances. According to integrated circuit technology, it is possible to control the resistance ratio with extremely high precision, so that the maximum gain control amount can also be set accurately.

AGC circuits according to the prior art and the present invention have been described above with reference to three figures. In any case, when AGC operation is performed, the collector current path of transistor Q ₃ is changed from transistor Q ₂ to Q ₁
or when switching from Q ₂ to Q ₁ and Q ₆ , the DC bias current of the load R _L changes, resulting in distortion when extracting a large signal from the load R _L.

FIG. 4 shows a third embodiment according to the invention.
This is an AGC circuit diagram configured as a double differential type to eliminate the above drawbacks. In the figure, the newly added items are resistors R ₉ to R ₁₃ and transistors.
_Q7 to _Q12 and capacitor _C3 .

As is well known, in a double differential circuit, the DC bias current flowing through the load, resistor R ₉ in the figure, is always constant; therefore, the DC bias current flows through the resistor R ₉
The voltage developed across the transistor Q ₁₁ and the transistor Q ₁₂ causes a constant DC bias current to be supplied to the load R _L at all times. Therefore, the load R
It is possible to eliminate the disadvantage that distortion occurs when extracting a large signal from _L. Of course, the gain control amount is set by the resistor _R8 connected to the emitter of the transistor _Q6 .

As described above, according to the present invention, the gain control amount of the amplifier can be set accurately and arbitrarily, so that the gain control is not performed excessively as in the past, and in other words, it can be performed accurately. Therefore, distortion does not occur in the amplified output of the previous stage.

As described above, the present invention is extremely effective in providing an AGC circuit that can accurately set the gain control amount.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a conventional AGC circuit, and FIGS. 2 to 4 are diagrams showing first to third embodiments of the present invention, respectively. Q ₁ ~ Q ₁₂ ... Transistor, R ₁ ~ _{R 15} ... Low resistance, C ₁
~ _C3 ...Capacitor, _D1 ~ _D3 ...Diode, _ZD1 ...
Zener diode, a...input terminal, b...output terminal, c...detection output terminal, d...AGC voltage output terminal, R _L ...load, A...detector.

Claims (1)

[Claims] 1 a first transistor whose base receives an input signal; second and third transistors each having an emitter connected to the collector of the first transistor and each having a bias voltage supplied to each base; a first means for forming an output signal and a gain control voltage from an output taken from the collector of the transistor; and a first means for applying an operating potential to the collector of the third transistor independently of the collector of the second transistor. 2 means and
a fourth transistor whose base is connected to the base of the third transistor, whose collector is connected to the collector of the second transistor, and whose emitter is connected to the collector of the first transistor via a resistor; and third means for controlling a base bias voltage supplied to the base of the second or third transistor according to the gain control voltage so that the signal level of the output signal is substantially constant. An automatic gain control circuit comprising: