JPS6142989B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a communication control device using a high-level procedure, and in particular, it is capable of detecting fractional bits of less than 1 byte in the final part when a data field in one frame is divided into units of 8 bits. The present invention relates to a fractional bit control circuit as described above.

In communication based on high-level procedures, data communication is performed using a frame structure as shown in FIG. A flag pattern (F pattern) exists at the beginning and end of one frame, and after the first flag pattern, an address field (part A) and a control field (part C) are located, followed by a data field (part D). ) is followed.

A frame check sequence (FCS) is provided between the data field and the final flag pattern. The flag pattern, address field, and control field each consist of one byte, and the frame check sequence consists of two bytes.

On the other hand, in the data field part, since bit-oriented communication is originally performed in high-level procedures without depending on the data format, there is no restriction on the poundage of the number of bits.

However, in general, between devices or within a device,
For example, between the central processing unit of the host and the communication control unit, or within the communication control unit, 1-byte (8-bit) pounder data is transferred, so data from the line should also be divided into 8-bit blocks before transfer. is being used. Therefore, if the data field is not 8-bit pounder, the first
The fractional bit portion D' shown in the figure must be determined.

On the other hand, even in data communication systems that employ high-level procedures that enable bit-oriented data communication, in general, when using existing equipment, data is handled in bytes on the transmitting side, and data is processed in byte units. Since a data field with a 100% is often transmitted, and the boundaries match on the sending and receiving sides, this has not been a particular problem.

However, in a communication control device connected via a line to a device intended for bit-oriented data communication without being aware of the 8-bit boundary, the fractional bits described above are detected.
Separation of data fields and frame check sequences must be made. Conventionally, for example, fractional bits were detected by program control after the final F pattern was detected, and the data field and frame check sequence were separated.

An object of the present invention is to easily detect fractional bits by adding simple hardware to an existing data receiving circuit that assembles data into 8-bit boundaries. The flag pattern at the beginning,
A processing request signal issued each time data is received in bytes in a communication control device that uses a high-level procedure consisting of an address field, a control field, a data field, a frame check sequence, and a final flag pattern. The count value of the counter circuit is initialized by the counter circuit, is incremented by the bit clock sent from the line side in synchronization with the received bits, and is stopped from incrementing by the flag pattern detection signal. According to
The present invention is characterized in that the number of fractional bits less than 1 byte in the final part of the data field is determined.

Hereinafter, the present invention will be explained with reference to the drawings. FIG. 2 shows a fractional bit control circuit in a communication control device according to an embodiment of the present invention. In the figure, 1 is a receiving circuit, 2
is a counter circuit, 3 is a data line from the line, 4 is a bit clock line, 5 is a received data line, 6 is a processing request signal line, 7 is a processing request reset line, 8 is an F pattern detection signal line, 9 is a bit count output It is a line.

The data line 3 and the bit clock line 4 are connected to a circuit corresponding device (not shown), and the bit clock on the bit clock line 4 is sent out in synchronization with the data on the data line 3. Also, a reception data line 5, a processing request signal line 6, a processing request reset line 7,
The F pattern detection signal line 8 and the bit count output line 9 are connected to a common section (not shown).

The receiving circuit 1 is an existing circuit, and has the function of assembling data sent from the data line 3 into 8-bit units based on the clock on the bit clock line 4. The assembled 8-bit data is sent to the common section through the reception data line 5 if the 8-bit data is a pattern other than the F pattern. Further, at this time, a processing request signal is sent to the common section through the processing request signal line 6. After receiving the received data based on the processing request signal, the common section sends a processing request reset signal to the receiving circuit 1 through the processing request reset signal line 7. As a result, the receiving circuit 1 stops sending out the processing request signal.

Furthermore, the receiving circuit 1 has an F pattern detection function, and when it receives the bit pattern "01111110" (F pattern) from the data line 3, it sends an F pattern detection signal to the common section via the F pattern detection signal line 8. Do it like this.

In FIG. 2, a counter circuit 2 is a new circuit provided according to the present invention. This counter circuit 2 consists of 3 bits and can count from 0 to 7. The counter circuit 2 has a processing request signal line 6
After being reset at the rising edge of the processing request signal above, the bit clock on the bit clock line 4 performs a stepping operation. Therefore, each time data arrives in units of 8 bits, the counting operation from 0 to 7 is repeated.

Furthermore, when the F pattern detection signal is issued on the F pattern detection signal line 8, the counter circuit 2 stops the counting operation at that point and holds the count value at that time.

Next, the fractional bit detection operation in the circuit of FIG. 2 will be explained with reference to the sequence diagram of FIG. Second
The receiving circuit 1 shown in the figure assembles bits using 8-bit boundaries after detecting the first F pattern (at this time, the F pattern reception is simply for synchronization and the F pattern detection signal does not turn on). When the parts are assembled, the first processing request signal is issued. At this time, the counter circuit 2 is set to an initial value of "0". Although the value of the counter circuit 2 is undefined before it is initialized, the value becomes meaningful when the F pattern detection signal 8 or the processing request signal 6 turns on. Thereafter, the counter circuit 2 is incremented by 1 each time the receiving circuit 1 receives data on the line one bit at a time, that is, each time one bit clock arrives. Then, when the receiving circuit 1 finishes receiving the next C part (not shown), the counter circuit 2 has the final value "7", and the counter circuit 2 returns to the initial value "0" due to the processing request signal from the receiving circuit 1. ”. Thereafter, the receiving circuit 1 assembles the D section (data field) 8 bits at a time, and at the same time, the counter circuit 2 repeats the counting operation of 2 to 7.

In the case shown in FIG. 3, after receiving the last regular 8-bit pounder data RD _o-1 , the next received and assembled data R ₀ includes 3 bits of fractional data and a part of FCS ₀ . There is. Further, the subsequent received data RD _o+1 includes a part of FCS ₀ and a part of FCS ₁ , and RD _o+2 includes a part of FCS ₁ and a part of F pattern.

After receiving the last F pattern, when the F pattern detection signal is issued, the counter circuit 2 stops counting operation. In the case shown in FIG. 3, the count value of the counter circuit 2 indicates "3" and has the same value as the fractional bit. In this way, when the F pattern detection signal is turned on after receiving the fractional bits, the value of the counter circuit 2 always indicates the number of fractional bits. Therefore, on the common part side, the received data R _o , which was assembled before the F pattern detection signal was turned on,
Depending on the values of RD _o+1 , RD _o+2 and counter circuit 2
Divide RD _o 8 bits into 3 fractional bits and 5 bits of FCS ₀ , and divide RD _{o +1} 8 bits with remaining 3 bits of FCS _0.
Divide into 5 bits of FCS ₁ , and divide RD _o+2 8 bits into FCS ₁
Only the remaining 3 bits are used to assemble fractional data and check the FCS. Furthermore, when receiving the next frame continuously, the receiving circuit 1
When the part is received, the processing request signal 6 is turned on as described above, and at this time the F pattern detection signal is turned off, the counter circuit 2 is initialized to "0", and the same operation as in the above-mentioned part A assembly is performed.

As described above, according to the present invention, it is possible to easily detect fractional bits by adding simple hardware, reducing the load on common parts and improving processing performance. It has excellent effects.

[Brief explanation of the drawing]

FIG. 1 is an example of a frame structure in a high-level procedure, FIG. 2 is a fractional bit control circuit in a communication control device according to an embodiment of the present invention, and FIG. 3 is a sequence diagram of a fractional bit detection operation. In FIG. 2, 1 is a receiving circuit, 2 is a counter circuit, 3 is a data line from the line, 4 is a bit clock line, 5 is a received data line, 6 is a processing request signal line, 7 is a processing request reset line, and 8 is a The F pattern detection signal line 9 is a bit counter output line.

Claims (1)

[Claims] 1 One frame consists of a flag pattern at the beginning, an address field, a control field, a data field, a frame check sequence,
In a communication control device that uses a high-level procedure consisting of a final flag pattern, it is initialized by a processing request signal that is issued every time data is received in bytes, and is also sent from the line side in synchronization with the received bit. It is equipped with a counter circuit that is incremented by the sent bit clock and stopped increment by the flag pattern detection signal, and the number of fractional bits less than 1 byte in the final part of the data field is determined by the count value of the counter circuit. 1. A fractional bit control circuit for a communication control device using a high-level procedure method, characterized in that the fraction bit control circuit is configured to determine.