JPS6143741B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a control method for a memory device including a plurality of memory modules.

Conventionally, a method called interleaving has been proposed as a method of using memory substantially faster than its original speed. In this method, a memory system is configured using n memory banks that can operate independently, and addresses are assigned in software or hardware so that consecutive memory accesses access different memory banks. Keep it on. This allows partial simultaneous operation of multiple banks as long as there are no consecutive accesses to the same memory bank. for example,
In a memory system like the one shown in Figure 1, 1/2 of the unique cycle time of each bank 0, 1, 2, and 3.
It is possible to operate with a cycle time of The memory banks shown in this figure are independent from other memory banks, and each bank usually has its own timing generator circuit, interface with a processing device, etc. required for memory operation. In addition, the memory bus is often managed by the processing device 4. In Fig. 1, a is memory bank i.
, b denotes the memory cycle of memory bank j, where i≠j, 0≦i, j≦3
It is.

On the other hand, considering the current state of large-scale information processing systems these days, the complexity of the software is increasing and the cost of developing it is enormous. Measures to reduce software development costs include increasing memory capacity, such as modularizing programs and using high-level languages. Furthermore, recent advances in memory technology have led to larger capacities and lower costs of memory elements, and together with these factors, there has been a strong tendency for memory capacities to increase.

However, if the capacity is increased using the conventional interleaving technology, the following problems will arise. In other words, if the storage capacity of a memory bank is kept constant and the capacity is increased by increasing the number of memory banks, the amount of hardware such as interface circuits and control circuits that must be prepared independently for each bank will also increase proportionally. It is not economical to do so. This is thought to be due to the fact that the increased capacity and lower cost of memory elements have not been fully utilized. On the other hand, if you increase the capacity by increasing the storage capacity within the memory bank while keeping the number of memory banks constant, the capacity of one bank will become too large and the effect of interleaving will decrease. be. For example, if a 16 kilobit memory element is used, a typical sized memory card will be 128 kilobytes per card, and if a bank is made up of four cards.
It reaches 512 kilobytes, and this is the basic unit and expansion unit. This is quite large even in typical large memory systems. Also,
In this case, a drawback arises in that the effect of interleaving cannot be fully demonstrated. because,
In normal access, the instruction fetch and data reading required by the processing unit occur alternately, so a commonly used interleaving method is to separate instructions and data into separate banks, but the storage in one bank is This is because if the capacity becomes too large, instructions and data cannot be allocated properly (the probability that instructions and data are stored in the same bank increases).

The present invention has been made in order to eliminate the above-mentioned drawbacks inherent in the conventional technology, and therefore, an object of the present invention is to improve the conventional speed-up method (interleaving) by using highly integrated memory elements. The object of the present invention is to provide an economical memory system.

Another object of the present invention is to provide a new memory system that can increase capacity without increasing the number of banks.

Still another object of the present invention is to provide a memory system that minimizes the number of expansion units and enables interleaving.

The above object of the present invention includes a memory module group consisting of n (n≧3) memory modules;
In a memory device that operates while being connected to a processing device, a control circuit, first and second timing generation circuits, display means for displaying usage states of the first and second timing generation circuits, and a display device that displays the usage status of the first and second timing generation circuits, a comparison means for comparing the number of the memory module and the number of the currently accessed memory module; and at least an address signal, a write signal, and a read data signal among the signals connecting the control circuit and the memory module group are common. a common line that supplies the timing signal generated by the first timing generation circuit to the memory module group; and a timing signal line that commonly supplies the timing signal generated by the first timing generation circuit to the memory module group; A timing signal line that is commonly supplied to a group of memory modules is provided, and when a first access request is received from the processing device, one of the first and second timing generation circuits is used. A first access request is processed by generating timing necessary for memory operation, a second access request is subsequently received from the processing device, and the display means is one of the first and second timing generation circuits. When one of the memory module is displayed as being in use, when the comparison means detects that the second access request is a request for the same memory module as the first access request, the second access request is displayed as being in use. The access request is invalidated, and when a request is made to a different memory module, the timing generation circuit that is not used among the first and second timing generation circuits is used to generate the timing necessary for memory operation. The second
This is achieved by a memory device control method characterized in that it processes access requests.

The present invention provides a memory module and
Most of the connection signal lines of the control circuit that controls this are shared by the negative number of memory modules, and the memory modules are operated with temporal overlap.

Next, a preferred embodiment of the present invention will be explained in detail with reference to the drawings.

FIG. 2 shows a block diagram of a memory system constructed using the present invention. In the figure, reference number 4 is a processing device, 6 is a memory device, 7 is a control circuit, and 8 ₁ to 8 ₄ are memory modules. Now, the focus of the present invention is to connect a large number of memory modules to two timing generation circuits (these will be referred to as TC1 and TC2) included inside the control circuit 7.
It is intended to be controlled by Suppose now that two consecutive memory access requests a ₁ and a ₂ are generated from the processing device 4 to the memory device 6. At this time, the time interval between memory access requests a ₁ and a ₂ is shorter than the memory cycle time for processing a ₁ , and
Assuming that the memory modules requested by memory access requests a ₁ and a ₂ are MMi and MMj (1≦i, j≦4), the operating conditions of the timing generation circuits TC1 and TC2 are as shown in FIG. 3 as an example. Just leave it as .

That is, when a certain access request a ₁ occurs,
When both timing generation circuits TC1 and TC2 are idle, timing generation circuit TC1 is activated. At this time, module selection is irrelevant. Next, when another access request _a2 occurs while processing access request _a1 , if memory modules MMi and MMj are different memory modules (i≠
j), the timing generation circuit TC2 is activated. Also, if memory modules MMi and MMj
are the same memory module (i=j), no new timing is activated. Of course, when both timing generation circuits TC1 and TC2 are in use, timing is not activated even if an access request occurs.

FIG. 4 is a partial diagram of an embodiment of a control circuit that specifically realizes the conditions shown in FIG.
Further, FIG. 5 shows a portion of an embodiment of the timing selection circuit within the memory module. FIG. 6 shows an operation timing chart of FIGS. 4 and 5.

This will be explained below with reference to FIGS. 4 to 6. In FIG. 4, reference numbers ₁₀₁ to ₁₀₂ are timing generation circuits, TC1 and TC2, respectively.
corresponds to 11 ₁ to 11 ₂ are timing generation circuits 10 ₁ and 10 ₂ (hereinafter simply referred to as TC1 and TC), respectively.
2). 12
₁ to 12 ₂ are flip-flops that display whether TC1 and TC2 are in use, respectively;
2 ₁ is set by the output T0 ₁ of TC1
₁₂₂ is set by the output _T02 of _TC2 and reset by TEND ₂ . 13 is a register that holds a 2-bit signal MS of the address signal received from the processing unit to select one of the four memory modules, and 14 is a register that holds the module number of the previous access and the current access. This is a comparator circuit for comparing the module numbers of , and its output is one input of AND gate 15 . The AND gate 16 receives the flip-flops 12 ₁ and 12 ₂ as inputs, and its output becomes the other input of the AND gate 15 via an inverter 17 . This means that when the flip-flops ₁₂₁ to ₁₂₂ are both "0", that is, when both TC1 and TC2 are inactive, the module number comparison circuit 14
This is to disable the output of . The OR gate ₁₈₁ and the inverter ₁₉₁ create the starting conditions for the TC1, and the flip-flop 12
₁ and the output of AND gate 15 are connected to the input of AND gate 11 ₁ via OR gate 18 ₁ and inverter 19 ₁ . or gate 18
₂ and inverter ₁₉₂ create the starting conditions for TC2, and the Q of flip-flop ₁₂₂
The output, the output of the AND gate 16 and the output of the AND gate 15 are the OR gate 18 ₂ , the inverter 19
₂ to the input of AND gate ₁₁₂ .

Now, assuming that the memory is currently in a stopped state,
Since flip-flops ₁₂₁ and ₁₂₂ have both been reset, the output of AND gate 16 is "1", the output of inverter 17 is "0", and the output of AND gate 15 is "0". Therefore, the output of OR gate ₁₈₁ is "0", and the output of inverter 19
The output of TC1 is " ₁ ", and TC1 is ready for operation. Also, since the output of the AND gate 16 is "1", the output of the OR gate ₁₈₂ is "1", the output of the inverter ₁₉₂ is "0",
Therefore, TC2 is in an operation prohibited state. Now, in this state, when the access request signal RQ from the processing device 4 is generated, the TC1 is activated.
When TC1 is activated, timing signals T0 ₁ to TEND ₁ are sequentially generated. timing signal T
0 ₁ sets flip-flop 12 ₁ , 12
When set to ₁ , the output of the OR gate ₁₈₁ is set to "1", the output of the inverter ₁₉₁ is set to "0", and the input of the next RQ signal to TC1 is prohibited. This inhibited state continues until the flip-flop ₁₂₁ is reset by the timing signal _TEND1 . T1 ₁
is a timing signal that informs the processing device that an access request has been accepted, and OR gate 2
0 to the processing device 4 as an acceptance signal ACP. The processing device will start the next operation after confirming this signal.

The upper 2-bit signal MS of the address when the access request is accepted specifies the memory module number, and is set in the register 13 at timing _T21 , and is decoded by the decoder 21, and the four Select one of the memory modules.

Next, the operation within the selected memory module will be explained with reference to FIG. In FIG. 5, flip-flops 30 ₁ - 30 ₂ are connected to AND gates 3 for the selected module, respectively.
Timing T3 ₁ to T3 ₂ through _{1 1} to 31 ₂
and also the timing signal TEND ₁ ~
Reset at TEND ₂ . The selector 32 selects TC1 depending on the states of the flip-flops ₃₀₁ to ₃₀₂ .
~TC2 generation timing is selectively captured and used for memory operation, and when flip-flop ₃₀₁ is set, TC1 is generated.
The timing of occurrence of the flip-flop 30
When _TC2 is set, the timing at which TC2 occurs is taken in. Now, TC1
operates, flip-flop ₃₀₁ is set in the specified memory module MMi, and
Memory operations are executed at the timing generated by TC1. memory module
In the MMi, memory operations are performed by taking in necessary signals from the address and write data lines common to each memory module, and when reading data, the read data is output to the read data lines. Of course, care must be taken to ensure that only selected memory modules output to the read data line for an appropriate period of time. When the next access request does not occur within the time until the operation of the memory module MMi is completed, that is, within the memory cycle, when TC1 stops at time TEND ₁ , the memory device itself also becomes stopped again.

Next, as a second step, consider a case where a second access occurs while the first access is being processed. First, assume that the first access is being processed by TC1 (even if the first access is being processed by TC2, the following explanation will be based on exchanging TC1 and TC2 and exchanging the suffixes of the reference numbers assigned to each circuit). (can be treated in exactly the same way). As explained above, input to the AND gate ₁₁₁ is prohibited, so the second
TC1 will not be restarted by this access. On the other hand, the output of the AND gate 16 is "0". What should be noted here is that since the output of the AND gate 16 is "0" and therefore the output of the inverter 17 is "1", the output of the comparison circuit 14 that compares the numbers specified by the memory modules The operating conditions are determined. When the memory modules for the first and second accesses are different, the output of the comparison circuit 14 is "0", so the output of the OR gate ₁₈₂ is "0", and the output of the inverter ₁₉₂ is "1". Therefore, TC2 is operable (first case). Also, the first and second
When the memory modules of the accesses are equal, the output of the comparison circuit 14 is "1", and the OR gate 1
The output of the inverter ₈₂ is "1" and the output of the inverter ₁₉₂ is "0", so the TC2 is inoperable (second case).

In the first case, TC2 is activated on the second access. At this time, flip-flop ₁₂₂ is set as in the case of TC1, and AND gate ₁₁₂ is closed through OR gate ₁₈₂ and inverter ₁₉₂ , thereby prohibiting the next request. The operation of the memory module MMj specified by the second access request is the same as in the case where there is one memory module as described above. That is, it will be understood that the memory processing by the first access and the memory processing by the second access partially overlap and proceed simultaneously.

However, it is necessary to pay attention to the following points. One is that most signals except timing signals are used in common by each memory module, but by overlapping, each memory module has its own unique time allocated to each memory module. It is shorter than the memory cycle. Therefore, signals that require a longer period of time than the allotted time for memory operation must be provided in registers within each memory module. However, in recent IC memories, the length of required timing has become considerably shorter than the memory cycle, so in practice there is no need to pay such consideration. The other case is that the required time length may be short, but a certain amount of time after the start of the second access process is related to the first access process. This can be dealt with by providing an appropriate register in the control section and delaying the time. For example, if data writing takes place in the latter half of the memory cycle, a write data register may be provided and the set time of this register may be set to an appropriate time before the second access occurs.

Next, regarding the second case, since TC2 is inoperable, the acceptance signal is sent to the processing device.
ACP is not returned. Therefore, the processing unit suspends this access request and issues it again on the next clock (or it can hold the RQ signal and other signals until it is accepted). If you do this,
The second access request is accepted after the first memory cycle ends.

A time chart is shown in FIG. 6 so that what has been explained above can be more easily understood. In the example shown in FIG. 6, the memory cycle is Tc, the processing unit clock is Tc/2, and it is assumed that an access request may occur for each clock. Under these conditions, the operating states and main control timings of TC1, TC2 and memory are shown.

Of course, the present invention is not limited to the example shown in FIG. 6, and can also be applied when the overlap time is shorter than Tc/2.

Although the present invention requires some hardware for timing control inside the memory module, the number of timing controls in recent IC memory devices has decreased, and this circuit can be realized with 2 to 3 ICs, with no economic disadvantage. rare.

As explained above, according to the present invention, by providing only two timing generation circuits for a plurality of memory modules, it becomes possible to effectively operate memories in an overlapping manner, thereby creating an economical memory system. can be configured.

Although the present invention has been described above with respect to one preferred embodiment thereof, this is merely an example, and
It goes without saying that the present invention is not limited to the embodiments described here, and can be implemented with various modifications.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a conventional memory system that performs interleaving, FIG. 2 is a block diagram showing an embodiment of the present invention, FIG. 3 is a diagram explaining a method of controlling a timing generation circuit, and FIG. FIG. 4 is a diagram partially showing one embodiment of the control section circuit, FIG. 5 is a diagram showing one embodiment of the timing control circuit in the memory module, and FIG. 6 is a diagram showing an operation time chart. It is. 0 to 3...Memory bank, 4...Processing device, 5
...Memory bus, a...Memory cycle of memory bank i, b...Memory cycle of memory bank j, 6...Memory device, 7...Control unit, 8 ₁ to 8
₄ ...Memory module, 10 ₁ , 10 ₂ , TC
1, TC2...timing generation circuit, 11 ₁ , 1
1 ₂ , 15, 16, 31 ₁ , 31 ₂ ... AND gate, 12 ₁ , 12 ₂ , 30 1 , 30 ₂ ... flip-flop, 13 ... _register , 14 ... comparison circuit, 17, 19 ₁ , 19 ₂ ...Inverter, 1
8 ₁ , 18 ₂ , 20, 22 ... or gate, 32
……selector.

Claims (1)

[Scope of Claims] 1. A memory device that includes a memory module group consisting of n (n≧3) memory modules and operates while being connected to a processing device, comprising: a control circuit, first and second timings; a generating circuit, a display means for displaying the usage status of the first and second timing generating circuits, and a comparison means for comparing the number of the memory module accessed last time and the number of the memory module accessed this time;
A common line that commonly supplies at least an address signal, a write signal, and a read data signal among the signals connecting the control circuit and the memory module group, and a timing signal generated by the first timing generation circuit. a timing signal line that commonly supplies the memory module group and a timing signal line that commonly supplies the timing signal generated by the second timing generation circuit to the memory module group; When a first access request is received, one of the first and second timing generation circuits is used to generate timing necessary for memory operation to process the first access request; If there is a second access request from the device and the display means indicates that one of the first and second timing generation circuits is in use, the comparison means When it is detected that the access request is for the same memory module as the first access request, the second access request is invalidated, and when the access request is for a different memory module, the first and second access request is invalidated. Control of a memory device characterized in that the timing generating circuit that is not in use among the timing generating circuits is used to generate the timing necessary for memory operation to process the second access request. method.