JPS6143751B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to an image storage device. Over the past years, with the advancement and practical use of image processing technology, various image input devices, image display devices,
Image processing devices have been developed. These devices require mass storage capable of high speed read and write operations. Such a storage device not only needs to operate in synchronization with the image scanning signal, but also needs to be able to use various reading and writing methods, primarily changing the order in which addresses are specified. For example, in the case of display, zooming operations,
Shift operations and transpose operations are required, and in the case of input, interlaced scanning is required. Furthermore, when combined with an image calculation device, a special read/write method (addressing method) is required depending on the type of calculation. Further, in the future, a multiple use function such as reading and writing to one storage device at the same time is required. Conventionally, in such cases, a method has been adopted in which dedicated control circuits are provided for each function and these are switched depending on the required operation. However, this method has the disadvantage that the entire control circuit becomes complicated and the functions that can be realized are limited to a narrow range. The present invention has been made in view of the above, and it is an object of the present invention to provide an image storage device that can uniformly change the read/write method or address designation order used during image display, image input, and image calculation. It is something. The details of the invention will be described below. Let I ₁ and I ₂ be two images consisting of p×q pixels. When I ₁ and I ₂ are viewed as two-dimensional matrices, their column numbers and row numbers are li, mj; Li, Mj
(1ip, 1jq) and create the following two permutations.

[Table] Then, the reading/writing method of the storage device required for the above-mentioned image display, image input, and image calculation can be expressed by equation (1). For example, 2
In the case of double zoom display, the result is as follows. I ₁
Let I be the image stored in the storage device and I ₂ be the image displayed on the display device. The required replacement is

It can be expressed as [Table]. However, for simplicity, p and q are assumed to be even numbers. In the case of transposition, the column number and row number in equation (1) can be exchanged and expressed in the following form.

[Table] For simplicity, p = q. Other operations can be similarly expressed in substitution form. In order to realize this replacement operation, the present invention introduces a high-speed rewritable control storage section at least regarding addresses, preferably also regarding write/read control and peripheral circuit control. Generally, three types of signals are required to scan an image. That is, a pulse signal Fφ indicates the start of one screen, and a pulse signal L indicates the start of one scanning line.
φ is a pulse Mφ indicating the position of the pixel. This image storage device is also driven by these three pulses. 1st
The figure shows a schematic configuration of one embodiment, and the entire device is designated by the reference numeral 20. Counters 1 and 2 count pulse signals. Counter 1 counts Mφ and is reset at Lφ. Counter 2 counts Lφ and is reset at Fφ. Control memories 3 and 4 are read out using the count value of counter 1 as an address, and control memories 5 and 6 are read out using the count value of counter 2 as an address. If the X and Y coordinates of the image are defined as shown in Figure 2, the control memory 3 provides control information for the X coordinate for reading, and the control memory 4 provides control information for the X coordinate for writing. Y for reading from memory 5
Coordinate control information and Y-coordinate control information for writing are read out from the control memory 6, respectively. The readout information of the control memories 3 and 5 is combined and used to control the readout of the storage section 18. Registers 7, 8, and 9 hold these control information, and are a read address register, a read storage section control register, and an output buffer control register, respectively. The read information of the control memories 4 and 6 is used for write control of the storage section 18, and is held in the write address register 10, the write storage section control register 11, and the input buffer control register 12. The control information of the read storage control register 8 and the write storage control register 11 is held in combination in the storage control register 13. These pieces of information include, for example, instructions for reading/writing to the storage unit 18, instructions for validating/invalidating the storage unit control information itself, and the like. Either the read address or the write address is selected by the address selector 14 according to a read/write instruction from the storage control register 13.
is selected and held in the address register 15,
This is the address for the storage unit 18. The storage section 18 consists of a memory integrated circuit. The reading and writing speed of an image storage device determines the quality of the images handled, so the faster the better. On the other hand, the reading and writing speed of large-capacity memory integrated circuits is not necessarily sufficient. Therefore, storage section 1
Output buffer 1 for each output section and input section of 8
6. Place the input buffer 17. The output buffer control register 9 holds control information for the output buffer 16, and the input buffer control register 12 holds control information for the input buffer 17. FIG. 3 shows an example of the word structure of the control memory of the storage device for an image of maximum 512×512 pixels. The size of the output buffer and input buffer is 8 pixels. The meaning of each bit is as follows. R/W ₀ , R/W ₁ : Storage device read/write designation. RXC ₂ , WXC ₂ , RYC ₁ , WYC ₁ : Indicates whether the read word is valid or invalid, respectively. RXC ₁ , RYC ₀ : Indicates whether to replace the output pixel from the storage unit with 0. WXC ₁ , WYC ₀ : Indicates whether input pixels to the storage section are replaced with 0. RXA _5~0 , RBF _2~0 : Specify the X coordinate when reading. RBF _{2 to 0} are output buffer addresses,
_RXA5-0 are the lower 6 bits of the memory address. RYA _8~0 : Y coordinate when reading. Corresponds to the upper 9 bits of the address of the storage section. WXA _5~0 , WBF _2~0 : Specify the X coordinate when writing. WBF _{2 to 0} are input buffer addresses,
WXA _5-0 are the lower 6 bits of the address of the storage unit. WYA _8~0 : Y coordinate when writing. Corresponds to the upper 9 bits of the address of the storage section. RXC ₀ : Instructs to write the information in the storage section specified by addresses RYA _{8 to 0} and RXR _{5 to 0} to the output buffer. WXC ₀ : Instructs to write the contents of the input buffer to the storage section specified by addresses WYA ₈ to 0 and WXA _{5 to 0} . Let τ be the period of Mφ. Regarding the control of the output buffer and input buffer, taking the reading time as an example, we specify the memory address in advance with RY _{8 to 0} and RXA _{5 to 0} , taking into account the memory read time. Afterwards, the read information for 8 pixels is written into the output buffer, and then, according to RBF _{2 to 0} , one pixel at a time is outputted at a period τ. The same applies when writing. Further, since the read/write operation of the storage section can be changed every 8τ by R/W ₀ and R/W ₁ , it is possible to apparently perform reading and writing at the same time. However, in this case, the read/write speed is halved. Each term in each line of substitution (1) corresponds to one word. The addressing part in the word represents the column number or row number. Each line of the substitution (1) expression can be relatively easily converted into a sequence of control words (a kind of microprogram). By connecting a minicomputer or a microcomputer to this image storage device to generate word strings and load them into the control memory, all operations expressed in the form of substitution (1) can be executed. Note that if each control memory 3, 4, 5, and 6 shown in FIG. 1 has a sufficient depth, a shift operation can be performed by changing the load address of a word string. Also,
In the transposition operation, the contents of control memories 3 and 4 and control memories 5 and 6 are exchanged, counter 1 counts Lφ and is reset at Fφ, and counter 2 counts Mφ and is reset at Lφ. Just do it like this. For example, as an example of the operation of the present image storage device, an operation for vertically and horizontally inverting an image will be described. To do this, first, as shown in Figure 8,
Two image storage devices 20 (I ₁ , I ₂ ) of the present invention shown in FIG. 1 are used and connected in series. The image read from the first image storage device _I1 at the front stage is written to the second image storage device _I2 at the rear stage. The signals Mφ, Lφ, Fφ necessary for the operation of the system shown in FIG. 8 are commonly given from the control section shown in the figure, as described above. However, the permutations required for this operation are as follows.

[Table] In order to realize this replacement, according to the word structure shown in _FIG .
(FIG. 1), the control word strings in Table 2 are loaded into the control memory 5, and the other control memories 4 and 6 are cleared even if they are in the first image storage device _I1 . Similarly, the control word strings shown in hexadecimal notation as Table 3 below are shown in the control memory 4 of the second image memory device _I2 .
Then, the control word strings shown in Table 4 are loaded into the control memory 6, and the other control memories 3 and 5 in the second image storage device _I2 are cleared.

【table】

【table】

【table】

【table】

【table】

【table】

[Table] First, the operation of the first image storage device _I1 will be explained. First, counter 2 (FIG. 1) is reset by signal Fφ. Lφ is then generated, resetting counter 1 (FIG. 1) and at the same time counter 2
Increment the count value by "1". With this count value "1", the control word located in the word order "1" position in the control memories 5 and 6 is read out. As already mentioned, the control memory 5 of this first image storage device _I1
Regarding, from Table 2, at this time, RYC _{1 to 0}
=2, RYA _8~0 =0 control words are read.
This indicates that the control word is valid and also means that the Y coordinate at the time of reading is fixed to 0, that is, to the first row of the image. Regarding the control memory 6 of the first image memory device I ₁ ,
As mentioned earlier, since WYC ₁ =0, the read control word is invalid. Counter 1, reset by signal Lφ, counts signal Mφ. Due to the first Mφ, this count value becomes “1”, and the word order of control memories 3 and 4 becomes “1”.
The control word corresponding to is read out. At this time, for the control memory 3, from Table 1, R/W = 0, RXC _{2 ~ 0} = 4, RXA _{5 ~} 0 = 0, RBF _{2 ~ 0} = * (* is don't care; can be ignored) ) is read. This means that the first image storage device should be in a read state, that the control word is valid, and that the line specified by the current Y coordinate from the storage unit 18 (Fig. 1) (in the above case) indicates that the first eight pixels in the first row) should be read out. It takes 8τ to read out the first eight pixels from the storage section 18, so it is not necessary to control the output buffer 16 (FIG. 1) during this time. After 8τ, that is, when the count value of the counter 1 reaches "8", data for 8 pixels is read out from the storage section 18. 8th bit group in word order
For RXCCC _2-0 =5, the least significant bit of the bit group, RXC ₀ =1, indicates that this data should be written to the output buffer. When the count value is between "9" and "10", the next eight pixels of the corresponding row are read out from the storage section 18. At the same time,
Data is sequentially output from the output buffer one pixel at a time at a period τ. That is why RBF _2-0 varies from 0 to 7. As for the control memory 4 of the first image storage device I ₁ , WXC ₂ =0, as described above, and the read word is invalid. In this way, the counter 1 is incremented by Mφ, and the word order in the control memory 3 becomes 210.
When it reaches , reading of one line is finished, and since Lφ occurs at this time, counter 2 is incremented by "1", counter 1 is reset, and reading of the next line begins. Further, when the word order in the control memory 5 reaches 200 as a result of incrementing the counter 2 by Lφ, reading for one screen is completed. On the one hand, the operation of the first image storage device I ₁ is as follows:
The second image storage device I ₂ operates synchronously with the first image storage device I ₁ in order to receive pixels read out one after another from the first image storage device I ₁ . First of all, the counter 2 is reset by the signal Fφ, as for the first image storage device _I1 . Lφ is then generated, resetting counter 1 (FIG. 1) in this second image storage device _I2 and at the same time incrementing the count value of counter 2 by "1". With this count value "1", this second image storage device
The control word at the word order "1" position in the control memories 5 and 6 regarding _I2 is read out. At this time, regarding the control memory 6, from Table 4, the control words WYC ₁ to ₀ = 2 and WYA _{8 to 0} = 1FF are read out. This indicates that the control word is valid, and the Y coordinate at the time of writing is 1FF.
This means fixing it to the last line of the image. Regarding control memory 5, from what I said earlier,
Since RYC _1-0 = 0, the read control word is invalid. Counter 1, reset by signal Lφ, counts signal Mφ. Due to the first Mφ, this count value becomes “1”, and the word order of control memories 3 and 4 becomes “1”.
The control word corresponding to is read out. At this time, for the control memory 4, from Table 3, R/W = 1, WXC _{2 ~ 0} = 4, WXA _{5 ~ 0} = *, WBF _{2 ~ 0} = 7 (* is don't care; can be ignored. ) is read. This indicates that the second image storage device _I2 is in the state to be written, that the control word is valid, and that one pixel data should be written to address 7 of the input buffer 17 (FIG. 1). ing. By sequentially reading and executing the control words 1 to 8 in the control memory over a time period of 8τ, the data for the first 8 pixels read from the first image storage device _I1 is stored in the input buffer. written. WXC ₀ = 1 at the 8th word order is input buffer 17
This indicates that the contents of the file should be written into the storage unit 18 (FIG. 1). When the count value is between "9" and "10", 8 pixels are written into the storage section 18, and one pixel at a time is subsequently written into the input buffer from the first image storage device _I1 . Note that for the control memory 3 of the second image storage device I ₂ , RXC ₂ =0, and therefore the read control word is invalid. In this way, the counter 1 is incremented by Mφ, and the word order in the control memory 4 becomes 210.
When reaching , writing for one line is completed, and since Lφ occurs at this time, counter 2 is incremented by "1", counter 1 is reset, and writing of the next line begins. Further, if the word order in the control memory 6 reaches 200 as a result of incrementing the counter 2 by Lφ, then the processing for one screen is completed. In this way, the image stored in the second image storage device _I1 is stored in the second image storage device with its top, bottom, left and right reversed. Based on these examples, zooming and other
It can be seen that any desired image processing procedure is possible with a considerable degree of freedom using the apparatus of the invention. Further other system configuration examples will be described below. As is obvious, in the above practical application example, each counter is incremented by the main scanning signal of the image, but
Although this is a normal form, it is not limited to this, and it may be a decrement, as long as the counting contents are changed in a predetermined manner. Application examples in which the image storage device 20 is combined with an image input device, an image display device, and an image calculation device are shown in FIGS. 4, 5, and 6, respectively. In FIG. 4, signals Mφ, Lφ, and Fφ necessary for the operation of the image storage device 20 are supplied from a television camera control section 21. The output video signal of the television camera 22 is digitized by the AD converter 23 and input to the main image storage device 20. It is assumed that the television camera 22 captures images using interlaced scanning, and the size of the input image is 512 x 480 pixels. Captured image
If I ₁ and the image stored in the image storage device 20 are I ₂ , then according to equation (1),

[Table] By performing the following substitution, the input image can be stored in the image storage device 20 by converting interlaced scanning into sequential scanning. The first line of both permutations in equation (4) represents the pixel sequence of the input image. The second line can be realized by the control storage of the image storage device 20 as described above. The second row of column permutation in the control memory 4 of FIG.
It is sufficient to load the control word string corresponding to the second row of row replacement into the control memory 6. In FIG. 5, signals Mφ, Lφ, and Fφ necessary for the operation of the image storage device 20 are supplied from a television monitor control section 24. Output pixels from the image storage device 20 are converted into analog by a DA converter 25 and displayed on a television monitor 26. The image stored in the image storage device 20 is I ₁ , and the displayed image is I 1 .
If I ₂ , the image size is 512 x 512,

[Table] Just consider the following permutation. For this purpose, the control memory 3 shown in FIG. 1 is loaded with the first row of column permutation, and the control memory 5 is loaded with a control word string corresponding to the first row of column permutation. In the application example shown in FIG. 6, two image storage devices 20 (20a, 20b) shown in FIG. First image storage device 2
The image arithmetic unit 28 performs arithmetic operations on the output pixels from 0a, and the results are stored in the second image storage device 20b. As an example, if we consider an operation in which a constant value 1 is added to the image I ₁ in the first image storage device 20a and the resulting image I ₂ is transferred to the second image storage device 20b, the required replacement is This is equation (5). In the control memory of the first image storage device 20a, the control word string corresponding to the first row of both permutations in equation (5) is loaded into parts 3 and 5 in FIG. In the control memory of the storage device 20b, the control word string corresponding to the second row of both permutations in equation (5) is loaded into portions 4 and 6 in FIG. Note that, depending on the type of calculation, there may be a plurality of image storage devices 20a and 20b. Furthermore, one image storage device 20 may serve as both the functions of these image devices 20a and 20b. Inputs and displays shown in FIGS. 4, 5, and 6,
It is also possible to configure an image processing device that integrates calculation functions.
Figure 7 shows an example of such an application. Here, seven image storage devices are used (respectively 20 _-1 , 20 _-2 ,
……………20 (indicated by _-7 ). The image input section 30 includes the television camera 22, television camera control section 21, and AD converter 2 in FIG.
It is composed of 3 elements. This image input section 30 and each image storage device 20 _-1 to 20 _-4 are
Since they are combined using the method described in connection with FIG.
You can input images to _-1 to 20 _-4 . The image calculation unit 31 is constructed using the image calculation unit 28 and the image calculation control unit 27 shown in FIG. 6 as elements. Then, the image storage device 2 in FIG.
0 _-1 and 20 _-7 correspond to the output side image storage device 20a and the input side image storage device 20b in FIG. 6, respectively. Since the image calculation unit 31 in FIG. 7 and each image storage device are coupled in the manner described in connection with FIG. By using it as , calculation becomes possible. The image display section 32 includes the DA converter 25, the television monitor control section 24, and the television monitor 2 in FIG.
It is composed of 6 elements. Signals Mφ, Lφ, necessary for the operation of the image calculation unit 31, image display unit 32, and image storage devices 20 _-1 to 20 _-7 in FIG.
Fφ is common. Since the image display unit 32 is connected to the data line that inputs the output signal of the image calculation unit 31 to each image storage device, the image calculation unit 3
Displays the calculation result based on 1. If the operation of converting an input pixel directly into an output pixel is viewed as one operation, the contents of each image storage device will be displayed. As explained in detail above, the present invention preferably employs a high-speed control memory in the control section of an image storage device necessary for inputting, displaying, and calculating images, and controls information by image scanning signals. This not only simplifies the circuit, but also makes it possible to rewrite the contents of the control memory, at least in terms of address designation order, and preferably with regard to other information as well, so that it can be adapted to various usage modes. This provides an extremely effective means for configuring a processing device.

[Brief explanation of the drawing]

FIG. 1 is a schematic configuration diagram of an embodiment of the present image storage device, FIG. 2 is an explanatory diagram showing a coordinate system on an image, FIG. 3 is an explanatory diagram showing an example of the word structure of control memory, and FIG.
5 is a schematic configuration diagram of an example of an image input device, FIG. 5 is a schematic configuration diagram of an example of an image display device, FIG. 6 is a schematic configuration diagram of an image processing device as a first application example of this device, and FIG. The figure is a schematic configuration diagram of an example of application to an image processing device, and FIG. 8 is a system configuration diagram when two image storage devices of the present invention are used for image reversal or the like. In the figure, 3, 4, 5, 6 are control storage units, 18 is an image storage unit, 20, 20a, 20b, 20 _-1 to 20
_-7 is the image storage device as a whole.

Claims (1)

[Scope of Claims] 1. An image storage unit consisting of a pixel storage unit with multiple rows and multiple columns, and selectively writes and reads pixels to each of the pixel storage units corresponding to an address specified by addressing information. An image storage device that performs the following: A total of two counters are provided, one each corresponding to the X and Y coordinates of the image; Each of the two counters is controlled by the main scanning signal of the image. The contents of the count at that time are changed in a predetermined manner; By reading out the control word string scheduled to correspond to the time from the control memory that can be rewritten according to the content of the count at that time, the address at the time is changed. An image storage device characterized by: obtaining specified information;