JPS6143795B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a driving circuit system for a semiconductor circuit.
The present invention is applied to increase the speed of a drive circuit that drives a plurality of load semiconductor circuits, but in order to simplify the explanation below, a typical memory circuit will be particularly described.

[Background of the Invention] Conventionally, bipolar memories using flip-flop type memory cells often have a circuit configuration as shown in FIG. (For example, "Integrated Circuits (IC Technology Explanation)" published by the Japan Electronics Industry Promotion Association,
Structure and Characteristics of Domestic and Foreign ICs)” Material No. 47-M-82).

First, the operation of a conventional memory cell matrix will be briefly described with reference to FIG. In addition, the same figure is
Two rows and two columns of a matrix of memory cells are shown. In addition, Figure 2 shows the word line X in Figure 1.
0, X1, read reference voltage terminal R, write signal line W
1, W0, digit selection lines Y0, Y1, and the relationship between the collector voltages of the memory cells.

Here, the voltages of the word lines X0 and X1 are V _XH (V _XH represents the voltage level shown in FIG. 2; the same applies hereinafter) for the selected word line, and V _XL for the unselected word line. These voltage levels are the same during reading and writing. Moreover, the voltage of the read reference voltage terminal R is
When reading, it becomes V _RH and when writing, it becomes V _RL . The voltages of the write signal lines W1 and W0 are V _WL during reading, and depending on whether the written information is "1" or "0" during writing,
Either W1 or W0 becomes _WWH , and the other becomes _WWL . Furthermore, the digit selection lines Y0 and Y1 are driven to be V _YL for selected digit lines and V _YH for unselected digit lines. These voltage levels of the digit selection lines are the same during reading and writing.

In this case, each of the memory cells C ₀ to _{C 3} is composed of two cross-coupled transistors, and information is stored when one is turned on and the other is turned off. The collector voltage V _C1 of the off-side transistor of the memory cell, ie, the base voltage of the on-side transistor, is approximately equal to the voltage of the word lines X0, X1, which is V _XH or V _XL . In addition, the collector voltage V _C1 of the transistor on the on side of the memory cell, that is, the base voltage of the transistor on the off side, is calculated from the voltage of the word lines X0 and X1 by the current I _c flowing through the transistor that is on, and the collector resistance R. The voltage is lower by the voltage drop △V _N (when word line is not selected) and △V _S (when word line is selected) due to _L00 or R _L01 , etc.

Reading of information from memory cells is performed as follows. Now, assuming that word line X0 is at V _XH , X1 is at V _XL , digit selection line Y0 is at V _YL , and Y1 is at V _YH , only memory cell _C0 is in the selected state, and the remaining memory cells are in the unselected state. in a state. Further, it is assumed that in the memory cell C ₀ in the selected state, for example, Q ₀₀ is on, Q ₀₁ is off, and information "0" is stored.

The current Q _R00 flowing through the current source Q _R00 flows from one of the transistors connected to the digit line D ₀₀ . In this case, the transistors connected to the digit line D ₀₀ are Q ₀₀ , Q ₁₀ , Q _ref00 , Q _W00 , and Q _Y00 , and their base voltages are V _XH and V _{XL ,} respectively.
(or V _XL -ΔV _N ), V _RH , V _WL , and V _YL , and the highest voltage among these is V _XH as shown in FIG. 2, so I _R00 flows from Q ₀₀ . Therefore, Q _ref00 is turned off, and the collector of Q _ref00 is at a high potential (earth potential).

On the other hand, the current I _R01 flowing through Q _R01 is the transistor _{Q 01 ,} Q ₁₁ , Q _ref01 , Q
The current will flow due to either _W01 or Q _R01 , and the base voltage of each transistor is V _XH −△V
_S , V _XL (or V _XL -△V _N ), V _RH , V _WL , V _Y
The highest voltage among these is V _RH as shown in _FIG . Therefore, at this time I _R0
1 flows from Q _ref01 . Therefore, the collector voltage of Q _ref01 becomes a low potential (approximately -I _R01 ×R _S01 ).

Furthermore, the information of memory cell C ₀ is "1", that is,
When Q ₀₀ is off and Q ₀₁ is on, the collector of Q _ref00 has a low potential and the collector of Q _ref001 has a high potential. In this way, the information of the memory cell C ₀ is read out as the collector voltage of the transistors Q _ref00 and Q _ref01 .

On the other hand, for the unselected digit lines D ₁₀ and D ₁₁ , the potential applied to the digit selection line Y1 is V _XH , which is higher than the base voltage of any other transistor, so Q
The currents I _R10 and I _R11 flowing through _R10 and Q _R11 are respectively Q
_Y10 , Q Flows from _Y11 . Therefore, Q _ref10 , Q _re
No current flows through _f11 , the collectors of these transistors both have a high potential, and no information is read from the memory cell.

Writing to a memory cell is performed as follows. Now, digit selection line Y0 is V _YL , Y1 is V _YH , word line X0 is V _XH , X1 is V _XL , and the memory cell
Consider the case where C ₀ is selected and "1" is written to this cell. For this purpose, write signal line W0 is W _WH
and let W ₁ be V _WL . Since V _WH is higher than the base voltage of the two transistors of the selected memory cell C ₀ and V _WL is lower than the above base voltage, the current flowing through Q _R00 is Q regardless of the information in the memory cell. The current that flows from _W00 and flows through Q _R01 flows from Q ₀₁ . Here, I _R is larger than V _st , so the on/off state of the transistor is determined by I _R , so the transistor Q ₀₀ of memory cell C ₀ is turned off and Q ₀₁ is turned on, resulting in "1". is written.

In addition, when writing "0", set W1 and W0 to V _WH and V _WL respectively, and turn on Q ₀₀ in the same way.
Turn Q ₁₁ off. In non-selected digits, the base of Q _Y10 and Q _Y11 is V _YH .
At this time, from Figure 2, V _YH is the highest potential among the base voltages of the transistors connected to the digit line, so the currents flowing through Q _R10 and Q _R11 are respectively Q _Y
10 , Q flows from _Y11 , so the state of the cell does not change.

By the way, in a conventional cell as shown in FIG.
This is performed using a constant current (holding current V _st ) flowing through constant current source transistors such as _ST0 and Q _ST1 . on the other hand,
Reading and writing are performed, for example, by a constant current (read/write current I _R ) flowing through Q _R00 to Q _R11 .
While I _st flows through all memory cells (N),
Since I _R only needs to flow in the number corresponding to one side of the memory cell matrix (the number of columns (α√), the total current flowing in the memory cell matrix is I _tptal = NI _st + α√I _R However, α is a constant determined by the aspect ratio of the matrix (when the matrix is square, α=2).

Normally, the upper limit of I _tptal is set from the viewpoint of heat dissipation of the package, so the bit capacity of the memory N
When N becomes large, I _st and I _R must be made small, and in particular, I _st has no choice but to be made small in inverse proportion to N. Therefore, as N increases, the current flowing through the word lines X0, X1, etc. and the holding current lines X _st 0, X _st 1, etc. decreases by approximately 1/√.

On the other hand, the number of memory cells connected to the word line X0 etc. increases in proportion to √, so the load capacitance increases
increases in proportion to As a result, X0, X _st 0
The switching speed, especially the falling time, of such signals increases approximately in proportion to N. An example of this is shown in FIG. 3, which shows the signal waveforms of the word line X0 for the case of N small and for the case of N large. The line of X _st 0 etc. has a similar tendency and N
When becomes large, the rising and falling edges of the signal are delayed. This increases the access time of the memory circuit.

In this case, the delay in rising can be achieved by improving the base resistance r _bb ' of the emitter follower transistor (that is, by improving the layout of the device). However, on the falling side, the current value is essentially I
Since it is determined by _st and the load connected to this auxiliary current line, the essential solution is to increase the current value.

The current in the word line X0 can also be increased by increasing the read current I _R as disclosed in Japanese Patent Laid-Open No. 48-61036. However, in the case of the circuit shown in FIG. 1, although it is possible to make the upper word line X0 fall faster, the lower word line X _st 0
etc. cannot be improved, and there is a strong possibility that this will lead to information destruction.

Therefore, the way to improve the falling of the word lines X0, X _st 0, etc. is to increase I _st itself. However, increasing all I _st is impossible in terms of power consumption as described above. A technique for solving this problem is the I _st concentration technique described in Japanese Patent Laid-Open No. 126335/1983, that is, a method of flowing a large amount of I _st only to selected word lines. FIG. 4 shows the waveform of the voltage change on the word line X0 when this method is used. Here, 42 shows the waveform, and compared to the waveform 41 when the same I _st is applied to all word lines,
It is true that the decline is becoming faster. However, it becomes parallel to 41 from the middle of the fall, and the speed is not increased much after all. This known technique flows I _st only to the selected word line and only when selected, and since I _st is not flowed intensively at the falling edge, it hardly contributes to speeding up the falling edge. Of course.

[Purpose of the invention]

An object of the present invention is to speed up the fall of word lines and holding current lines of a memory circuit, thereby shortening the access time of the memory circuit.

[Summary of the invention]

In order to achieve the above object, the present invention provides at least a transient period after applying a selection voltage to an upper word line and from when the word line is non-selectively switched until the voltage on the upper word line becomes a non-selection voltage. The middle one is provided with a current applying circuit that makes the current in the upper word line larger than when it is not selected.

[Embodiments of the invention]

Next, the present invention will be explained with reference to examples. FIG. 5 is an explanatory diagram of the basic concept of the present invention.
00 is a memory cell, and 110 and 111 are word lines. The level _VX of the selected word line switches from the low level _VXL to the high level _VXH as described above. V _X then switches from selected (V _XH ) to non-selected (V _XL ). This switching is detected by the circuit 101. Although FIG. 5 shows that this switching is detected from _{the V} It may also be detected.

The detected signal is appropriately delayed or widened in pulse width by circuit 102, changed to an appropriate level, and sent to current switch circuit 103. The output of circuit 102 holds its output level until word line 110 completely settles to the holding level. Therefore, current switch circuit 103 continues to supply current at least from the moment _VX switches from selection to non-selection until _VX settles to a sufficiently low level. Although this current is shown in FIG. 5 as flowing in parallel with I _st current source 121, it may also flow directly from word line 110 in some circuits.

Next, FIG. 6 shows an embodiment of the present invention that implements the concept of FIG. 5.

In this example, Emitsuta follower Q ₂₀₁ is word line 11.
Detect whether 0 is at high level. This signal is applied to the base of the emitter follower Q ₂₀₃ at an appropriate level due to the voltage drop across the resistor R ₂₀₁ . The base voltage of Q ₂₀₃ is the current source transistor
It can be changed arbitrarily by setting the base voltage V _CS of Q ₂₀₂ and the emitter resistance R ² ₀₂ to appropriate values. The output of Emitsuta Follower Q ₂₀₃ is a current source transistor
Q applied to ₂₀₄ , turning on this transistor.

In this embodiment, by choosing an appropriate value for R ₂₀₃ or R ₂₀₁ , the signal delay time can be appropriately selected, so that the output of Q ₂₀₃ remains constant even after V _X switches to a low level. It is held for an appropriate amount of time, during which current continues to flow through Q ₂₀₄ . This current may flow to two word lines only while being delayed, but basically it flows only to the selected word line, so it can be made sufficiently larger than I _st . Therefore, _VX can fall quickly. Therefore, when no delay circuit is inserted in Figure 4, the speed is increased only to the extent shown by curve 42, but when the circuit in Figure 6 is used, the speed is increased as shown by the waveform shown by curve 43. be done.

Note that in FIG. 6, the resistance values of Q ₂₀₃ and R ₂₀₁ are selected to be large in order to provide a delay effect, so that the power consumed in this circuit can be extremely small. In addition, _Q204 is turned on quickly at the rising edge of a word line, expanding the operating margin as described in JP-A-50-126335, and providing a delay effect only at the falling edge of the word line to increase speed. If this is desired, R ₂₀₁ should be made small and only R ₂₀₃ should be made large to provide a delay effect. In this case, the Emitsuta Follower Q ₂₀₃ responds quickly at the rising edge, but responds very slowly at the falling edge, which can accomplish the purpose.

FIG. 7 shows another embodiment of the invention. In addition
Q ₄₀₅ and Q ₄₀₆ constitute a V _X generation circuit. _Q405
signal extracted from the collector of (opposite phase to _V
is applied to the base of the pnp transistor _Q401 through the resistor R401, making it conductive. When Q ₄₀₁ conducts, a signal appears at its collector, turning on current source transistor Q ₄₀₂ . In this embodiment, signal delay is performed by R ₂₀₁ and C ₄₀₁ (C ₄₀₁ and C ₄₀₂ are floating capacitances or external capacitances) or R ₄₀₃ and C ₄₀₂ . Needless to say, in an actual circuit, only one of these is sufficient. Also pnp transistor Q ₄₀₁
As such, if you use a transistor with aggressively slow response (e.g. a lateral pnp transistor),
There is no need to use delays due to R and C.

In the embodiments described above, current continues to flow through the selected word line while it is selected and for some time after it is switched to non-selection. However, if you just want to speed up the fall,
It is only necessary to increase the current from immediately after switching from selection to non-selection until V _X becomes sufficiently low. One such embodiment is shown in Figure 8a.

Here, Q ₆₀₃ and Q ₆₀₄ constitute a V _X generation circuit. V _X applied to word line 110 is applied to delay circuit 603
AND gate 60 is delayed by a time t _d by
4 input 605. On the other hand, the negative phase signal of _VX is applied to the input ₆₀₁ of the AND gate 604 via the emitter follower Q601. The waveforms appearing at inputs 601 and 605 are shown in Figure 8b.
AND gate 604 delivers an output 606 for only t _d as shown, turns on transistor Q ₆₀₂ , used as a current switch, and conducts current to _V
Speed up the fall of .

In the above description, the present invention has been described using a bipolar memory as an example, but the present invention is not limited to this, but can be widely applied to semiconductor memories in general, and its effects are extremely large.

〔Effect of the invention〕

According to the present invention, it is possible to speed up the fall of a word line to which a selection voltage is applied during selection to a non-selection voltage, and it is possible to shorten the access time of a memory circuit.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of the memory device, FIG. 2 is an explanatory diagram showing voltage levels to explain the circuit operation of FIG. 1, FIG. 3 is a waveform diagram showing the characteristics of the circuit in FIG. 1, and FIG. The figures are waveform diagrams showing the characteristics of the conventional circuit and the circuit of the present invention. Fig. 5 is a configuration diagram for explaining the concept of the present invention. The configuration diagram, FIG. 8b, is a voltage waveform diagram of the main parts of FIG. 8a. 100: Memory cell, 101: Fall detection circuit, 102: Delay or pulse expansion circuit, 10
3: Current switch circuit, 110, 111: Word line,
121: Current source.

Claims (1)

[Scope of Claims] 1. (a) A plurality of word line pairs, each word line pair consisting of a pair of upper and lower word lines, and (b) The above words. In a semiconductor circuit comprising: a plurality of memory cells connected between word lines in a line pair; and (c) means for selectively applying a selection voltage to an upper word line of one of the plurality of word line pairs. , after applying a selection voltage to the upper word line in the word line pair selected by the voltage applying means, a transient period from at least switching that word line to non-selection until the voltage of the upper word line becomes the non-selection voltage; A semiconductor circuit characterized by being provided with a current application circuit that makes the current of the lower word line corresponding to the upper word line larger than when not selected throughout the period. . 2. In the semiconductor circuit according to claim 1, the current applying circuit includes a circuit for detecting switching from a selected state to a non-selected state of the upper word line of each word line pair, a constant current source, and A semiconductor circuit comprising a switch circuit that selectively causes a current from the constant current source to flow through a lower word line with respect to an upper word line whose switching is detected by the detection circuit. 3. The semiconductor circuit according to claim 1, including a circuit for delaying the selection signal by the voltage applying means, a constant current source, and a lower side of the selected word line pair limited by the output of the delay circuit. A semiconductor circuit comprising: a switch circuit that causes a current from the constant power source to flow through the word line for a predetermined period of time. 4. The semiconductor circuit according to claim 3, wherein the delay circuit is configured such that when the selection signal is input, the delay circuit rises with approximately the same rise time as the selection signal, and has a fall time larger than the fall time of the selection signal. What is claimed is: 1. A semiconductor circuit comprising a circuit that generates a signal that rises and then falls.