JPS6144247B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic integrating meter testing device for inspecting the offset state and starting characteristics of an integrating meter that transmits pulses with a frequency proportional to the magnitude of a measured quantity such as electricity, gas, water, etc. It is something.

In this type of integrating meter, power supply voltage is always applied to the electronic circuit so that the measured quantity can be measured at any time, regardless of the presence or absence of input. There has been a phenomenon in which an output is generated on the output side of a measurand quantity detection circuit configured with the above, or on the output side of a frequency conversion circuit that converts the output of the measurand quantity detection circuit into a frequency. This phenomenon, called offset, is caused by variations in electronic components constituting the measurand quantity detection circuit or frequency conversion circuit, leakage current, or operation of one or several electronic circuits. If there is an offset, the electronic integrating meter will measure the apparent measured quantity due to the offset, even though the input measured quantity is actually zero. In order to prevent erroneous measurements due to offset, offset adjustment is performed to cut off the output of the measurand quantity detection circuit or frequency conversion circuit below a certain low value. As a result, under general conditions,
Even if the quantity to be measured rises slightly from zero, the quantity to be measured may not be measured, and it becomes necessary to standardize the lowest input at which the metering operation must be reliably started as an integrating meter. In other words, this type of integrating meter must not perform a metering operation (pulse transmission) when the input is zero, and must definitely start the metering operation (pulse transmission) at a certain amount when the input has slightly increased from zero. Must. To check whether these conditions are met,
Offset check to see how many pulses are output within a preset time when the input is zero, and the time required for one cycle of output pulses when the minimum input to start the metering operation is given. An inspection device is required to perform a start-up check.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an electronic totalizer tester capable of performing offset checks and start-up checks on electronic totalizers.

Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 shows a block diagram of one embodiment of the invention.
A test instrument is connected to input terminal _t1 . First, the case of offset check will be explained with reference to the time chart of FIG. The test instrument is kept in a state where no input is applied, that is, a state in which the measured quantity is zero. Offset check selection terminal t ₂ of switching circuit 1
When a selection signal is applied to the RS flip-flop FF1 and the RS flip-flop _FF1 is set, the output of its output terminal Q becomes high level and the AND gates _G3 and _G5 are opened.
On the other hand, since the output of the output terminal is low level,
AND gates G ₄ and G ₆ are closed. Therefore, the pulse from the supply meter input to input terminal _t1 is
Input circuit 2 that adjusts the input level and shapes the waveform
The signal passes through an AND gate _G3 and an OR gate _G7 , and is applied to the first gate circuit _G1 . Further, a low frequency (for example, 1 pulse/minute) offset check reference pulse _P01 outputted from the reference pulse generation circuit 3 passes through an AND gate _G5 and is applied to the second gate circuit _G2 . The preset counter 4 is preset with a specified number of pulses corresponding to the offset check time. Preparation is complete in this state. Next, when an external start signal is applied to the external start signal input terminal _t4 , the external start signal is input to the control circuit 5, and the control circuit 5 outputs pulses _P1 , P2 _.
are output one after the other. The counting circuit ₆ and the preset counter ₄ are reset by the output pulse P1, and the first gate circuit _G1 and the second gate circuit _G2 are simultaneously opened by the output pulse P2. Therefore, the pulse from the test instrument is input to the counting circuit 6 via the input terminal t ₁ , the input circuit 2, the AND gate G ₃ , the OR gate G ₇ and the first gate circuit G ₁ , and is counted by the counting circuit 6. The count value is displayed on the display section 7. On the other hand, by opening the second gate circuit _G2 , the offset check reference pulse _P01 is input from the reference pulse generating circuit 3 to the preset counter 4 and counted. Preset counter 4
When the count value reaches the preset value, it outputs a narrow output pulse _P3 , and this pulse _P3 causes the control circuit 5 to stop outputting the output pulse _P2 .
Close the gate circuit _G1 and the second gate circuit _G2 .
As a result, the counting circuit 6 stops counting, and the display section 7
displays the number of pulses output by the meter under test until the reference pulse _P01 for offset check reaches the specified number of pulses, that is, within the predetermined offset check time. From this display, it is possible to know whether or not the test meter has erroneously measured and the magnitude of the erroneous measurement.

A starting check can be performed by applying a selection signal to the starting check selection terminal _t3 . During the start-up check, the lowest input that is required to ensure the start of metering operation is applied to the test meter connected to input terminal _t1 . Since the preset counter 4 is not used, there is no need to preset it. When a selection signal is input to the start check selection terminal _t3 , the RS flip-flop _FF1 is reset and the AND gates _G3 ,
_G5 closes and AND gates _G4 and _G6 open. When an external start signal is applied to the external start signal input terminal _t4 , the external start signal is input to the control circuit 5. Since the control circuit 5 receives a high level signal from the output terminal of the RS flip-flop FF ₁ , in this case, it does not output the output pulses P ₁ and P ₂ one after another due to the input of the external start signal. Then, as shown in FIG. 3, only the output pulse _P1 is output, and the counting circuit 6 and preset counter 4
Reset. After that, when the first pulse from the supply meter is outputted from the switching circuit 1 as the control circuit driving signal P ₄ via the input terminal t ₁ , the input circuit 2 and the AND gate G ₄ , this signal P ₄ becomes The signal is input to the control circuit 5 via the OR gate _G3 , and the control circuit 5 outputs an output pulse _P2 . The output pulse P ₂ opens the first gate circuit G ₁ and the second gate circuit G ₂ .
When the first gate circuit _G1 opens, the reference pulse _P02 for starting check is input from the reference pulse generation circuit 3 to the counting circuit 6 via the AND gate _G6 , the OR gate _G7 and the first gate circuit _G1 , and is counted. ,
The count value is displayed on the display section 7. The starting check reference pulse P ₀₂ is of high frequency, for example 100 pulses/second. The second pulse of the test instrument passes from the input terminal _t1 through the AND gate _G4 , is outputted from the switching circuit 1 as the control circuit drive signal _P4 , and is input to the control circuit 5 via the OR gate _G8 .
Causes the control circuit to stop outputting the output pulse _P2 . This closes the first gate circuit _G1 and the second gate circuit _G2 . The counting circuit 6 stops counting, and the display section 7 shows the time during which the first gate circuit _G1 was open, that is, the time required for one cycle of the output pulse of the test meter. By knowing this time, it is possible to know whether or not the instrument under test is emitting ultra-low frequencies, and its frequency.

FIG. 4 shows another embodiment of the present invention, and only the parts different from the embodiment of FIG. 1 are shown. In this embodiment, the average time per cycle can be determined by counting the time during which a given number of pulses are output from the instrument under test during the start-up check. In this embodiment, the preset counter 4 is preset to the specified number of pulses n of the meter under test even during a start-up check. The high level signal at the output terminal of the RS flip-flop _FF1 is applied to the input terminal J of the JK flip-flop _FF2 , and the input terminal K is set to the low level. In response to the external start signal, the control circuit 5 outputs an output pulse _P1 , which resets the counting circuit 6 and the preset counter 4, and also resets the JK flip-flop _FF2 . The first pulse from the input terminal _t1 is outputted from the AND gate _G4 as the control circuit driving signal _P4 , inputted to the input terminal CL of the JK flip-flop _FF2 , and sent to the preset counter 4 via the OR gate _G9 . input. JK flip flop
FF ₂ changes the output of the output terminal Q from low level to high level in synchronization with the rise of signal P ₄ , and due to this change, single pulse generation circuit 8 controls one pulse via OR gate G ₈ . Send to circuit 5.
As a result, the control circuit 5 outputs an output pulse _P2 , which opens the first gate circuit _G1 and the second gate circuit _G2.The second and subsequent pulses from the input terminal _t1 are the control circuit drive signal P2. ₄ is inputted to the preset counter 4 via the OR gate _G9 , and the preset counter 4 counts these pulses. When the count value reaches the preset value n, the preset counter 4
outputs an output pulse _P3 , which causes the control circuit 5
stops the output of the output pulse _P2 , and the first gate circuit
Close _G1 and the second gate circuit _G2 . Counting circuit 6
stops counting, and the display section 7 shows the first gate circuit.
It shows the time that G ₁ is open, that is, the time required for (n-1) periods of the output pulse of the test instrument. Therefore, if the displayed count value is divided by (n-1), 1
The average time per cycle can be determined and a more accurate starting check can be performed.

During an offset check, it takes a long time to strictly confirm whether or not the instrument under test is transmitting signals. , it is practical to consider it acceptable as long as it is not emitted during this period or as long as it is less than a few pulses. Note that the AND gate _G5 and the second gate circuit _G2 can be replaced with one AND gate having three input terminals.

According to the present invention, when performing an offset check, the input to the instrument under test connected to the input terminal is set to zero, and the preset counter is preset to a specified number of pulses corresponding to a predetermined offset check time. Therefore, the number of pulses emitted by the test instrument during the offset check time can be counted by the counting circuit, and the offset check can therefore be performed. In addition, during the start check, by setting the minimum input to start the weighing operation to the test meter connected to the input terminal, it is possible to control the The number of reference pulses for a starting check can be counted by a counting circuit and a starting check can therefore be carried out.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention;
FIG. 2 is a time chart during the offset check, FIG. 3 is a time chart during the start check, and FIG. 4 is a block diagram showing a part of another embodiment of the present invention. 1...Switching circuit, 3...Reference pulse generation circuit, 4...
Preset counter, 5...Control circuit, 6...Counting circuit, 7...Display section, _t1 ...Input terminal, _t2 ...Offset check selection terminal, _t3 ...Start check selection terminal,
t ₄ ...External start signal input terminal, _G1 ...First gate circuit, _G2 ...Second gate circuit, _P4 ...Control circuit drive signal, _P01 ...Reference pulse for offset check, _P02 ...For start check Reference pulse.

Claims (1)

[Claims] 1. An input terminal into which pulses from the test instrument are input, a reference pulse generation circuit that generates a reference pulse for offset check and a reference pulse for start check, a first gate circuit, a second gate circuit, and a first gate. A counting circuit that counts pulses passing through the circuit, a display section that displays the counted value of the counting circuit, and a second
A preset counter that counts the pulses passing through the gate circuit and outputs an output pulse when the counted value reaches a preset value, and a reference pulse generation circuit that sends the pulse from the input terminal to the first gate circuit at the time of offset check. The reference pulse for offset check is sent to the second gate circuit, and at the time of start check, the pulse from the input terminal is output as a signal for driving the control circuit, and the reference pulse for start check of the reference pulse generation circuit is sent to the first gate circuit. The counting circuit and the preset counter are reset by receiving an external start signal during an offset check, and then the first gate circuit and the second gate circuit are opened to receive the output pulse of the preset counter. The first gate circuit and the second gate circuit are closed, and at the time of start check, the counting circuit and preset counter are reset by receiving an external start signal, and then the first pulse from the input terminal is sent from the switching circuit to drive the control circuit. The first gate circuit and the second gate circuit are opened when the pulse is output as a signal, and the first gate circuit and the second gate circuit are opened when a predetermined pulse from the input terminal is output as a control circuit drive signal from the switching circuit. An electronic integrating meter inspection device equipped with a control circuit that controls the closing of the meter.