JPS6144340B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information processing apparatus equipped with a data buffering function, and more particularly to an information processing apparatus that can arbitrarily set the width of data taken into a data buffer.

As shown in FIG. 1, a processing device that plays a central role in an information processing system is composed of a central processing unit CPU, a main storage device MS, and a channel CH. The main storage device MS stores information (data and programs) processed by the central processing unit CPU and the channel CH. When activated by the central processing unit CPU, the channel CH independently controls the input/output device IO and causes information to be exchanged between the input/output device IO and the main storage device MS.

The configuration of the central processing unit CPU differs depending on the model, but for example, as shown in Figure 1, the arithmetic control unit
It is functionally divided into EU, instruction control unit IU, storage control unit SCU, input/output processing unit IOP, and service processing unit SVP. When the storage control unit SCU reads an instruction from the main memory MS, the instruction control unit IU temporarily stores the instruction in the buffer storage and then sequentially reads the data.
The instruction is loaded into the buffer register, and preparations are made to execute the instruction in the arithmetic control unit EU.

In this case, if the basic data width of the central processing unit CPU is m, the instruction control unit IU generally
Data read width from buffer storage device is n×m
The unit width when taking data into the buffer register is also n×m. And Batsuhua
When the capacity of the register is k×n×m, the amount of increase in the address for reading data from the buffer storage device is usually n×m. For example, if the buffer register is k×n×m (3×4×
8 bytes), the amount of instructions read from the buffer storage device into the buffer register at one time is n x m (4 x 8 bytes), and the read address from the buffer storage device is n x m (4 x 8 bytes). The determined increment amount of the address incrementer is also n×m (4×8 bytes).

However, in such conventional buffer registers, all buffer registers are empty, that is, k×n×
Even if m data can be taken in, the buffer register cannot be filled unless n×m data are read k times from the buffer storage device. In addition, when the buffer register is filled, that is, when k×n×m data has already been taken into the buffer register,
Even if j×m (1j<n) data is read from the buffer register and processed, if j
You cannot begin reading the next data from the buffer storage until . In other words, in FIG. 2, when the buffer register of 3 x 4 x 8 bytes is filled, 8 bytes of A1,
Even if 16 bytes of A1 and A2 or 24 bytes of A1 to A3 are read for processing and become empty, the buffer registers will not be filled until all 32 bytes of A1 to A4 are read. Data cannot be imported. This also applies to each data of B1 to B4 and C1 to C4 in FIG.

As described above, in the data buffering operation, there are two types of requests: a request to increase the data read width from the buffer storage device and a request to decrease the data read width, and these are contradictory to each other.

An object of the present invention is to solve such problems, to satisfy conflicting demands regarding data width when reading data from a buffer storage device, and to arbitrarily set the data width to be read into a buffer register. The object of the present invention is to improve the buffering efficiency of buffer registers.

In the present invention, the data width when data is taken into the buffer register and the increment amount of the read address from the buffer storage device are made variable, and the free space in the buffer register is detected and fed back to the address incrementer. The above objective is achieved by determining the address increase amount thereby.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 3 is a schematic block diagram of a buffer device according to the invention.

In the present invention, as shown in FIG. 3, the buffer storage device BM is divided into two, an even number BM.E and an odd number BM.O. The contents of the instruction address register IAR are incremented by the address incrementer AI and updated via the address latch AL. The amount of address increase is specified by the instruction address control unit IAC. The address of the instruction address register IAR is incremented by the address incrementer AD at the same time as one buffer memory BM/E is accessed and data is read into the instruction buffer register IBR/A. Access the memory BM/O and transfer the data to the instruction buffer register.
Read to IBR・B. The instruction to increase is given by the logical address control unit LAC. Instruction buffer register
The contents of IBR.A and IBR.B are extracted under the control of pointer PT and taken into register REG.
In addition, the increase amount of the increaser AD is the buffer storage device.
Equal to the width of data read from BM.E or BM.O at one time. Further, the amount of increase in the address incrementer AI is equal to the amount of increase in the incrementer AD, or is equal to a multiple thereof.

If both instruction buffer registers IBR・A and IBR・B are empty, the data indicated by the address of address register IAR is transferred to buffer storage device BM・E.
and BM.O, and can be loaded into buffer registers IBR.A and IBR.B at the same time. Also, if one of the instruction buffer registers IBR・A or IBR・B is empty, the data indicated by the address of the address register IAR is read from either buffer storage device BM・E or BM・O and the buffer register IBR・B is empty. A or IBR・
It can be taken into one side of B. The instruction buffer control unit IBC detects the empty status of buffer registers IBR・A and IBR・B, and the instruction address control unit
By notifying the IAC, the amount of increase in the address incrementer AI is determined.

FIG. 4 is a detailed block diagram of FIG. 3.

In Figure 4, the maximum width of data that can be read in one data read operation is n x m (2 x 8 bytes).
buffer storage units 6 and 7, and 8 bytes or
Instruction buffer registers 67, 68, 73, 7 that can take in data with a data width of 16 bytes
4 and 167, 168, 173, 174 and 8
Instruction address incrementers 61 and 16 that can increase the instruction read address by byte or 16-byte values
1 will be explained as an example.

When the start of the first instruction read is instructed from the arithmetic control unit EU via the control line 1, the instruction stream control unit 2 starts the initial value setting operation for instruction read.

In FIG. 4, two streams are used. Initially, the A stream having circuits 51 to 85 operates, and when a branch instruction or a branchable execution instruction is set in the instruction register 18, 15
A B stream with 1 to 185 circuits operates.

The instruction stream control unit 2 sets the instruction read start address sent from the data line 3 in the instruction address register 52 and instruction extraction pointer 53 via the control line 51. For example, if the blocks in the buffer storage units 6 and 7 are 64 bytes as shown in FIG. 5a, the first 8 bytes
Set which 8 bytes from (0) to the last 8 bytes (7) the address starts from.

Furthermore, the command address control section 54 is activated by the control line 51. Instruction address control unit 54
As a result, an instruction read request signal is sent to the logical address control unit 4 via the control line 55.

When the logical address control unit 4 has not received another request with a high priority, it accepts the request and returns an instruction read acceptance signal to the instruction address control unit 54 via the control line 56. By setting this accept signal, the contents of the instruction address register 52 are transferred to the logical address register 5 via the data line 57, and after a certain period of time, the contents of the instruction address register 52 are transferred from the instruction address control section 54 to the control line 58.
By setting , the contents of instruction address latch 59 are transferred to instruction address register 52 via data line 60. The instruction address latch 59 is set to a value obtained by increasing the contents of the instruction address register 52 by the instruction address incrementer 61. This amount of increase is determined by the instruction address control section 54, which sets the control line 62 when increasing the address by 8 bytes, and sets the control line 63 when increasing the address by 16 bytes. This is because the instruction buffer control unit 69 controls the instruction buffer register 6.
7, 68 is detected and the control lines 64, 6 are connected.
5, the instruction address control unit 54 is notified. The address increase amount is determined based on control lines 64 and 65 and data line 66. The control line 64 is detected and set by the instruction buffer control unit 69 when the instruction buffer register 67 is in an empty state, and the control line 65 is detected and set when the instruction buffer register 68 is in an empty state. Further, data line 66 indicates the contents of the lower three bits (3.2 to 3.4) of instruction address register 52.

As shown in FIG. 5B, the instruction address register 52 is set with a 32-bit instruction address of bits 0.0 (0th bit of the 0th byte) to 3.7, but bits 2 and 3 of the third byte are set in the instruction address register 52. 3,4
indicates the 8-byte address in the block of buffer storage units 6 and 7, that is, which 8 bytes among the 64 bytes shown in FIG. This is a display bit that indicates.

For example, when the lower three bits (3.2 to 3.4) are all "1", this indicates that the instruction address specifies the last 8 bytes of 64 bytes, which is one unit of buffer storage sections 6 and 7. In this case, only 8 bytes can be read by one buffer storage section access.

The instruction address control unit 54 uses control lines 64 and 65
are set together, and the data line 66
When all three bits of ``1'' are not ``1'', 16 bytes can be read by one access to the buffer storage section, so the control line 63 is set and the instruction address is increased by 16 bytes.

On the other hand, if only one of the control lines 64 and 65 is set, or if all three bits (3.2 to 3.4) of the data line 66 are "1", the control line
2 is set to increase the instruction address by 8 bytes.

The control lines 62 and 63 are connected to the command buffer control section 69.
(not shown), and notifies the effective instruction data width that can be read from the buffer storage units 6 and 7.

When the instruction read request signal issued by the instruction address control section 54 is accepted by the logical address control section 4, the address translation device 8 is processed according to the logical address set in the logical address register 5.
The buffer indexing device 9 is referred to. If a real address corresponding to a logical address is registered in the address translation device 8, and if the real address is registered in the buffer indexing device 9, the data specified by the logical address can be immediately read from the buffer storage units 6, 7. I can do it.

The buffer storage device includes a buffer storage unit 6 that stores even-numbered 8-byte data indicated by E in FIG. 5a.
and a buffer storage section 7 for storing odd-numbered 8-byte data indicated by O, and each of the 8-byte data can be read in one access.

The read address of the buffer storage device is created by the output of the address translation device 8 and the output of the buffer index device 9, and is created by the output of the address translation device 8 and the output of the buffer indexing device 9.
It is set above 11. Buffer address register E10 and buffer address register E10
The upper address of register O11 is block (64
(byte) address. On the other hand, the lower 3 bits of buffer address register E10 and buffer address register O11 are as follows:
Indicates the address of 8-byte data within the block. That is, the address in which one block (64 bytes) shown in FIG. (3.2 to 3.4) are stored as is or after being processed and stored as buffer address register 1.
It is set to the lower order of 0 and 11.

Address of logical address register 5 is even number 8
When within a byte boundary, the bits (3.2-3.4) of logical address register 5 are incremented by zero in incrementer/decrementer E12 and stored in buffer address register E1.
It is set lower than 0, and the increase/decrease O13
is incremented by 8 and set in the lower part of buffer address register O11. That is, in this case, (0, 1), (2, 3),
(4,5) or (6,7) even number 8 bytes E
Since it is 16-byte data starting with , add 8 to the odd-numbered 8-byte address. Therefore,
The first 8 bytes of the instruction data designated by the logical address register 5 are read from the buffer storage E6, and the latter 8 bytes are read from the buffer storage O7.

Conversely, when the address of logical address register 5 is within an odd 8-byte boundary, the bits (3.2 to 3.4) of logical address register 5 are incremented by 8 in increment/decrement E12 to become buffer address register 5.
It is set to the lower part of register E10, and
It is incremented by 0 by the incrementer/decrementer O13 and set in the lower part of the buffer address register O11. At this time, the latter half 8 of the instruction data specified by the logical address register 5 is sent from the buffer storage section E6.
Bytes are read out, and the first 8 bytes are read out from the buffer storage section O7.

The increase/decrease units 12 and 13 are controlled using the control line 14 when the logical address control unit 4 receives an instruction read request signal via the control line 55. Further, when the logical address control unit 4 receives the instruction read request signal, it sends an instruction read accept signal back to the instruction address control unit 54 via the control line 56, and at the same time activates the buffer control unit 15. The buffer control unit 15 sends a control line 16 indicating that a real address corresponding to the logical address is registered in the address translation device 8 and a control line 17 indicating that the real address is registered in the buffer indexing device 9. Accordingly, the buffer storage units 6 and 7
The validity of the read instruction data is determined, and if it is valid, an instruction read address signal is sent to the instruction buffer control unit 69 via the control line 70. The instruction buffer control unit 69 stores information from the control lines 62 and 63 indicating the amount of increase in the instruction address, adds an instruction read advance signal to this information, and outputs the input instruction signal of the instruction buffer register 67 and the instruction buffer. - Creates an input instruction signal for the register 68 and sends it to the control lines 71 and 72. That is,
The instruction read advance signal is set,
If the control line 62 is "1", it instructs input to either the instruction buffer register 67 or 68, whichever is in an empty state. Note that the empty state of the instruction buffer registers 67 and 68 is determined by the instruction buffer control unit 6.
9 manages and remembers.

On the other hand, if control line 63 is "1", it instructs input to both instruction buffer registers 67 and 68.

When instruction data is set in either instruction buffer register 67 or 68 and either instruction buffer register 73 or 74 is empty, the necessary one of control lines 75, 76, 77, and 78 is set. is set by the instruction buffer control unit 69 to move instruction data. In this case, the contents of the instruction buffer registers 73 and 74 are regarded as 16 consecutive bytes of instruction data, and are extracted by the selection circuit 79 in units of 2 bytes.

The operation of the selection circuit 79 is based on the instruction extraction pointer 5.
3. Instruction extraction pointer 53
receives the read start address information from the instruction stream control unit 2, and stores the position of the next instruction to be decoded. Then, the extracted instruction is input to the instruction register 18, and when the decoding of the instruction is completed, the pointer is incremented in accordance with the instruction length in order to fetch the next instruction. In other words, the instruction length is 2
When the instruction length is 6 bytes, the pointer is incremented by 1, and when the instruction length is 6 bytes, the instruction is decoded in two steps. After incrementing the pointer by 1, the pointer is then incremented by 2.

When the instruction decoding is completed, the instruction decoding control unit 19
sends out an instruction decoding end signal via the control line 80, and instructs the instruction extraction pointer 53 to perform an input operation to the instruction register 18 and increment the instruction extraction pointer.

The value of the step is determined by the output from the instruction decoder 20 and the state of the instruction decoding control section 19, and is determined by the control line 8.
1 or 82 controls the instruction extraction pointer incrementer 83. The value of the output latch 84 of the instruction extraction pointer incrementer, the instruction decoding completion signal on the control line 80, and the contents of the control lines 81 and 82 are also sent to the instruction buffer control unit 69. Instruction buffer control section 69 can detect the empty state of instruction buffer registers 73 and 74 based on these signals. In other words, instruction extraction pointer 5
The position indicated by 3 is the instruction buffer register 73
When moving from instruction buffer register 74 to 74, the instruction buffer register 73 is considered to be empty, and when moving from instruction buffer register 74 to 73, instruction buffer register 74 is assumed to be empty. I regard it as something.

When a branchable execution instruction or a branch instruction is set in the instruction register 18, the instruction reading operation of the B stream is started, and steps 151 to 151 in FIG.
The circuitry, data lines, and control lines shown at 185 are activated. The operation of the B stream is exactly the same as the operation of the circuits, data lines, and control lines indicated by 51 to 85 in the A stream described above, so the explanation will be omitted.

As described above, according to the present invention, by detecting the empty state of the instruction buffer register and feeding it back to the read address incrementer, the data width read from the buffer storage section can be made variable. Moreover, since the data can be read out continuously, the buffering efficiency of the data buffer register can be improved.

In the embodiment, a case has been described in which instruction data is read from the buffer storage device of the instruction control unit IU to the buffer register. It can be applied when reading data.

[Brief explanation of the drawing]

Figure 1 is a schematic block diagram of the information processing system.
Figure 2 is a diagram showing an example of the configuration of a buffer register.
FIG. 3 is a schematic block diagram of a buffer device of the present invention, FIG. 4 is a block diagram of an information processing device showing an embodiment of the present invention, and FIG. 5 is an explanatory diagram of the operation of FIG. 4. IU: Instruction control unit, EU: Arithmetic control unit, SCU: Storage control unit, IOP: Input/output processing unit, SVP: Service processing unit, CH: Channel device, MS: Main storage,
IAR: Instruction address register, AI: Address incrementer, AL: Address latch, IAC: Instruction address control section, IBR・A, IBR・B: Instruction buffer register, AD: Increaser, BM・E, BM・
O: Buffer storage unit, REG: Instruction register,
PT: pointer, IBC: instruction buffer control block,
LAC: logical address control section, 1: control line, 2:
instruction stream control section, 3: data line, 4: logical address control section, 5: logical address register,
6, 7: Buffer storage unit (E, O), 8: Address translation device, 9: Buffer index device, 10, 1
1: Buffer address register (E, O),
12, 13: Increase/decrease unit (E, O), 15: Buffer control unit, 18: Instruction register, 19: Instruction release control unit, 20: Instruction decoder, 52, 152: Instruction address register (A, B), 53, 153: Instruction extraction pointer (A, B), 54, 154: Instruction address control unit (A, B), 59, 159: Instruction address latch (A, B), 61, 161:
Instruction address incrementer (A, B), 67, 68, 7
3, 74, 167, 168, 173, 174: Instruction buffer register (A0 to A3, B0 to B
3), 69, 169: Instruction buffer control unit (A,
B), 79, 179: Selection circuit (A, B), 83,
183: Instruction extraction pointer incrementer (A, B),
84, 184: Output latch (A, B) of instruction extraction pointer incrementer.

Claims (1)

[Claims] 1. In an information processing device having a data buffering function, a buffer storage means having a maximum read width of n×m bytes, an address incrementer capable of increasing the amount of read address read from the buffer storage means is variable, and the buffer storage means means for detecting the free space of a buffer register for storing data read from the buffer register and feeding back the free space to the address incrementer; An information processing device characterized in that (l is 1 to m) a data width of bytes is selected to be read at one time.